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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
70 & \color{red} Note that decision to requeue is based on value of OLC {\it before} execution\\
72 & Added {\tt OLC=0} predicate \\
73 & Eliminated {\tt TAPL} (made possible by previous change) \\
74 & Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
76 & Fixed a few typos \\
77 & Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
78 & Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
80 & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
81 & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
83 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
84 & Reworked encoding of {\tt set} instruction \\
87 & Factored in Russell Kao's comments (thanks!)\\
88 & Added mechanism for setting C-flag from fabric even on outboxes\\
90 & Made {\tt OLC} test a predicate-controlled condition\\
91 & Rewrote ``on deck'' section \\
92 & Added ``{\tt unset}'' value for {\tt ILC}\\
93 & Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
96 & added comment about address-to-path ship \\
97 & changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
98 & changed the order of instructions in the encoding map \\
100 & added epilogue fifo to diagrams \\
101 & indicated that a token sent to the instruction port is treated as a torpedo \\
103 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
104 %& replaced {\tt literal} with {\tt shift} instruction \\
106 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
107 %& Removed ability to manually set the {\tt C} flag \\
108 %& Expanded predicate field to three bits \\
109 %& New literals scheme (via shifting) \\
110 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
111 %& Added summary of instruction encodings on last page \\
113 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
115 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
116 %& update table 3.1.2 \\
117 %& rename {\tt S} flag to {\tt C} \\
118 %& noted that {\tt setFlags} can be used as {\tt nop} \\
120 %& removed the {\tt L} flag (epilogues can now do this) \\
121 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
122 %& renamed {\tt data} instruction to {\tt literal} \\
123 %& renamed {\tt send} instruction to {\tt move} \\
125 %& added ``if its predicate is true'' to repeat count \\
126 %& added note that red wires do not contact ships \\
127 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
128 %& removed black dot from diagrams \\
129 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
130 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
131 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
132 %& added section ``Torpedo Details'' \\
133 %& removed {\tt torpedo} instruction \\
136 %& renamed loop+repeat to outer+inner (not in red) \\
137 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
138 %& rewrote ``inner and outer loops'' section \\
139 %& updated all diagrams \\
142 %& Moved address bits to the LSB-side of a 37-bit instruction \\
143 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
144 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
145 %& Created the {\tt Hold} field \\
146 %& Changed how ReLooping works \\
147 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
154 \epsfig{file=all,height=1.5in}
155 \epsfig{file=overview-new,height=1.5in}
160 \section{Overview of Fleet}
162 A Fleet processor is organized around a {\it switch fabric}, which is
163 a packet-switched network with reliable in-order delivery. The switch
164 fabric is used to carry data between different functional units,
165 called {\it ships}. Each ship is connected to the switch fabric by
166 one or more programmable elements known as {\it docks}.
168 A {\it path} specifies a route through the switch fabric from a
169 particular {\it source} to a particular {\it destination}. The
170 combination of a path and a single word to be delivered is called a
171 {\it packet}. The switch fabric carries packets from their sources to
172 their destinations. Each dock has two destinations: one for {\it
173 instructions} and one for {\it data}. A Fleet is programmed by
174 depositing instruction packets into the switch fabric with paths that
175 will lead them to instruction destinations of the docks at which they
178 When a packet arrives at the instruction destination of a dock, it is
179 enqueued for execution. Before the instruction executes, it may cause
180 the dock to wait for a packet to arrive at the dock's data destination
181 or for a value to be presented by the ship. When an instruction
182 executes it may consume this data and may present a data value to the
183 ship or transmit a packet.
185 When an instruction sends a packet into the switch fabric, it may
186 specify that the payload of the packet is irrelevant. Such packets
187 are known as {\it tokens}, and consume less energy than data packets.
191 \epsfig{file=overview-new,width=2.5in}\\
192 {\it Overview of a Fleet processor; dark gray shading represents the
193 switch fabric, ships are shown in light gray, and docks are shown in blue.}
199 \section{The FleetTwo Dock}
201 The diagram below represents a conceptual view of the interface
202 between ships and the switch fabric; actual implementation circuitry
206 \epsfig{file=all,width=3.5in}\\
207 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
208 blue lines carry either tokens or data words, red lines carry either
209 instructions or torpedoes, and dashed lines carry only tokens.}
212 Each dock consists of a {\it data latch}, which is as wide as a single
213 machine word and a {\it pump}, which is a circular fifo of
214 instruction-width latches. The values in the pump control the data
215 latch. The dock also includes a {\it path latch}, which
216 stores the path along which outgoing packets will be sent.\color{black}
218 Note that the pump in each dock has a destination of its own; this is
219 the {\it instruction destination} mentioned in the previous section.
221 From any source to any dock's data destination there are
222 two distinct paths which differ by a single bit. This bit is known as
223 the ``signal'' bit, and the routing of a packet is not affected by it;
224 the signal bit is used to pass control values between docks. Note that paths
225 terminating at an {\it instruction} destination need not have a signal
229 \section{Instructions}
231 In order to cause an instruction to execute, the programmer must first
232 arrange for that instruction word to arrive in the data latch of some
233 output dock. For example, this might be the ``data read'' output dock
234 of the memory access ship or the output of a fifo ship. Once an
235 instruction has arrived at this output dock, it is {\it dispatched} by
236 sending it to the {\it instruction port} of the dock at which it is to
239 Each instruction is 26 bits long, which makes it possible for an
240 instruction and an 11-bit path to fit in a single word of memory.
241 This path is the path from the {\it dispatching} dock to the {\it
244 \setlength{\bitwidth}{3.5mm}
246 \begin{bytefield}{37}
247 \bitheader[b]{0,10,11,36}\\
248 \bitbox{26}{instruction}
249 \bitbox{11}{dispatch path}
255 \subsection{Life Cycle of an Instruction}
257 The diagram below shows an input dock for purposes of illustration:
260 \epsfig{file=in,width=4in}\\
264 Note the mux on the path between {\tt EF} (epilogue fifo) and {\tt IF}
265 (instruction fifo); this is known as ``the hatch''. The hatch has two
266 states: sealed and unsealed. When the machine powers up, the hatch is
267 unsealed; it is sealed by the {\tt tail} instruction and unsealed
268 whenever the outer loop counter is set to zero (for any
269 reason\footnote{this includes {\tt OLC} being decremented to zero, a
270 {\tt set} instruction, or the occurrence
273 When an instruction arrives at the epilogue fifo ({\tt EF}), it waits
274 there until the hatch is in the unsealed state; the instruction then
275 enters the instruction fifo. When an instruction emerges from the
276 instruction fifo, it arrives at the ``on deck'' ({\tt OD}) stage,
277 where it may execute.
280 \epsfig{file=out,width=4in}\\
284 \subsubsection{Torpedoes}
286 A token sent to an instruction destination is called a {\it torpedo}.
287 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
288 waiting area (not shown) rather than being enqueued into {\tt EF}.
290 \subsection{Format of an Instruction}
292 All instruction words have the following format:
294 \newcommand{\bitsHeader}{
299 \newcommand{\bitsHeaderNoI}{
305 \setlength{\bitwidth}{3.5mm}
307 \begin{bytefield}{37}
308 \bitheader[b]{0,10,11,31,32,34-36}\\
313 \bitbox{11}{dispatch path}
318 \item The {\tt I} bit stands for {\tt Interruptible}, and indicates if an
319 instruction is vulnerable to torpedoes. This bit only appears in {\tt move} instructions.
321 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
322 instruction can pass through the pump more than once. If set to
323 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
324 does not pass through the instruction fifo more than once.
326 \item The {\tt P} bits are a {\it predicate}; this
327 holds a code which indicates if the instruction should be executed or
328 ignored depending on the state of flags in the dock.
332 \subsection{Loop Counters}
334 A programmer can perform two types of loops: {\it inner} loops of only
335 one instruction and {\it outer} loops of multiple instructions. Inner
336 loops may be nested within an outer loop, but no other nesting of
339 The dock has two loop counters, one for each kind of loop:
342 \item {\tt OLC} is the Outer Loop Counter
343 \item {\tt ILC} is the Inner Loop Counter
346 The {\tt OLC} applies to all instructions and can hold integers {\tt
349 The {\tt ILC} applies only to {\tt move} instructions and can hold
350 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
351 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
352 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
353 executes until interrupted by a torpedo. After every {\tt move}
354 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
355 to {\tt 1}, {\it not to 0}).
358 \subsection{Flags and Predication}
360 The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
363 \item The {\tt A} and {\tt B} flags are general-purpose flags which
364 may be set and cleared by the programmer.
368 % The {\tt L} flag, known as the {\it last} flag, is set whenever
369 % the value in the outer counter ({\tt OLC}) is one,
372 % that the dock is in the midst of the last iteration of an
373 % outer loop. This flag can be used to perform certain
374 % operations (such as sending a completion token) only on the last
375 % iteration of an outer loop.
377 \item The {\tt C} flag is known as the {\it control} flag, and may be
378 set by the {\tt move} instruction based on information from the
379 ship or from an inbound packet. See the {\tt move} instruction
385 The {\tt P} field specifies a three-bit {\it predicate}. The
386 predicate determines which conditions must be true in order for the
387 instruction to execute; if it is not executed, it is simply {\it
388 ignored}. The table below shows what conditions must be true in
389 order for an instruction to execute:
392 \begin{tabular}{|r|ll|}\hline
393 Code & Execute & if \\\hline
394 {\tt 000:} & {\tt OLC$\neq$0} & and {\tt A=0} \\
395 {\tt 001:} & {\tt OLC$\neq$0} & and {\tt A=1} \\
396 {\tt 010:} & {\tt OLC$\neq$0} & and {\tt B=0} \\
397 {\tt 011:} & {\tt OLC$\neq$0} & and {\tt B=1} \\
398 {\tt 100:} & Unused & \\
399 {\tt 101:} & {\tt OLC=0} & \\
400 {\tt 110:} & {\tt OLC$\neq$0} & \\
401 {\tt 111:} & always & \\
408 When an instruction arrives on deck, two concurrent processes are
409 started. No subsequent instruction may come on deck until both
410 processes have completed:
416 \item If the outer loop counter is zero ({\tt OLC=0})
417 \color{red}{\it before executing the
418 instruction}\color{black}\ or the instruction on deck is a
419 one-shot instruction ({\tt OS=1}), do nothing.
420 \item {\it Otherwise} wait for the hatch to be sealed and
421 enqueue a copy of the instruction currently on deck.
428 If the instruction's predicate condition is not met (see
429 section on predicates), do nothing.
432 {\it Otherwise} if the instruction is interruptible ({\tt I=0})
433 and a torpedo is present in the waiting area: consume the
434 torpedo, set the outer loop counter to zero ({\tt OLC=0}),
435 set the inner loop counter to one ({\tt ILC=1}),
439 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
440 not} a {\tt move}: execute the instruction.
449 \section{Instructions}
451 The dock supports four instructions:
452 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
459 \subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
461 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
463 \begin{bytefield}{26}
464 \bitheader[b]{14-20}\\
478 \begin{bytefield}{26}
479 \bitheader[b]{0,12,13}\\
480 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
483 \bitbox{13}{\tt Immediate}
486 \begin{bytefield}{26}
487 \bitheader[b]{11,12,13}\\
488 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
497 \begin{bytefield}{26}
498 \bitheader[b]{11,12,13}\\
499 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
510 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
511 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
512 \item {\tt Dc} - Data Capture: pulse the data latch.
513 \item {\tt Do} - Data Output: fill the data successor.
514 \item {\tt To} - Token Output: fill the token successor.
517 The data successor and token successor must both be empty in order for
518 a {\tt move} instruction to attempt execution.
520 Every time the {\tt move} instruction executes, the {\tt C} flag may
524 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
525 of the incoming packet if {\tt Di} or {\tt Ti} is set.
527 \item At an {\it output} dock the {\tt C} flag is set to a value
528 provided by the ship if the {\tt Di} bit is set, and to the
529 signal bit of the incoming packet if {\tt Di} is clear and {\tt
537 \subsection{{\tt set}}
539 The {\tt set} command is used to set or decrement the inner loop
540 counter, outer loop counter, and data latch.
542 \newcommand{\bitsSet}{
543 \setlength{\bitwidth}{5mm}
545 \begin{bytefield}{26}
546 \bitheader[b]{19-25}\\
556 \begin{bytefield}{26}
557 \bitheader[b]{0,5,12-18}\\
558 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
560 \bitbox{4}{\tt 1000\color{black}}
563 \bitbox{6}{\tt Immediate}
566 \begin{bytefield}{26}
567 \bitheader[b]{12-18}\\
568 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
570 \bitbox{4}{\tt 1000\color{black}}
575 \begin{bytefield}{26}
576 \bitheader[b]{12-18}\\
577 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
579 \bitbox{4}{\tt 1000\color{black}}
584 \begin{bytefield}{26}
585 \bitheader[b]{0,5,6,12-18}\\
586 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
588 \bitbox{4}{\tt 0100\color{black}}
592 \bitbox{6}{\tt Immediate}
595 \begin{bytefield}{26}
596 \bitheader[b]{6,12-18}\\
597 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
599 \bitbox{4}{\tt 0100\color{black}}
606 \begin{bytefield}{26}
607 \bitheader[b]{12-18}\\
608 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
610 \bitbox{4}{\tt 0100\color{black}}
615 \begin{bytefield}{26}
616 \bitheader[b]{0,13-18}\\
617 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 0-Extended Immediate}\to{\tt Data Latch}}
619 \bitbox{4}{\tt 0010\color{black}}
621 \bitbox{14}{\tt Immediate}
624 \begin{bytefield}{26}
625 \bitheader[b]{0,13-18}\\
626 \bitbox[1]{6}{\raggedleft \footnotesize {\tt 1-Extended Immediate}\to{\tt Data Latch}}
628 \bitbox{4}{\tt 0010\color{black}}
630 \bitbox{14}{\tt Immediate}
633 \begin{bytefield}{26}
634 \bitheader[b]{0,5,6,11,15-18}\\
635 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
637 \bitbox{4}{\tt 0001\color{black}}
639 \bitbox{6}{\tt nextA}
640 \bitbox{6}{\tt nextB}
649 The FleetTwo implementation is likely to have an unarchitected
650 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
651 with the possibly-extended literal {\it at the time that the {\tt set}
652 instruction comes on deck}. This latch is then copied into the data
653 latch when a {\tt set Data Latch} instruction
654 executes\color{black}.
656 Each of the {\tt nextA} and {\tt nextB} fields has the following
657 structure, and indicates which old flag values should be logically
658 {\tt OR}ed together to produce the new flag value:
664 \bitbox{1}{${\text{\tt A}}$}
665 \bitbox{1}{$\overline{\text{\tt A}}$}
666 \bitbox{1}{${\text{\tt B}}$}
667 \bitbox{1}{$\overline{\text{\tt B}}$}
668 \bitbox{1}{${\text{{\tt C}\ }}$}
669 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
673 Each bit corresponds to one possible input; all inputs whose bits are
674 set are {\tt OR}ed together, and the resulting value is assigned to
675 the flag. Note that if none of the bits are set, the value assigned
676 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
677 OR}ing any flag with its complement, and that {\tt set Flags} can
678 be used to create a {\tt nop} (no-op) by setting each flag to itself.
684 \subsection{{\tt shift}}
686 \newcommand{\shiftImmediateSize}{19}
688 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
689 bits. When a {\tt shift} instruction is executed, this immediate is copied
690 into the least significant \shiftImmediateSize\ bits of the data latch,
691 and the remaining most significant bits of the data latch are loaded
692 with the value formerly in the least significant bits of the data latch.
693 In this manner, large literals can be built up by ``shifting'' them
694 into the data latch \shiftImmediateSize\ bits at a time.
696 \newcommand{\bitsShift}{
697 \setlength{\bitwidth}{5mm}
699 \begin{bytefield}{26}
700 \bitheader[b]{0,18-20}\\
707 \bitbox{\shiftImmediateSize}{Immediate}
712 The FleetTwo implementation is likely to have an unarchitected
713 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
714 with the literal {\it at the time that the {\tt shift} instruction
715 comes on deck}. This latch is then copied into the data latch when
716 the instruction executes.
720 \subsection{{\tt tail}}
722 \newcommand{\bitsTail}{
723 \setlength{\bitwidth}{5mm}
725 \begin{bytefield}{26}
726 \bitheader[b]{19-20}\\
737 When a {\tt tail} instruction reaches the hatch, it seals the hatch.
738 The {\tt tail} instruction does not enter the instruction fifo.
742 %\subsection{{\tt takeOuterLoopCounter}}
744 %\setlength{\bitwidth}{5mm}
746 %\begin{bytefield}{26}
747 % \bitheader[b]{16-19,21}\\
761 %This instruction copies the value in the outer loop counter {\tt OLC}
762 %into the least significant bits of the data latch and leaves all other
763 %bits of the data latch unchanged.
765 %\subsection{{\tt takeInnerLoopCounter}}
767 %\setlength{\bitwidth}{5mm}
769 %\begin{bytefield}{26}
770 % \bitheader[b]{16-19,21}\\
784 %This instruction copies the value in the inner loop counter {\tt ILC}
785 %into the least significant bits of the data latch and leaves all other
786 %bits of the data latch unchanged.
791 %%\subsection{{\tt interrupt}}
793 %%\setlength{\bitwidth}{5mm}
795 %\begin{bytefield}{26}
796 % \bitheader[b]{0,5,16-19,21}\\
807 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
808 %there for the {\tt OD} stage to be full with an instruction that has
809 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
810 %{\it will not execute}, but {\it may reloop} if the conditions for
812 %\footnote{The ability to interrupt an instruction yet have it reloop is very
813 %useful for processing chunks of data with a fixed size header and/or
814 %footer and a variable length body.}
817 %\subsection{{\tt massacre}}
819 %\setlength{\bitwidth}{5mm}
821 %\begin{bytefield}{26}
822 % \bitheader[b]{16-19,21}\\
834 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
835 %for the {\tt OD} stage to be full with an instruction that has the
836 %{\tt IM} bit set. When this occurs, all instructions in the
837 %instruction fifo (including {\tt OD}) are retired.
839 %\subsection{{\tt clog}}
841 %\setlength{\bitwidth}{5mm}
843 %\begin{bytefield}{26}
844 % \bitheader[b]{16-19,21}\\
856 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
857 %no more instructions will be executed until an {\tt unclog} is
860 %\subsection{{\tt unclog}}
862 %\setlength{\bitwidth}{5mm}
864 %\begin{bytefield}{26}
865 % \bitheader[b]{16-19,21}\\
871 % \bitbox[lrtb]{2}{11}
877 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
878 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
879 %instructions retire.
881 %Note that issuing an {\tt unclog} instruction to a dock which is not
882 %clogged and whose instruction fifo contains no {\tt clog} instructions
883 %will cause the dock to deadlock.
888 \section*{Instruction Encoding Map\color{black}}
890 \hspace{-1cm}{\tt shift}\\
893 \hspace{-1cm}{\tt set}\\
896 \hspace{-1cm}{\tt move}\\
899 \hspace{-1cm}{\tt tail}\\
906 \epsfig{file=all,height=5in,angle=90}
909 \subsection*{Input Dock}
910 \epsfig{file=in,width=8in,angle=90}
913 \subsection*{Output Dock}
914 \epsfig{file=out,width=8in,angle=90}
918 %\epsfig{file=ports,height=5in,angle=90}
921 %\epsfig{file=best,height=5in,angle=90}