[fleet.git] / am33.tex

\documentclass[10pt]{article}
\usepackage{palatino}
\usepackage{amsmath}
\usepackage{epsfig}
\usepackage{color}
\usepackage{bytefield1}
\usepackage{wrapfig}
\usepackage{stmaryrd}
\usepackage{subfigure}
\usepackage{syntax}
\usepackage{comment}
\usepackage{fancyhdr}
\usepackage{lastpage}
\usepackage{multirow}
\usepackage{multicol}
\usepackage{rotating}
\include{megacz}
\bibliographystyle{alpha}
\pagestyle{fancyplain}

\definecolor{light}{gray}{0.7}

\newcommand{\footnoteremember}[2]{
  \footnote{#2}
  \newcounter{#1}
  \setcounter{#1}{\value{footnote}}
} \newcommand{\footnoterecall}[1]{
  \footnotemark[\value{#1}]
}

%\pdfpagewidth 8.5in
%\pdfpageheight 11in 
%\topmargin 0in
%\textheight 7.5in
%\textwidth 6.0in
%\oddsidemargin 0.25in
%\evensidemargin 0.25in
%\headwidth 6.0in
\def\to{\ $\rightarrow$\ }

\def\docnum{AM33}

\author{
\normalsize{
\begin{tabular}{c}
\end{tabular}}
}

\title{\vspace{-1cm}The FleetTwo Dock}

\begin{document}

\maketitle

\begin{abstract}
Changes:

\begin{tabular}{rl}
\color{red}
29-Mar
\color{black}
& removed the {\tt L} flag (epilogues can now do this) \\
& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
& renamed {\tt data} instruction to {\tt literal} \\
& renamed {\tt send} instruction to {\tt move} \\
\color{red}
23-Mar
\color{black}
& added ``if its predicate is true'' to repeat count \\
& added note that red wires do not contact ships \\
& changed name of {\tt flags} instruction to {\tt setFlags} \\
& removed black dot from diagrams \\
& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
& indicated that only {\tt send} instructions which wait for data are torpedoable \\
& added section ``Torpedo Details'' \\
& removed {\tt torpedo} instruction \\
12-Mar
\color{black}
& renamed loop+repeat to outer+inner (not in red) \\
& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
& rewrote ``inner and outer loops'' section \\
& updated all diagrams \\
\color{black}
7-Mar
& Moved address bits to the LSB-side of a 37-bit instruction \\
& Added {\it micro-instruction} and {\it composite instruction} terms \\
& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
& Created the {\tt Hold} field \\
& Changed how ReLooping works \\
& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
\end{tabular}
\end{abstract}

\vfill

\begin{center}
\epsfig{file=overview,width=1.5in}
\epsfig{file=indock,width=3in}
\end{center}

\pagebreak

\section{Overview of Fleet}

A Fleet processor consists of a {\it switch fabric} with several
functional units called {\it ships} connected to it.  At each
connection between a ship and the switch fabric lies a programmable
element known as the {\it dock}.

A {\it path} specifies a route through the switch fabric from a
particular {\it source} to a particular {\it destination}.  The
combination of a path and a single word {\it payload} is called a {\it packet}.  The
switch fabric carries packets from their sources to their
destinations.  Each dock has two destinations: one for {\it
  instructions} and one for {\it data}.  A Fleet is programmed by
depositing packets into the switch fabric; these packets' paths lead
them to the instruction destinations of the docks.

When a packet arrives at the instruction destination of a dock, it is
enqueued for execution.  Before the instruction executes, it may cause
the dock to wait for a packet to arrive at the dock's data destination
or for a value to be presented by the ship.  It may present a data
value to the ship or transmit it for transmission to some other
destination.

When an instruction sends a packet into the switch fabric, it may
specify that the payload of the packet is irrelevant.  Such packets
are known as {\it tokens}, and consume less energy than data packets.
From a programmer's perspective, a token packet is indistinguishable
from a data packet with a unknown payload.

\color{red}
In the diagram below, the red wires carry instructions and the blue
wires carry data; the switch fabric (gray area) carries both.  Notice
that the red (instruction) wires do not contact the ships.  This is an
advantage: ships are designed without any consideration for the
instructions used to program their docks.
\color{black}

\begin{center}
\epsfig{file=overview,width=2.5in}\\
{\it Overview of a Fleet processor; gray shading represents a
  packet-switched network fabric; blue lines carry data, red lines
  carry instructions.}
\end{center}
\color{black}

\pagebreak

\section{The FleetTwo Pump}

The diagram below represents a {\it programmer's} conceptual view of
the interface between ships and the switch fabric.  Actual
implementation circuitry may differ substantially.  Sources and
destinations that can send and receive only tokens -- not data items
-- are drawn as dashed lines.

\begin{center}
\epsfig{file=indock,width=3.5in}\\
{\it an ``input'' dock}

\epsfig{file=outdock,width=3.5in}\\
{\it an ``output'' dock}
\end{center}

The term {\it port} refers to an interface to the ship, the {\it
  dock} connecting it to the switch fabric, and the corresponding
sources and destinations on the switch fabric.

Each dock consists of a {\it data latch}, which is as wide as a single
machine word and a {\it pump}, which is a circular fifo of
instruction-width latches.  The values in the pump control the data
latch.

Note that the pump in each dock has a destination of its own; this is
the {\it instruction destination} mentioned in the previous section.
Note that unlike all other destinations, there is no buffering fifo
guarding this one.  The size of these fifos are exposed to the
software programmer so he can avoid deadlock.

\pagebreak
\section{Instructions}

In order to cause an instruction to execute, the programmer must first
cause that instruction word to arrive in the data latch of some output
dock.  For example, this might be the ``data read'' output dock of the
memory access ship or the output of a fifo ship.  Once an instruction
has arrived at this output dock, it is {\it dispatched} by sending it
to the {\it instruction port} of the dock at which it is to execute.

Each instruction is 26 bits long, which makes it possible for an
instruction and an 11-bit path to fit in a single word of memory.
This path is the path from the {\it dispatching} dock to the {\it
  executing} dock.

\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
  \bitheader[b]{0,10,11,36}\\
  \bitbox{26}{instruction} 
  \bitbox{11}{dispatch path} 
\end{bytefield}}

{\bf Note:} the instruction encodings below are simply ``something to
shoot at'' and a sanity check to make sure we haven't overrun our bit
budget.  The final instruction encodings will probably be
different.

All instruction words have the following format:

\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
  \bitheader[b]{0,10,11,36}\\
\color{black}
  \bitbox{1}{\color{red}I\color{black}} 
  \bitbox{1}{\color{red}OS\color{black}} 
  \bitbox{2}{P} 
\color{light}
  \bitbox[tbr]{22}{} 
  \bitbox{11}{dispatch path} 
\color{black}
\end{bytefield}}

Each instruction word is called a {\it micro instruction}.
Collections of one or more micro instruction are known as {\it
  composite instructions}.

\color{red}
The {\tt I} bit stands for {\tt Interruptible}\color{black}.  The \color{red}{\tt OS}
(``One Shot'')\color{black}\ bit indicates whether or not this instruction is part
of an outer loop.  Both of the preceding bits are explained in the
next section.

\color{black}

The abbreviation {\tt P} stands for {\it predicate}; this is a two-bit
code that indicates if the instruction should be executed or ignored.



\pagebreak
\subsection{Life Cycle of an Instruction}

The diagram below shows an input dock for purposes of illustration
(behavior at an output dock is identical).

\begin{center}
\epsfig{file=indock,width=3in}\\
{\it an input dock}
\end{center}

Note the circle on the path between ``instr horn'' and ``instr fifo'';
this is known as ``the hatch''.  The hatch has two states: sealed and
unsealed.  When the machine powers up, the hatch is unsealed; it is
sealed by the {\tt tail} instruction and unsealed \color{red}whenever
the outer loop counter is set to zero (for any
reason\footnote{\color{red}this includes {\tt OLC} being decremented
  to zero, a {\tt setOuter} with a literal field of zero, a {\tt
    setOuter} which copies a zero from the data register to {\tt OLC},
  or the occurrence of a torpedo\color{black}}).\color{black}

When an instruction arrives at the instruction horn, it waits there
until the hatch is in the unsealed state.  The instruction then enters
the instruction fifo.  When an instruction emerges from the
instruction fifo, it arrives at the ``on deck'' stage, where it may
execute.

\subsubsection{Inner and Outer Loops}

A programmer can perform two types of loops: {\it inner} loops of only
one micro-instruction and {\it outer} loops of multiple
micro-instructions.  Inner loops may be nested within an outer loop,
but no other nesting of loops is allowed.  The paths used by inner
loops and outer loops are shown below:

\begin{center}
\begin{minipage}{2in}
\begin{center}
\epsfig{file=inner-loop,width=2in}\\
{\it inner loop (in red)}
\end{center}
\end{minipage}
\begin{minipage}{2in}
\begin{center}
\epsfig{file=outer-loop,width=2in}\\
{\it outer loop (in red)}
\end{center}
\end{minipage}
\end{center}

\color{red}

Each type of loop has a counter associated with it: the {\tt ILC}
counter for inner loops and the {\tt OLC} counter for outer loops.
The inner loop counter applies only to certain ``inner-looping''
instructions (see the table below for details).  When such an
instruction reaches On Deck, if its predicate is true it will execute
a number of times equal to {\tt ILC+1}, and leave {\tt ILC=0} after
executing.  Non-inner-looping instructions and instructions whose
predicate is false do not decrement {\tt ILC}.

The outer loop counter applies to all instructions {\it except} the
instruction {\tt setOuter} with {\tt OS=1}, because such instructions
are needed to reset the outer loop counter after it becomes zero.
However, predicated {\tt setOuter} with {\tt OS=0} is useful for
resetting the loop counter in the middle of the execution of a loop.

\color{black}

\subsubsection{On Deck}
\color{red} The
table below lists the actions which may be taken when an
instruction arrives on deck:

\begin{center}
\def\side#1{\begin{sideways}\parbox{15mm}{#1}\end{sideways}}
\begin{tabular}{|r|ccccc|cccccc|}\hline
%&\multicolumn{10}{c}{Predicate}&\\
%&\multicolumn{10}{c}{True}&\\\hline
&\multicolumn{5}{c}{Outer-Looping} &\multicolumn{5}{c}{One-Shot}&\\
&\multicolumn{5}{c}{{\tt (OS=0)}} &\multicolumn{5}{c}{{\tt (OS=1)}}&\\
&\side{{\tt move}}
&\side{{\tt literal}}
&\side{{\tt setFlags}}
&\side{{\tt setInner}}
&\side{{\tt setOuter}}
&\side{{\tt move}}
&\side{{\tt literal}}
&\side{{\tt setFlags}}
&\side{{\tt setInner}}
&\side{{\tt setOuter}}
&
\\\hline
Wait for hatch sealed         & +        & + & + & + & +  &          &   &   &   &   &  \\
Fill IF0 w/ copy of self      & +        & + & + & + & +  &          &   &   &   &   &  \\\hline
Request arbiter               & P+$\star$ &   &   &   &    & P+$\star$ &   &   &   &   &  \\
Potentially torpedoable       & P+$\star$ &   &   &   &    & P+$\star$ &   &   &   &   &  \\\hline
Execute                       & P+       & P+& P+& P+& P+ & ?        & ? & ? & ? & P &  \\
Inner-looping                 & P+       &   &   &   & ?  & P+       &   &   &   & ? &  \\
\hline
\end{tabular}

\begin{tabular}{|r|l|}\hline
+       & Only if {\tt OLC>0} (ie {\tt OLC} is positive) \\
P       & Only if predicate is true \\
P+      & Only if predicate is true and {\tt OLC>0} \\
P+$\star$ & Only if predicate is true and {\tt OLC>0} and {\tt I=1} and one of {\tt Ti},{\tt Di},{\tt Do} true. \\
?       & to discuss \\\hline
\end{tabular}
\end{center}

\subsubsection{\color{red}Torpedo\color{black}}

\color{red}
There is a small fifo (not shown) before the latch marked
``Instruction Horn''; after the {\tt tail} instruction seals the
hatch, any subsequent instructions will queue up in this fifo until
the hatch is unsealed.  This is typically used as storage for a ``loop
epilogue'' -- a sequence of instructions to be executed after a
torpedo arrives or the outer loop counter expires.

Each dock has a fourth connection to the switch fabric (not shown),
called its {\it torpedo destination}.  Anything (even a token) sent to
this destination is treated as a torpedo.  Note that because this is a
distinct destination, instructions or data queued up in the other
destination fifos will not prevent a torpedo from occuring.

When a data item or token arrives at the torpedo destination, it lies
there in wait until On Deck holds a potentially torpedoable
instruction (see previous table).  Once this is the case, the torpedo
causes the inner and outer loop counters to be set to zero (and
therefore also unseals the hatch).\footnote{it is unspecified whether
  the torpedoed instruction is requeued or not; this may or may not
  occur, nondeterministically.  It is the programmer's responsibility
  to ensure that the program behaves the same whether this happens or
  not.  We think that this will not matter in most situations.}

\color{black}


\subsection{Flags}

The pump has \color{red}three\color{black}\ flags: {\tt A}, {\tt B},
and {\tt S}.

\begin{itemize}
\item The {\tt A} and {\tt B} flags are general-purpose flags which
      may be set and cleared by the programmer.

%\item
%
% The {\tt L} flag, known as the {\it last} flag, is set whenever
%      the value in the outer counter ({\tt OLC}) is one,
\color{black}
% indicating
%      that the dock is in the midst of the last iteration of an
%      outer loop.  This flag can be used to perform certain
%      operations (such as sending a completion token) only on the last
%      iteration of an outer loop.

\item The {\tt S} flag, known as the {\it summary} flag.  Its value is
      determined by the ship, but unless stated otherwise, it should
      be assumed that whenever the 37th bit of the data ({\tt D})
      latch is loaded, that same bit is also loaded into the {\tt S}
      flag.  This lets the ship make decisions based on whether or not
      the top bit of the data latch is set; if two's complement
      numbers are in use, this will indicate whether or not the
      latched value is negative.
\end{itemize}

Many instruction fields are specified as two-bit {\it predicates}.
These fields contain one of four values, indicating if an action
should be taken unconditionally or conditionally on one of the {\tt A}
or {\tt B} flags:

\begin{itemize}
\item {\tt 00:} if {\tt A} is set
\item {\tt 10:} if {\tt B} is set
\item {\tt 01:} \color{red}TBD\color{black}
\item {\tt 11:} always
\end{itemize}


\pagebreak
\section{Instructions}

\color{red}

Here is a list of the instructions supported by the dock:

\begin{center}
\begin{tabular}{|l|}\hline
{\tt move} (variants: {\tt moveto}, {\tt dispatch}) \\
{\tt literal} (variants: {\tt literalhi}, {\tt literallo})\\
{\tt setFlags} \\
{\tt setInner} \\
{\tt setOuter} \\
%{\tt torpedo} \\
{\tt tail} \\\hline
\end{tabular}
\end{center}

{\tt tail} {\it will probably become a bit on every instruction rather than
  its own instruction}

\color{black}


\subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{12-16,19,21}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS}
  \bitbox{2}{P}
\color{black}
   \bitbox{3}{001} 
\color{light}
  \bitbox[trb]{2}{} 
\color{black}
  \bitbox{1}{\tt Ti}
  \bitbox{1}{\tt Di}
  \bitbox{1}{\tt Dc}
  \bitbox{1}{\tt Do}
  \bitbox{1}{\tt To}
  \bitbox[l]{17}{}
\end{bytefield}}

%\begin{bytefield}{26}
%  \bitheader[b]{12-18}\\
%  \bitbox[]{8}{\raggedleft Input Dock:}
%  \bitbox[r]{2}{}
%  \bitbox{1}{\tt So} 
%  \bitbox{1}{\tt Dc}
%  \bitbox[l]{15}{}
%\end{bytefield}
%
%\begin{bytefield}{26}
%  \bitheader[b]{12-18}\\
%  \bitbox[]{8}{\raggedleft Output Dock:}
%  \bitbox[r]{2}{}
%  \bitbox{1}{\tt Si}
%  \bitbox{1}{\tt To}
%  \bitbox[l]{15}{}
%\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,10,11}\\
  \bitbox[1]{13}{\raggedleft {\tt moveto} ({\tt LiteralPath\to Path})}
  \bitbox[r]{1}{}
  \bitbox{1}{\tt 1}
  \bitbox{11}{\tt LiteralPath}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{10,11}\\
  \bitbox[1]{13}{\raggedleft {\tt dispatch} ({\tt DP[37:27]\to Path})\ \ }
  \bitbox[r]{1}{}
  \bitbox{1}{\tt 0}
  \bitbox{1}{\tt 1}
\color{light}
  \bitbox[trb]{10}{}
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{10,11}\\
  \bitbox[1]{13}{\raggedleft {\tt move} ({\tt Path} unchanged):}
  \bitbox[r]{1}{}
  \bitbox{1}{\tt 0}
  \bitbox{1}{\tt 0}
\color{light}
  \bitbox[trb]{10}{}
\color{black}
\end{bytefield}

\begin{itemize}
\item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
\item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
\item {\tt Dc} - Data Capture: pulse the data latch.
\item {\tt Do} - Data Output: fill the data successor.
\item {\tt To} - Token Output: fill the token successor.
\end{itemize}

The data successor and token successor must both be empty in order for
a {\tt move} instruction to attempt execution.

The inner loop counter can hold a number {\tt 0..MAX} or a special
value $\infty$.  If {\tt ILC} is nonzero after execution of a {\tt
  move} instruction, the instruction will execute again, and {\tt ILC}
will be latched with {\tt (ILC==$\infty$?$\infty$:max(ILC-1, 0))}.  When
the inner loop counter reaches zero, the instruction ceases executing.


\pagebreak
\subsection{{\tt literal}, {\tt literalhi}, {\tt literallo}}

These instructions load part or all of the data latch ({\tt D}).

{\tt literalhi: Literal[18:1]\to D[37:20]} (and {\tt Literal[18]\to S})

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,18,19,21}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS} 
  \bitbox{2}{P}
\color{black}
  \bitbox{1}{0} 
  \bitbox{2}{11} 
\color{light}
  \bitbox[trb]{1}{} 
\color{black}
  \bitbox{18}{Literal} 
\end{bytefield}}

{\tt literallo: Literal[19:1]\to D[19:1]}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,18,19,21}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS} 
  \bitbox{2}{P}
\color{black}
  \bitbox{1}{0} 
  \bitbox{2}{10} 
  \bitbox{19}{Literal} 
\end{bytefield}}

{\tt literal:}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,18,19,21}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS} 
  \bitbox{2}{P}
\color{black}
  \bitbox{1}{1} 
  \bitbox{2}{SEL} 
  \bitbox{19}{Literal} 
\end{bytefield}}

{\tt
\begin{tabular}{|r|c|c|c|}\hline
sel  & D[37:20]      & D[19:1]       \\\hline
00  & Literal[18:1] & all 0         \\
01  & Literal[18:1] & all 1         \\
10  & all 0         & Literal[19:1] \\
11  & all 1         & Literal[19:1] \\
\hline
\end{tabular}}




\subsection{
\color{red}
{\tt setFlags}
\color{black}
}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,7,8,15,16-19,21}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS} 
  \bitbox{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{0}
\color{red}
  \bitbox{6}{nextA}
  \bitbox{6}{nextB}
  \bitbox{6}{nextS}
\color{black}
\end{bytefield}}

The {\tt P} field is a predicate; if it does not hold, the instruction
is ignored.  Otherwise the flags are updated according to the {\tt
  nextA}, {\tt nextB}, and {\tt nextS} fields; each specifies the new
value as the logical {\tt OR} of zero or more inputs:

\begin{center}
{\tt
\begin{bytefield}{6}
  \bitheader[b]{0-5}\\
  \bitbox{1}{${\text{\tt A}}$}
  \bitbox{1}{$\overline{\text{\tt A}}$}
  \bitbox{1}{${\text{\tt B}}$}
  \bitbox{1}{$\overline{\text{\tt B}}$}
  \bitbox{1}{${\text{\tt S}}$}
  \bitbox{1}{$\overline{\text{\tt S}}$}
\end{bytefield}}
\end{center}

Each bit corresponds to one possible input; all inputs whose bits are
set are {\tt OR}ed together, and the resulting value is assigned to
the flag.  Note that if none of the bits are set, the value assigned
is zero.  Note also that it is possible to produce a {\tt 1} by {\tt
  OR}ing any flag with its complement.


\pagebreak

\subsection{{\tt setInner}}

This instruction loads the inner loop counter with either a literal
number, the special value $\infty$, or the contents of the {\tt data}
register.

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS} 
  \bitbox{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{1}
  \bitbox{2}{01}
\color{light}
  \bitbox[tbr]{8}{}
  \bitbox[l]{8}{}
\color{black}
\end{bytefield}}\\

\begin{bytefield}{26}
  \bitbox[r]{18}{\raggedleft from data latch:\hspace{0.2cm}\ }
  \bitbox{2}{\tt 00}
\color{light}
  \bitbox[tbr]{6}{} 
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,5,6,7}\\
  \bitbox[r]{18}{\raggedleft from literal:\hspace{0.2cm}\ }
  \bitbox{2}{\tt 10}
  \bitbox{6}{\tt Literal} 
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,5,6,7}\\
  \bitbox[r]{18}{\raggedleft with $\infty$\ \ }
  \bitbox{2}{\tt 11} 
\color{light}
  \bitbox[tbr]{6}{} 
\color{black}
\end{bytefield}


\subsection{{\tt setOuter}}

This instruction loads the outer loop counter {\tt OLC} with either
{\tt max(0,OLC-1)}, a literal or the contents of the {\tt data}
register.

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21,24}\\
\color{light}
  \bitbox{1}{I}
  \bitbox{1}{OS}
\color{light}
  \bitbox[tbr]{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{1}
  \bitbox{2}{10}
\color{light}
  \bitbox[tbr]{9}{} 
  \bitbox[l]{7}{}
\color{black}
\end{bytefield}}\\

\begin{bytefield}{26}
  \bitbox[r]{19}{\raggedleft {\tt max(0,OLC-1)}:\hspace{0.2cm}\ }
  \bitbox{2}{\tt 00} 
%\color{light}
  \bitbox[tbr]{5}{} 
%\color{black}
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitbox[r]{19}{\raggedleft from data latch:\hspace{0.2cm}\ }
  \bitbox{2}{\tt 01} 
\color{light}
  \bitbox[tbr]{5}{} 
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,5,6}\\
  \bitbox[r]{19}{\raggedleft from literal:\hspace{0.2cm}\ }
  \bitbox{1}{\tt 1} 
  \bitbox{6}{\tt Literal} 
\end{bytefield}


%\subsection{{\tt torpedo}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{0,5,16-19,21}\\
%\color{light}
%  \bitbox{4}{} 
%\color{black}
%  \bitbox{3}{000} 
%  \bitbox{1}{1}
%  \bitbox{2}{00}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\end{bytefield}}
%
%
%When a {\tt torpedo} instruction reaches the instruction horn, it will
%wait there until an instruction is on deck whose {\tt A}rmor bit is
%not set.  The {\tt torpedo} will then cause ``Process \#2'' of the on
%deck instruction to terminate and will set the outer loop counter to zero.

\subsection{{\tt tail}}

\color{red}
{\it This will probably become a bit on every instruction rather than
  its own instruction.  The only problem is that we have run out of bits in the {\tt literal} instruction.  Two possible solutions: (a) declare that {\tt literal} cannot be the last instruction in a loop or (b) because {\tt literal} instructions cannot be torpedoed anyways, re-use its {\tt I} bit for this purpose.}
\color{black}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,5,16-19,21}\\
\color{light}
  \bitbox{4}{} 
\color{black}
  \bitbox{3}{000} 
  \bitbox{1}{1}
  \bitbox{2}{01}
\color{light}
  \bitbox[tbr]{16}{} 
\end{bytefield}}

When a {\tt tail} instruction reaches {\tt IH}, it seals the hatch.
The {\tt tail} instruction does not enter the instruction fifo.

\color{black}
%\pagebreak
%\subsection{{\tt takeOuterLoopCounter}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{16-19,21}\\
%\color{light}
%  \bitbox{1}{A}
%  \bitbox{1}{OS} 
%  \bitbox{2}{P}
%\color{black}
%  \bitbox{3}{000}
%  \bitbox{1}{0}
%  \bitbox{2}{11}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\color{black}
%\end{bytefield}}
%
%This instruction copies the value in the outer loop counter {\tt OLC}
%into the least significant bits of the data latch and leaves all other
%bits of the data latch unchanged.
%
%\subsection{{\tt takeInnerLoopCounter}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{16-19,21}\\
%\color{light}
%  \bitbox{1}{A}
%  \bitbox{1}{OS} 
%  \bitbox{2}{P}
%\color{black}
%  \bitbox{3}{???}
%  \bitbox{1}{?}
%  \bitbox{2}{??}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\color{black}
%\end{bytefield}}
%
%This instruction copies the value in the inner loop counter {\tt ILC}
%into the least significant bits of the data latch and leaves all other
%bits of the data latch unchanged.
%
%
%
%%\pagebreak
%%\subsection{{\tt interrupt}}
%%
%%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{0,5,16-19,21}\\
%\color{light}
%  \bitbox{4}{} 
%\color{black}
%  \bitbox{3}{000} 
%  \bitbox{1}{1}
%  \bitbox{2}{00}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\end{bytefield}}
%
%When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
%there for the {\tt OD} stage to be full with an instruction that has
%the {\tt IM} bit set.  When this occurs, the instruction at {\tt OD}
%{\it will not execute}, but {\it may reloop} if the conditions for
%relooping are met.
%\footnote{The ability to interrupt an instruction yet have it reloop is very
%useful for processing chunks of data with a fixed size header and/or
%footer and a variable length body.}
%
%
%\subsection{{\tt massacre}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{16-19,21}\\
%\color{light}
%  \bitbox{4}{} 
%\color{black}
%  \bitbox{3}{000} 
%  \bitbox{1}{1}
%  \bitbox{2}{01}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\color{black}
%\end{bytefield}}
%
%When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
%for the {\tt OD} stage to be full with an instruction that has the
%{\tt IM} bit set.  When this occurs, all instructions in the
%instruction fifo (including {\tt OD}) are retired.
%
%\subsection{{\tt clog}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{16-19,21}\\
%\color{light}
%  \bitbox{4}{} 
%\color{black}
%  \bitbox{3}{000} 
%  \bitbox{1}{1}
%  \bitbox{2}{10}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\color{black}
%\end{bytefield}}
%
%When a {\tt clog} instruction reaches {\tt OD}, it remains there and
%no more instructions will be executed until an {\tt unclog} is
%performed.
%
%\subsection{{\tt unclog}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
%  \bitheader[b]{16-19,21}\\
%\color{light}
%  \bitbox{4}{} 
%\color{black}
%  \bitbox{3}{000} 
%  \bitbox{1}{1}
%  \bitbox[lrtb]{2}{11}
%\color{light}
%  \bitbox[tbr]{16}{} 
%\color{black}
%\end{bytefield}}
%
%When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
%until a {\tt clog} instruction is at {\tt OD}.  When this occurs, both
%instructions retire.
%
%Note that issuing an {\tt unclog} instruction to a dock which is not
%clogged and whose instruction fifo contains no {\tt clog} instructions
%will cause the dock to deadlock.



\pagebreak
\epsfig{file=overview,height=5in,angle=90}

\pagebreak
\subsection*{Input Dock}
\epsfig{file=indock,width=7in,angle=90}

\pagebreak
\subsection*{Output Dock}
\epsfig{file=outdock,width=6.5in,angle=90}


%\pagebreak
%\epsfig{file=ports,height=5in,angle=90}

%\pagebreak
%\epsfig{file=best,height=5in,angle=90}


\end{document}