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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
69 \color{red}17-Feb\color{black}
70 & \color{red} Clarified setting of the {\tt C}-flag\color{black}\\
72 & Fixed a one-word typo \\
74 & Added {\tt head} instruction \\
75 & Lengthened external encoding of {\tt tail} instruction by one bit \\
76 & Added {\tt abort} instruction \\
77 & Removed {\tt OS} field from instructions \\
78 & Renamed the {\tt Z}-flag (olc {\bf Z}ero) to the {\tt D}-flag (loop {\bf D}one)\\
80 & Updated diagram in section 3 to put dispatch path near MSB\\
81 & Changed DP[37:25] to DP[37:27]\\
82 & Added note on page 4 regarding previous\\
84 & Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\
85 & Clarify what ``{\tt X-Extended}'' means \\
86 & Change C-bit source selector from {\tt Di} to {\tt Dc} \\
88 & Distinguish {\tt Z}-flag from OLC=0\\
89 & Add {\tt flush} instruction\\
90 & Change {\t I} bit from ``Interruptable'' to ``Immune''\\
92 & Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
94 & Note that decision to requeue is based on value of OLC {\it before} execution\\
95 & Note that decision to open the hatch is based on value of {\tt OS} bit\\
97 %& Added {\tt OLC=0} predicate \\
98 %& Eliminated {\tt TAPL} (made possible by previous change) \\
99 %& Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
101 %& Fixed a few typos \\
102 %& Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
103 %& Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
105 %& When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
106 %& Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
108 %& Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
109 %& Reworked encoding of {\tt set} instruction \\
112 %& Factored in Russell Kao's comments (thanks!)\\
113 %& Added mechanism for setting C-flag from fabric even on outboxes\\
115 %& Made {\tt OLC} test a predicate-controlled condition\\
116 %& Rewrote ``on deck'' section \\
117 %& Added ``{\tt unset}'' value for {\tt ILC}\\
118 %& Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
121 %& added comment about address-to-path ship \\
122 %& changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
123 %& changed the order of instructions in the encoding map \\
125 %& added epilogue fifo to diagrams \\
126 %& indicated that a token sent to the instruction port is treated as a torpedo \\
128 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
129 %& replaced {\tt literal} with {\tt shift} instruction \\
131 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
132 %& Removed ability to manually set the {\tt C} flag \\
133 %& Expanded predicate field to three bits \\
134 %& New literals scheme (via shifting) \\
135 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
136 %& Added summary of instruction encodings on last page \\
138 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
140 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
141 %& update table 3.1.2 \\
142 %& rename {\tt S} flag to {\tt C} \\
143 %& noted that {\tt setFlags} can be used as {\tt nop} \\
145 %& removed the {\tt L} flag (epilogues can now do this) \\
146 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
147 %& renamed {\tt data} instruction to {\tt literal} \\
148 %& renamed {\tt send} instruction to {\tt move} \\
150 %& added ``if its predicate is true'' to repeat count \\
151 %& added note that red wires do not contact ships \\
152 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
153 %& removed black dot from diagrams \\
154 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
155 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
156 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
157 %& added section ``Torpedo Details'' \\
158 %& removed {\tt torpedo} instruction \\
161 %& renamed loop+repeat to outer+inner (not in red) \\
162 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
163 %& rewrote ``inner and outer loops'' section \\
164 %& updated all diagrams \\
167 %& Moved address bits to the LSB-side of a 37-bit instruction \\
168 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
169 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
170 %& Created the {\tt Hold} field \\
171 %& Changed how ReLooping works \\
172 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
179 \epsfig{file=all,height=1.5in}
180 \epsfig{file=overview-new,height=1.5in}
185 \section{Overview of Fleet}
187 A Fleet processor is organized around a {\it switch fabric}, which is
188 a packet-switched network with reliable in-order delivery. The switch
189 fabric is used to carry data between different functional units,
190 called {\it ships}. Each ship is connected to the switch fabric by
191 one or more programmable elements known as {\it docks}.
193 A {\it path} specifies a route through the switch fabric from a
194 particular {\it source} to a particular {\it destination}. The
195 combination of a path and a single word to be delivered is called a
196 {\it packet}. The switch fabric carries packets from their sources to
197 their destinations. Each dock has two destinations: one for {\it
198 instructions} and one for {\it data}. A Fleet is programmed by
199 depositing instruction packets into the switch fabric with paths that
200 will lead them to instruction destinations of the docks at which they
203 When a packet arrives at the instruction destination of a dock, it is
204 enqueued for execution. Before the instruction executes, it may cause
205 the dock to wait for a packet to arrive at the dock's data destination
206 or for a value to be presented by the ship. When an instruction
207 executes it may consume this data and may present a data value to the
208 ship or transmit a packet.
210 When an instruction sends a packet into the switch fabric, it may
211 specify that the payload of the packet is irrelevant. Such packets
212 are known as {\it tokens}, and consume less energy than data packets.
216 \epsfig{file=overview-new,width=2.5in}\\
217 {\it Overview of a Fleet processor; dark gray shading represents the
218 switch fabric, ships are shown in light gray, and docks are shown in blue.}
224 \section{The FleetTwo Dock}
226 The diagram below represents a conceptual view of the interface
227 between ships and the switch fabric; actual implementation circuitry
231 \epsfig{file=all,width=3.5in}\\
232 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
233 blue lines carry either tokens or data words, red lines carry either
234 instructions or torpedoes, and dashed lines carry only tokens.}
237 Each dock consists of a {\it data latch}, which is as wide as a single
238 machine word and a circular {\it instruction fifo} of
239 instruction-width latches. The values in the instruction fifo control
240 the data latch. The dock also includes a {\it path latch}, which
241 stores the path along which outgoing packets will be
244 Note that the instruction fifo in each dock has a destination of its
245 own; this is the {\it instruction destination} mentioned in the
246 previous section. A token sent to an instruction destination is
247 called a {\it torpedo}; it does not enter the instruction fifo, but
248 rather is held in a waiting area where it may interrupt certain
249 instructions (see the section on the {\tt move} instruction for further
252 From any source to any dock's data destination there are
253 two distinct paths which differ by a single bit. This bit is known as
254 the ``signal'' bit, and the routing of a packet is not affected by it;
255 the signal bit is used to pass control values between docks. Note that paths
256 terminating at an {\it instruction} destination need not have a signal
260 \section{Instructions}
262 In order to cause an instruction to execute, the programmer must first
263 arrange for that instruction word to arrive in the data latch of some
264 output dock. For example, this might be the ``data read'' output dock
265 of the memory access ship or the output of a fifo ship. Once an
266 instruction has arrived at this output dock, it is {\it dispatched} by
267 sending it to the {\it instruction destination} of the dock at which
270 Each instruction is 26 bits long, which makes it possible for an
271 instruction and an 11-bit path to fit in a single word of memory.
272 This path is the path from the {\it dispatching} dock to the {\it
277 \setlength{\bitwidth}{3.5mm}
279 \begin{bytefield}{37}
280 \bitheader[b]{0,25,26,36}\\
281 \bitbox{11}{dispatch path}
282 \bitbox{26}{instruction}
286 Note that the 11 bit {\tt dispatch path} field is not the same width
287 as the 13 bit {\tt Immediate} path field in the {\tt move} instruction,
288 which in turn may not be the same width as the actual path latches in
291 The algorithm for expanding a path to a wider width is specific to the
292 switch fabric implementation, and is not specified by this
293 document.\footnote{for the Marina experiment, the correct
294 algorithm is to sign-extend the path; the most significant bit of
295 the given path is used to fill all vacant bits of the latch} In
296 particular, because the {\tt dispatch path} field is always used to
297 specify a path which terminates at an instruction destination (never a
298 data destination), and because instruction destinations ignore the
299 signal bit, certain optimizations may be possible. \color{black}
302 %\subsection{Life Cycle of an Instruction}
304 %The diagram below shows an input dock for purposes of illustration:
307 %\epsfig{file=in,width=4in}\\
314 %\epsfig{file=out,width=4in}\\
315 %{\it an output dock}
318 %\subsection{Format of an Instruction}
320 %All instruction words have the following format:
322 \newcommand{\bitsHeader}{
327 \newcommand{\bitsHeaderNoI}{
333 %The {\tt P} bits are a {\it predicate}; this holds a code which
334 %indicates if the instruction should be executed or ignored depending
335 %on the state of flags in the dock. Note that {\tt head} and {\tt
336 %tail} instructions do not have {\tt P} fields.
339 \subsection{Loop Counters}
341 A programmer can perform two types of loops: {\it inner} loops
342 consisting of only one {\tt move} instruction and {\it outer} loops of
343 multiple instructions of any type. Inner loops may be nested within
344 an outer loop, but no other nesting of loops is allowed.
346 The dock has two loop counters, one for each kind of loop:
349 \item {\tt OLC} is the Outer Loop Counter
350 \item {\tt ILC} is the Inner Loop Counter
353 The {\tt OLC} applies to all instructions and can hold integers {\tt
356 The {\tt ILC} applies only to {\tt move} instructions and can hold
357 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
358 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
359 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
360 executes until interrupted by a torpedo. After every {\tt move}
361 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
362 to {\tt 1}, {\it not to 0}).
367 The dock has four flags: {\tt A}, {\tt B},
368 {\tt C}, and {\tt D}.
371 \item The {\tt A} and {\tt B} flags are general-purpose flags which
372 may be set and cleared by the programmer.
376 % The {\tt L} flag, known as the {\it last} flag, is set whenever
377 % the value in the outer counter ({\tt OLC}) is one,
380 % that the dock is in the midst of the last iteration of an
381 % outer loop. This flag can be used to perform certain
382 % operations (such as sending a completion token) only on the last
383 % iteration of an outer loop.
385 \item The {\tt C} flag is known as the {\it control} flag, and may be
386 set by the {\tt move} instruction based on information from the
387 ship or from an inbound packet. See the {\tt move} instruction
390 \item The {\tt D} flag is known as the {\it done} flag. The {\tt D}
391 flag is {\it set} when the {\tt OLC} is zero immediately after
392 execution of a {\tt set olc} or {\tt decrement olc} instruction,
393 or when a torpedo strikes. The {\tt D} flag is {\it cleared}
394 when a {\tt set olc} instruction causes the {\tt OLC} to be
395 loaded with a nonzero value.
401 \subsection{Predication}
403 All instructions except for {\tt head} and {\tt tail} have a three-bit
404 field marked {\tt P}, which specifies a {\it predicate}.
407 \setlength{\bitwidth}{5mm}
409 \begin{bytefield}{26}
410 \bitheader[b]{0,20,21,23-25}\\
417 The predicate determines which conditions must be true in order for
418 the instruction to execute; if it is not executed, it is simply {\it
419 ignored}. The table below shows what conditions must be true in
420 order for an instruction to execute:
423 \begin{tabular}{|r|l|}\hline
424 Code & Execute if \\\hline
425 {\tt 000:} & {\tt D=0}\ and {\tt A=0} \\
426 {\tt 001:} & {\tt D=0}\ and {\tt A=1} \\
427 {\tt 010:} & {\tt D=0}\ and {\tt B=0} \\
428 {\tt 011:} & {\tt D=0}\ and {\tt B=1} \\
429 {\tt 100:} & Unused \\
430 {\tt 101:} & {\tt D=1}\ \\
431 {\tt 110:} & {\tt D=0}\ \\
432 {\tt 111:} & always \\
438 \begin{wrapfigure}{r}{40mm}
440 \epsfig{file=requeue,height=1.5in}\\
442 \caption{{\it the requeue stage}}
445 \subsection{The Requeue Stage}
447 The requeue stage has two inputs, which will be referred to as the
448 {\it enqueueing} input and the {\it recirculating} input. It has a
449 single output which feeds into the instruction fifo.
451 The requeue stage has two states: {\sc Updating} and {\sc
454 \subsubsection{The {\sc Updating} State}
456 On initialization, the dock is in the {\sc Updating} state. In this
457 state the requeue stage is performing three tasks:
459 \item it is draining the
460 previous loop's instructions (if any) from the fifo
461 \item it is executing any ``one
462 shot'' instructions which come between the previous loop's {\tt tail}
463 and the next loop's {\tt head}
464 \item it is loading the instructions of
465 the next loop into the fifo.
468 In the {\sc Updating} state, the requeue stage will accept any
469 instruction other than a {\tt tail} which arrives at its {\it
470 enqueueing} input, and pass this instruction to its output. Any
471 instruction other than a {\tt head} which arrives at the {\it
472 recirculating} input will be discarded.
474 Note that when a {\tt tail} instruction arrives at the {\it
475 enqueueing} input, it ``gets stuck'' there. Likewise, when a {\tt
476 head} instruction arrives at the {\it recirculating} input, it also
477 ``gets stuck''. When the requeue stage finds {\it both} a {\tt tail}
478 instruction stuck at the {\it enqueueing} input and a {\tt head}
479 instruction stuck at the {\it recirculating} input, the requeue stage
480 discards both the {\tt head} and {\tt tail} and transitions to the
481 {\sc Circulating} state.
483 \subsubsection{The {\sc Circulating} State}
485 In the {\sc Circulating} state, the dock repeatedly executes the set
486 of instructions that are in the instruction fifo.
488 In the {\sc Circulating} state, the requeue stage will not accept
489 items from its {\it enqueueing} input. Any item presented at the {\it
490 recirculating} input will be passed through to the requeue stage's
493 When an {\tt abort} instruction is executed, the requeue stage
494 transitions back to the {\sc Updating} state. Note that {\tt abort}
495 instructions include a predicate; an {\tt abort} instruction whose
496 predicate is not met will not cause this transition.
502 \section{Instructions}
504 %The dock supports four instructions:
505 %{\tt move} (variants: {\tt moveto}, {\tt dispatch}),
512 \subsection{{\tt move}}
514 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
516 \begin{bytefield}{26}
517 \bitheader[b]{14-20}\\
531 \begin{bytefield}{26}
532 \bitheader[b]{0,12,13}\\
533 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
536 \bitbox{13}{\tt Immediate}
539 \begin{bytefield}{26}
540 \bitheader[b]{11,12,13}\\
541 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:27\color{black}]\to Path}})\ \ }
550 \begin{bytefield}{26}
551 \bitheader[b]{11,12,13}\\
552 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
563 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
564 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
565 \item {\tt Dc} - Data Capture: pulse the data latch.
566 \item {\tt Do} - Data Output: fill the data successor.
567 \item {\tt To} - Token Output: fill the token successor.
570 The data successor and token successor must both be empty in order for
571 a {\tt move} instruction to attempt execution.
573 The {\tt I} bit stands for {\tt Immune}, and indicates if the
574 instruction is immune to torpedoes.
576 Every time the {\tt move} instruction executes, the {\tt C} flag may
581 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
582 of the incoming packet if {\tt Dc} bit is set. If the {\tt Dc}
583 bit is not set the {\tt C} flag takes an unknown value.
585 \item At an {\it output} dock the {\tt C} flag is set to a value
586 provided by the ship if the {\tt Dc} bit is set. If the {\tt
587 Dc} bit is not set, the {\tt C} flag is set to the signal bit of
592 The {\tt flush} instruction is a variant of {\tt move} which is valid
593 only at input docks. It has the same effect as {\tt deliver}, except
594 that it sets a special ``flushing'' indicator along with the data
597 \newcommand{\bitsFlush}{\setlength{\bitwidth}{5mm}
599 \begin{bytefield}{26}
600 \bitheader[b]{14-18}\\
601 \bitbox[r]{7}{\raggedleft{\tt flush\ \ }}
613 When a ship fires, it must examine the ``flushing'' indicators on the
614 input docks whose fullness was part of the firing condition. If all
615 of the input docks' flushing indicators are set, the ship must drain
616 all of their data successors and take no action. If some, but not
617 all, of the indicators are set, the ship must drain {\it only the data
618 successors of the docks whose indicators were {\bf not} set}, and
619 take no action. If none of the flushing indicators was set, the ship
626 \subsection{{\tt set}}
628 The {\tt set} command is used to set or decrement the inner loop
629 counter, outer loop counter, and data latch.
631 \newcommand{\bitsSet}{
633 \begin{bytefield}{26}
634 \bitheader[b]{19-25}\\
645 \begin{bytefield}{26}
646 \bitheader[b]{0,5,12-18}\\
647 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
649 \bitbox{4}{\tt 1000\color{black}}
652 \bitbox{6}{\tt Immediate}
655 \begin{bytefield}{26}
656 \bitheader[b]{12-18}\\
657 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
659 \bitbox{4}{\tt 1000\color{black}}
664 \begin{bytefield}{26}
665 \bitheader[b]{12-18}\\
666 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
668 \bitbox{4}{\tt 1000\color{black}}
673 \begin{bytefield}{26}
674 \bitheader[b]{0,5,6,12-18}\\
675 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
677 \bitbox{4}{\tt 0100\color{black}}
681 \bitbox{6}{\tt Immediate}
684 \begin{bytefield}{26}
685 \bitheader[b]{6,12-18}\\
686 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
688 \bitbox{4}{\tt 0100\color{black}}
695 \begin{bytefield}{26}
696 \bitheader[b]{12-18}\\
697 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
699 \bitbox{4}{\tt 0100\color{black}}
704 \begin{bytefield}{26}
705 \bitheader[b]{0,13-18}\\
706 \bitbox[1]{6}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}\to{\tt Data Latch}}
708 \bitbox{4}{\tt 0010\color{black}}
709 \bitbox{1}{\begin{minipage}{0.5cm}{
716 \bitbox{14}{\tt Immediate}
719 \begin{bytefield}{26}
720 \bitheader[b]{0,5,6,11,15-18}\\
721 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
723 \bitbox{4}{\tt 0001\color{black}}
725 \bitbox{6}{\tt nextA}
726 \bitbox{6}{\tt nextB}
732 The FleetTwo implementation is likely to have an unarchitected
733 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
734 with the possibly-extended literal {\it at the time that the {\tt set}
735 instruction comes on deck}. This latch is then copied into the data
736 latch when a {\tt set Data Latch} instruction
739 The {\tt Sign-Extended Immediate} instruction copies the {\tt
740 Immediate} field into the least significant bits of the data latch.
741 All other bits of the data latch are filled with a copy of the
742 bit marked ``{\tt Sign}.''
745 Each of the {\tt nextA} and {\tt nextB} fields has the following
746 structure, and indicates which old flag values should be logically
747 {\tt OR}ed together to produce the new flag value:
753 \bitbox{1}{${\text{\tt A}}$}
754 \bitbox{1}{$\overline{\text{\tt A}}$}
755 \bitbox{1}{${\text{\tt B}}$}
756 \bitbox{1}{$\overline{\text{\tt B}}$}
757 \bitbox{1}{${\text{{\tt C}\ }}$}
758 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
762 Each bit corresponds to one possible input; all inputs whose bits are
763 set are {\tt OR}ed together, and the resulting value is assigned to
764 the flag. Note that if none of the bits are set, the value assigned
765 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
766 OR}ing any flag with its complement, and that {\tt set Flags} can
767 be used to create a {\tt nop} (no-op) by setting each flag to itself.
773 \subsection{{\tt shift}}
775 \newcommand{\shiftImmediateSize}{19}
777 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
778 bits. When a {\tt shift} instruction is executed, this immediate is copied
779 into the least significant \shiftImmediateSize\ bits of the data latch,
780 and the remaining most significant bits of the data latch are loaded
781 with the value formerly in the least significant bits of the data latch.
782 In this manner, large literals can be built up by ``shifting'' them
783 into the data latch \shiftImmediateSize\ bits at a time.
785 \newcommand{\bitsShift}{
786 \setlength{\bitwidth}{5mm}
788 \begin{bytefield}{26}
789 \bitheader[b]{0,18-20}\\
796 \bitbox{\shiftImmediateSize}{Immediate}
801 The FleetTwo implementation is likely to have an unarchitected
802 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
803 with the literal {\it at the time that the {\tt shift} instruction
804 comes on deck}. This latch is then copied into the data latch when
805 the instruction executes.
809 \subsection{{\tt abort}}
810 \newcommand{\bitsAbort}{\setlength{\bitwidth}{5mm}
812 \begin{bytefield}{26}
813 \bitheader[b]{17-20}\\
826 An {\tt abort} instruction causes a loop to exit; see the section on
827 the Requeue Stage for further details.
829 \subsection{{\tt head}}
830 \newcommand{\bitsHead}{
831 \setlength{\bitwidth}{5mm}
833 \begin{bytefield}{26}
834 \bitheader[b]{17-20}\\
847 A {\tt head} instruction marks the start of a loop; see the section on
848 the Requeue Stage for further details.
851 \subsection{{\tt tail}}
852 \newcommand{\bitsTail}{
853 \setlength{\bitwidth}{5mm}
855 \begin{bytefield}{26}
856 \bitheader[b]{17-20}\\
869 A {\tt tail} instruction marks the end of a loop; see the section on
870 the Requeue Stage for further details.
874 %\subsection{{\tt takeOuterLoopCounter}}
876 %\setlength{\bitwidth}{5mm}
878 %\begin{bytefield}{26}
879 % \bitheader[b]{16-19,21}\\
893 %This instruction copies the value in the outer loop counter {\tt OLC}
894 %into the least significant bits of the data latch and leaves all other
895 %bits of the data latch unchanged.
897 %\subsection{{\tt takeInnerLoopCounter}}
899 %\setlength{\bitwidth}{5mm}
901 %\begin{bytefield}{26}
902 % \bitheader[b]{16-19,21}\\
916 %This instruction copies the value in the inner loop counter {\tt ILC}
917 %into the least significant bits of the data latch and leaves all other
918 %bits of the data latch unchanged.
923 %%\subsection{{\tt interrupt}}
925 %%\setlength{\bitwidth}{5mm}
927 %\begin{bytefield}{26}
928 % \bitheader[b]{0,5,16-19,21}\\
939 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
940 %there for the {\tt OD} stage to be full with an instruction that has
941 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
942 %{\it will not execute}, but {\it may reloop} if the conditions for
944 %\footnote{The ability to interrupt an instruction yet have it reloop is very
945 %useful for processing chunks of data with a fixed size header and/or
946 %footer and a variable length body.}
949 %\subsection{{\tt massacre}}
951 %\setlength{\bitwidth}{5mm}
953 %\begin{bytefield}{26}
954 % \bitheader[b]{16-19,21}\\
966 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
967 %for the {\tt OD} stage to be full with an instruction that has the
968 %{\tt IM} bit set. When this occurs, all instructions in the
969 %instruction fifo (including {\tt OD}) are retired.
971 %\subsection{{\tt clog}}
973 %\setlength{\bitwidth}{5mm}
975 %\begin{bytefield}{26}
976 % \bitheader[b]{16-19,21}\\
988 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
989 %no more instructions will be executed until an {\tt unclog} is
992 %\subsection{{\tt unclog}}
994 %\setlength{\bitwidth}{5mm}
996 %\begin{bytefield}{26}
997 % \bitheader[b]{16-19,21}\\
1003 % \bitbox[lrtb]{2}{11}
1005 % \bitbox[tbr]{16}{}
1009 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
1010 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
1011 %instructions retire.
1013 %Note that issuing an {\tt unclog} instruction to a dock which is not
1014 %clogged and whose instruction fifo contains no {\tt clog} instructions
1015 %will cause the dock to deadlock.
1020 \section*{Instruction Encoding Map\color{black}}
1023 \vspace{3mm}\hspace{-1cm}{\tt shift}\hspace{1cm}\vspace{-6mm}\\
1026 \vspace{3mm}\hspace{-1cm}{\tt set}\hspace{1cm}\vspace{-6mm}\\
1029 \vspace{3mm}\hspace{-1cm}{\tt move}\hspace{1cm}\vspace{-6mm}\\
1033 \vspace{3mm}\hspace{-1cm}{\tt abort}\hspace{1cm}\vspace{-6mm}\\
1036 \vspace{3mm}\hspace{-1cm}{\tt head}\hspace{1cm}\vspace{-6mm}\\
1039 \vspace{3mm}\hspace{-1cm}{\tt tail}\hspace{1cm}\vspace{-6mm}\\
1044 %\epsfig{file=all,height=5in,angle=90}
1047 %\subsection*{Input Dock}
1048 %\epsfig{file=in,width=8in,angle=90}
1051 %\subsection*{Output Dock}
1052 %\epsfig{file=out,width=8in,angle=90}
1056 %\epsfig{file=ports,height=5in,angle=90}
1059 %\epsfig{file=best,height=5in,angle=90}