chips/marina/electric/redFive.delib/nand3en.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell nand3en;1{sch}
   8 Cnand3en;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-29;Y-7;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-29;Y-6;)S1|ATTR_drive0(D5G1;HNPTX-29;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-29;Y-9;)Sstrong1|ATTR_verilog_template(D5G1;NTX20.5;Y-17.5;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
   9 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX2;Y2;)Smax(@X/10., 5./6.)
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@1||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  11 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@2||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  12 Ngeneric:Facet-Center|art@0||0|0||||AV
  13 NOff-Page|conn@0||-22|4||||
  14 NOff-Page|conn@1||0|14.5|||R|
  15 NOff-Page|conn@2||14|-1|||RR|
  16 NOff-Page|conn@3||-15|-12||||
  17 Inand3en;1{ic}|nand3en@0||29|14|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  18 Inms3;1{ic}|nms3@0||0|-12|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-2;Y0.5;)S@X
  19 NWire_Pin|pin@0||9|-8||||
  20 NWire_Pin|pin@1||-18|-4||||
  21 NWire_Pin|pin@2||-18|4||||
  22 NWire_Pin|pin@3||-14|0||||
  23 Ngeneric:Invisible-Pin|pin@4||-0.5|27|||||ART_message(D5G6;)S[nand3en]
  24 NWire_Pin|pin@5||9|-1||||
  25 NWire_Pin|pin@6||9|4||||
  26 NWire_Pin|pin@7||4.5|0||||
  27 NWire_Pin|pin@8||-9|-12||||
  28 Ngeneric:Invisible-Pin|pin@9||-0.5|22|||||ART_message(D5G2;)S["three input, fixed-size NAND where ina is DC signal (enable)"]
  29 NWire_Pin|pin@10||-5|0||||
  30 NWire_Pin|pin@11||0|0||||
  31 NWire_Pin|pin@12||-9|4||||
  32 Ngeneric:Invisible-Pin|pin@13||-0.5|19.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 3]
  33 Ngeneric:Invisible-Pin|pin@14||30|-10|||||ART_message(D5G2;)S[X is drive strength,Each pull-up has the same strength,as the pull-down]
  34 NWire_Pin|pin@15||4.5|7.5||||
  35 NWire_Pin|pin@16||-14|7.5||||
  36 NWire_Pin|pin@17||-5|7.5||||
  37 NPower|pwr@0||-5|11.5||||
  38 Awire|net@0|||900|pin@17||-5|7.5|PMOS@0|s|-5|6
  39 Awire|net@1|||1800|pin@12||-9|4|PMOS@0|g|-8|4
  40 Awire|net@2|||2700|pin@10||-5|0|PMOS@0|d|-5|2
  41 Awire|net@3|||1800|pin@8||-9|-12|nms3@0|g|-3|-12
  42 Awire|net@4|||900|pin@5||9|-1|pin@0||9|-8
  43 Awire|net@5|||0|pin@0||9|-8|nms3@0|g2|3|-8
  44 Awire|net@6|||0|nms3@0|g3|-3|-4|pin@1||-18|-4
  45 Awire|net@7|||2700|pin@1||-18|-4|pin@2||-18|4
  46 Awire|net@8|||0|pin@2||-18|4|conn@0|y|-20|4
  47 Awire|net@9|||0|pin@10||-5|0|pin@3||-14|0
  48 Awire|net@10|||900|pin@11||0|0|nms3@0|d|0|-2
  49 Awire|net@11|||1800|pin@5||9|-1|conn@2|y|12|-1
  50 Awire|net@12|||2700|pin@5||9|-1|pin@6||9|4
  51 Awire|net@13|||0|pin@8||-9|-12|conn@3|y|-13|-12
  52 Awire|net@14|||0|pin@11||0|0|pin@10||-5|0
  53 Awire|net@15|||0|pin@7||4.5|0|pin@11||0|0
  54 Awire|net@16|||2700|pin@11||0|0|conn@1|a|0|12.5
  55 Awire|net@17|||2700|pin@8||-9|-12|pin@12||-9|4
  56 Awire|net@18|||2700|pin@7||4.5|0|PMOS@1|d|4.5|2
  57 Awire|net@19|||1800|PMOS@1|g|7.5|4|pin@6||9|4
  58 Awire|net@20|||2700|pin@3||-14|0|PMOS@2|d|-14|2
  59 Awire|net@21|||0|PMOS@2|g|-17|4|pin@2||-18|4
  60 Awire|net@22|||900|pin@15||4.5|7.5|PMOS@1|s|4.5|6
  61 Awire|net@23|||2700|PMOS@2|s|-14|6|pin@16||-14|7.5
  62 Awire|net@24|||1800|pin@17||-5|7.5|pin@15||4.5|7.5
  63 Awire|net@25|||1800|pin@16||-14|7.5|pin@17||-5|7.5
  64 Awire|net@26|||2700|pin@17||-5|7.5|pwr@0||-5|11.5
  65 Eina||D5G2;|conn@3|a|I
  66 Einb||D5G2;|conn@2|a|I
  67 Einc||D5G2;|conn@0|y|I
  68 Eout||D5G2;|conn@1|y|O
  69 X