chips/marina/electric/redFive.delib/nms2_sy.sch

   1 HredFive|8.10k
   2
   3 # Cell nms2_sy;1{sch}
   4 Cnms2_sy;1{sch}||schematic|1021415734000|1157998666994||ATTR_Delay(D5G1;HNPX-17;Y-12.5;)I100|ATTR_X(D5G1;HNOLPX-17;Y-11.5;)S1|prototype_center()I[0,0]
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 NOff-Page|conn@0||16.5|0||||
   7 NOff-Page|conn@1||16|-5.5|||YRR|
   8 NOff-Page|conn@2||-15|-5.5||||
   9 Inms2b;1{ic}|nms2@0||8|-9.5|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-0.5;)S@Delay|ATTR_X(D5G1.5;NOLPX-2.25;Y1.5;)S@X/2.
  10 Inms2b;1{ic}|nms2@1||-6.5|-9.5|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-0.5;)S@Delay|ATTR_X(D5G1.5;NOLPX-2.25;Y1.5;)S@X/2.
  11 Inms2_sy;1{ic}|nms2_sy@0||25|11|||D0G4;|ATTR_Delay(D5G1;NPX5.5;Y-0.5;)I100|ATTR_X(D5G1.5;NOLPX-3.75;Y2.5;)S1
  12 Ngeneric:Invisible-Pin|pin@0||-4|14|||||ART_message(D5G6;)S[nms2_sy]
  13 Ngeneric:Invisible-Pin|pin@1||-4|9|||||ART_message(D5G2;)S[symmetric fixed-size N-type two-stack]
  14 NWire_Pin|pin@2||-6.5|0||||
  15 NWire_Pin|pin@3||-1|-9.5||||
  16 NWire_Pin|pin@4||3|-5.5||||
  17 NWire_Pin|pin@5||3|-9.5||||
  18 NWire_Pin|pin@6||-1|-5.5||||
  19 NWire_Pin|pin@7||8|0||||
  20 Awire|net@0|||2250|pin@3||-1|-9.5|pin@4||3|-5.5
  21 Awire|net@1|||3150|pin@5||3|-9.5|pin@6||-1|-5.5
  22 Awire|net@2|||0|pin@6||-1|-5.5|nms2@1|g2|-3.5|-5.5
  23 Awire|net@3|||0|nms2@0|g|5|-9.5|pin@5||3|-9.5
  24 Awire|net@4|||0|nms2@0|g2|11|-5.5|pin@4||3|-5.5
  25 Awire|net@5|||0|conn@1|y|14|-5.5|nms2@0|g2|11|-5.5
  26 Awire|net@6|||1800|nms2@1|g|-9.5|-9.5|pin@3||-1|-9.5
  27 Awire|net@7|||2700|nms2@1|d|-6.5|-3.5|pin@2||-6.5|0
  28 Awire|net@8|||1800|pin@7||8|0|conn@0|a|14.5|0
  29 Awire|net@9|||1800|pin@2||-6.5|0|pin@7||8|0
  30 Awire|net@10|||900|pin@7||8|0|nms2@0|d|8|-3.5
  31 Awire|net@11|||1800|conn@2|y|-13|-5.5|nms2@1|g2|-3.5|-5.5
  32 Ed||D5G2;|conn@0|y|O
  33 Eg||D5G2;|conn@2|a|I
  34 Eg2||D5G2;|conn@1|a|I
  35 X