chips/marina/electric/wiresL.delib/select40.lay

   1 HwiresL|8.10k
   2
   3 # Cell select40;1{lay}
   4 Cselect40;1{lay}||cmos90|1180136751346|1241981698008|I|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 NP-Well-Node|plnode@0||0|0|40|48||A
   7 NN-Well-Node|plnode@1||0|-50|40|52||A
   8 NN-Well-Node|plnode@2||0|50|40|52||A
   9 NP-Select-Node|plnode@3||0|-50|37|52||A
  10 NP-Select-Node|plnode@4||0|50|37|52||A
  11 NN-Select-Node|plnode@5||0|0|37|48||A
  12 X