chips/omegaCounter/40nm/electric/redFive.delib/inv2iHT.sch

   1 HredFive|8.10k
   2
   3 # Cell inv2iHT;1{sch}
   4 Cinv2iHT;1{sch}||schematic|1021415734000|1248729106644||ATTR_Delay(D5G1;HNPX-14.5;Y-11.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-14.5;Y-10.5;)S1|ATTR_drive0(D5G1;HNPTX-14.5;Y-12.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-14.5;Y-13.5;)Sstrong1|prototype_center()I[0,0]
   5 INMOS;1{ic}|NMOS@1||0|-6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
   6 IPMOS;1{ic}|PMOS@1||0|6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X*2.0
   7 Ngeneric:Facet-Center|art@0||0|0||||AV
   8 NOff-Page|conn@0||-13|-6||||
   9 NOff-Page|conn@1||-13.5|6||||
  10 NOff-Page|conn@2||8|0||||
  11 NGround|gnd@0||0|-12.5||||
  12 Iinv2iHT;1{ic}|inv2iHT@0||16|10.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  13 Ngeneric:Invisible-Pin|pin@4||-1|24|||||ART_message(D5G6;)S[inv2iHT]
  14 Ngeneric:Invisible-Pin|pin@5||0|19|||||ART_message(D5G2;)S[two-input HI-threshold inverter]
  15 NWire_Pin|pin@6||0|0||||
  16 Ngeneric:Invisible-Pin|pin@7||1|17|||||ART_message(D5G2;)S[P to N width ratio is 4 to 1]
  17 Ngeneric:Invisible-Pin|pin@8||25|-9|||||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
  18 NPower|pwr@0||0|12.5||||
  19 Awire|net@8|||900|NMOS@1|s|0|-8|gnd@0||0|-10.5
  20 Awire|net@9|||900|pin@6||0|0|NMOS@1|d|0|-4
  21 Awire|net@10|||2700|PMOS@1|s|0|8|pwr@0||0|12.5
  22 Awire|net@11|||2700|pin@6||0|0|PMOS@1|d|0|4
  23 Awire|net@12|||0|conn@2|a|6|0|pin@6||0|0
  24 Awire|net@17|||0|PMOS@1|g|-3|6|conn@1|y|-11.5|6
  25 Awire|net@18|||1800|conn@0|y|-11|-6|NMOS@1|g|-3|-6
  26 Ein[n]||D5G2;|conn@0|a|I
  27 Ein[p]||D5G2;|conn@1|a|I
  28 Eout||D5G2;|conn@2|y|O
  29 X