1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Size(..), intSize, floatSize, isFloatSize,
29 wordSize, cmmTypeSize, sizeToWidth,
32 Imm(..), strImmLit, litToImm,
40 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
41 RegClass(..), regClass,
47 get_GlobalReg_reg_or_addr,
49 -- * Machine-dependent register-related stuff
50 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
51 allocatableRegsInClass,
58 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
61 EABase(..), EAIndex(..),
62 eax, ebx, ecx, edx, esi, edi, ebp, esp,
63 fake0, fake1, fake2, fake3, fake4, fake5,
66 #if x86_64_TARGET_ARCH
67 EABase(..), EAIndex(..), ripRel,
68 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
69 eax, ebx, ecx, edx, esi, edi, ebp, esp,
70 r8, r9, r10, r11, r12, r13, r14, r15,
71 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
72 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
74 addrModeRegs, allFPArgRegs,
78 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
79 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
81 #if powerpc_TARGET_ARCH
90 #include "HsVersions.h"
93 # define STOLEN_X86_REGS 4
94 -- HACK: go for the max
97 #include "../includes/MachRegs.h"
101 import CgUtils ( get_GlobalReg_addr )
102 import CLabel ( CLabel, mkMainCapabilityLabel )
104 import Outputable ( Outputable(..), pprPanic, panic )
105 import qualified Outputable
113 #if powerpc_TARGET_ARCH
114 import Data.Word ( Word8, Word16, Word32 )
115 import Data.Int ( Int8, Int16, Int32 )
118 -- -----------------------------------------------------------------------------
119 -- Sizes on this architecture
121 -- A Size is usually a combination of width and class
123 -- It looks very like the old MachRep, but it's now of purely local
124 -- significance, here in the native code generator. You can change it
125 -- without global consequences.
127 -- A major use is as an opcode qualifier; thus the opcode
131 -- where the Size field encodes the ".l" part.
133 -- ToDo: it's not clear to me that we need separate signed-vs-unsigned sizes
134 -- here. I've removed them from the x86 version, we'll see what happens --SDM
136 -- ToDo: quite a few occurrences of Size could usefully be replaced by Width
138 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
139 data Size -- For these three, the "size" also gives the int/float
140 -- distinction, because the instructions for int/float
141 -- differ only in their suffices
142 = II8 | II16 | II32 | II64 | FF32 | FF64 | FF80
145 intSize, floatSize :: Width -> Size
150 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
154 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
157 wordSize = intSize wordWidth
159 sizeToWidth :: Size -> Width
161 sizeToWidth II16 = W16
162 sizeToWidth II32 = W32
163 sizeToWidth II64 = W64
164 sizeToWidth FF32 = W32
165 sizeToWidth FF64 = W64
166 sizeToWidth _ = panic "MachInstrs.sizeToWidth"
168 cmmTypeSize :: CmmType -> Size
169 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
170 | otherwise = intSize (typeWidth ty)
172 isFloatSize :: Size -> Bool
173 isFloatSize FF32 = True
174 isFloatSize FF64 = True
175 isFloatSize FF80 = True
176 isFloatSize other = False
179 #if alpha_TARGET_ARCH
183 -- | W -- word (2 bytes): UNUSED
185 | L -- longword (4 bytes)
186 | Q -- quadword (8 bytes)
187 -- | FF -- VAX F-style floating pt: UNUSED
188 -- | GF -- VAX G-style floating pt: UNUSED
189 -- | DF -- VAX D-style floating pt: UNUSED
190 -- | SF -- IEEE single-precision floating pt: UNUSED
191 | TF -- IEEE double-precision floating pt
195 #if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
198 | Bu -- byte (unsigned)
199 | H -- halfword (signed, 2 bytes)
200 | Hu -- halfword (unsigned, 2 bytes)
201 | W -- word (4 bytes)
202 | F -- IEEE single-precision floating pt
203 | DF -- IEEE single-precision floating pt
207 -- -----------------------------------------------------------------------------
212 | ImmInteger Integer -- Sigh.
213 | ImmCLbl CLabel -- AbstractC Label (with baggage)
214 | ImmLit Doc -- Simple string
215 | ImmIndex CLabel Int
218 | ImmConstantSum Imm Imm
219 | ImmConstantDiff Imm Imm
220 #if sparc_TARGET_ARCH
221 | LO Imm {- Possible restrictions... -}
224 #if powerpc_TARGET_ARCH
227 | HA Imm {- high halfword adjusted -}
229 strImmLit s = ImmLit (text s)
231 litToImm :: CmmLit -> Imm
232 litToImm (CmmInt i w) = ImmInteger (narrowS w i)
233 -- narrow to the width: a CmmInt might be out of
234 -- range, but we assume that ImmInteger only contains
235 -- in-range values. A signed value should be fine here.
236 litToImm (CmmFloat f W32) = ImmFloat f
237 litToImm (CmmFloat f W64) = ImmDouble f
238 litToImm (CmmLabel l) = ImmCLbl l
239 litToImm (CmmLabelOff l off) = ImmIndex l off
240 litToImm (CmmLabelDiffOff l1 l2 off)
242 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
244 litToImm (CmmBlock id) = ImmCLbl (infoTblLbl id)
246 -- -----------------------------------------------------------------------------
250 #if alpha_TARGET_ARCH
256 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
257 = AddrBaseIndex EABase EAIndex Displacement
260 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
261 data EAIndex = EAIndexNone | EAIndex Reg Int
262 type Displacement = Imm
265 #if sparc_TARGET_ARCH
270 #if powerpc_TARGET_ARCH
275 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
276 addrModeRegs :: AddrMode -> [Reg]
277 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
279 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
280 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
285 addrOffset :: AddrMode -> Int -> Maybe AddrMode
289 #if alpha_TARGET_ARCH
290 _ -> panic "MachMisc.addrOffset not defined for Alpha"
292 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
293 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
295 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
296 AddrBaseIndex r i (ImmInteger n)
297 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
299 AddrBaseIndex r i (ImmCLbl lbl)
300 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
302 AddrBaseIndex r i (ImmIndex lbl ix)
303 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
305 _ -> Nothing -- in theory, shouldn't happen
307 #if sparc_TARGET_ARCH
308 AddrRegImm r (ImmInt n)
309 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
310 | otherwise -> Nothing
313 AddrRegImm r (ImmInteger n)
314 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
315 | otherwise -> Nothing
316 where n2 = n + toInteger off
318 AddrRegReg r (RealReg 0)
319 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
320 | otherwise -> Nothing
324 #if powerpc_TARGET_ARCH
325 AddrRegImm r (ImmInt n)
326 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
327 | otherwise -> Nothing
330 AddrRegImm r (ImmInteger n)
331 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
332 | otherwise -> Nothing
333 where n2 = n + toInteger off
339 #if alpha_TARGET_ARCH
341 fits8Bits :: Integer -> Bool
342 fits8Bits i = i >= -256 && i < 256
346 #if sparc_TARGET_ARCH
348 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
349 fits13Bits :: Integral a => a -> Bool
350 fits13Bits x = x >= -4096 && x < 4096
354 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
355 ++show i++");\nprobably because of large constant data structures;" ++
356 "\nworkaround: use -fvia-C on this module.\n")
360 #if powerpc_TARGET_ARCH
361 fits16Bits :: Integral a => a -> Bool
362 fits16Bits x = x >= -32768 && x < 32768
364 makeImmediate :: Integral a => Width -> Bool -> a -> Maybe Imm
365 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
367 narrow W32 False = fromIntegral (fromIntegral x :: Word32)
368 narrow W16 False = fromIntegral (fromIntegral x :: Word16)
369 narrow W8 False = fromIntegral (fromIntegral x :: Word8)
370 narrow W32 True = fromIntegral (fromIntegral x :: Int32)
371 narrow W16 True = fromIntegral (fromIntegral x :: Int16)
372 narrow W8 True = fromIntegral (fromIntegral x :: Int8)
374 narrowed = narrow rep signed
377 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
378 | otherwise = Nothing
380 | narrowed >= 0 && narrowed < 65536 = Just narrowed
381 | otherwise = Nothing
382 toI16 _ _ = Just narrowed
386 -- @spRel@ gives us a stack relative addressing mode for volatile
387 -- temporaries and for excess call arguments. @fpRel@, where
388 -- applicable, is the same but for the frame pointer.
390 spRel :: Int -- desired stack offset in words, positive or negative
394 #if defined(i386_TARGET_ARCH)
395 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
396 #elif defined(x86_64_TARGET_ARCH)
397 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
399 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
402 #if sparc_TARGET_ARCH
403 fpRel :: Int -> AddrMode
404 -- Duznae work for offsets greater than 13 bits; we just hope for
407 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
410 #if x86_64_TARGET_ARCH
411 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
414 -- -----------------------------------------------------------------------------
417 -- We map STG registers onto appropriate CmmExprs. Either they map
418 -- to real machine registers or stored as offsets from BaseReg. Given
419 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
420 -- register it is in, on this platform, or a CmmExpr denoting the
421 -- address in the register table holding it.
422 -- (See also get_GlobalReg_addr in CgUtils.)
424 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
425 get_GlobalReg_reg_or_addr mid
426 = case globalRegMaybe mid of
428 Nothing -> Right (get_GlobalReg_addr mid)
430 -- ---------------------------------------------------------------------------
433 -- RealRegs are machine regs which are available for allocation, in
434 -- the usual way. We know what class they are, because that's part of
435 -- the processor's architecture.
437 -- VirtualRegs are virtual registers. The register allocator will
438 -- eventually have to map them into RealRegs, or into spill slots.
439 -- VirtualRegs are allocated on the fly, usually to represent a single
440 -- value in the abstract assembly code (i.e. dynamic registers are
441 -- usually single assignment). With the new register allocator, the
442 -- single assignment restriction isn't necessary to get correct code,
443 -- although a better register allocation will result if single
444 -- assignment is used -- because the allocator maps a VirtualReg into
445 -- a single RealReg, even if the VirtualReg has multiple live ranges.
447 -- Virtual regs can be of either class, so that info is attached.
449 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
450 -- when supplied with the vreg for the lower-half of the quantity.
451 -- (NB. Not reversible).
452 getHiVRegFromLo (VirtualRegI u)
453 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
454 getHiVRegFromLo other
455 = pprPanic "getHiVRegFromLo" (ppr other)
463 instance Uniquable RegClass where
464 getUnique RcInteger = mkUnique 'L' 0
465 getUnique RcFloat = mkUnique 'L' 1
466 getUnique RcDouble = mkUnique 'L' 2
471 = RealReg {-# UNPACK #-} !RegNo
472 | VirtualRegI {-# UNPACK #-} !Unique
473 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
474 | VirtualRegF {-# UNPACK #-} !Unique
475 | VirtualRegD {-# UNPACK #-} !Unique
478 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
479 -- in the register allocator.
480 instance Uniquable Reg where
481 getUnique (RealReg i) = mkUnique 'C' i
482 getUnique (VirtualRegI u) = u
483 getUnique (VirtualRegHi u) = u
484 getUnique (VirtualRegF u) = u
485 getUnique (VirtualRegD u) = u
487 unRealReg (RealReg i) = i
488 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
490 mkVReg :: Unique -> Size -> Reg
492 | not (isFloatSize size) = VirtualRegI u
495 #if sparc_TARGET_ARCH
496 FF32 -> VirtualRegF u
498 FF32 -> VirtualRegD u
500 FF64 -> VirtualRegD u
501 _other -> panic "mkVReg"
503 isVirtualReg :: Reg -> Bool
504 isVirtualReg (RealReg _) = False
505 isVirtualReg (VirtualRegI _) = True
506 isVirtualReg (VirtualRegHi _) = True
507 isVirtualReg (VirtualRegF _) = True
508 isVirtualReg (VirtualRegD _) = True
510 isRealReg :: Reg -> Bool
511 isRealReg = not . isVirtualReg
513 renameVirtualReg :: Unique -> Reg -> Reg
516 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
517 VirtualRegI _ -> VirtualRegI u
518 VirtualRegHi _ -> VirtualRegHi u
519 VirtualRegF _ -> VirtualRegF u
520 VirtualRegD _ -> VirtualRegD u
522 instance Show Reg where
523 show (RealReg i) = showReg i
524 show (VirtualRegI u) = "%vI_" ++ show u
525 show (VirtualRegHi u) = "%vHi_" ++ show u
526 show (VirtualRegF u) = "%vF_" ++ show u
527 show (VirtualRegD u) = "%vD_" ++ show u
529 instance Outputable RegClass where
530 ppr RcInteger = Outputable.text "I"
531 ppr RcFloat = Outputable.text "F"
532 ppr RcDouble = Outputable.text "D"
534 instance Outputable Reg where
535 ppr r = Outputable.text (show r)
540 -- trivColorable function for the graph coloring allocator
541 -- This gets hammered by scanGraph during register allocation,
542 -- so needs to be fairly efficient.
544 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
545 -- (which are disjoint) ie. x86, x86_64 and ppc
549 -- Doing a nice fold over the UniqSet makes trivColorable use
550 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
552 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
553 trivColorable classN conflicts exclusions
556 acc :: Reg -> (Int, Int) -> (Int, Int)
559 RcInteger -> (cd+1, cf)
560 RcDouble -> (cd, cf+1)
561 _ -> panic "MachRegs.trivColorable: reg class not handled"
563 tmp = foldUniqSet acc (0, 0) conflicts
564 (countInt, countFloat) = foldUniqSet acc tmp exclusions
566 squeese = worst countInt classN RcInteger
567 + worst countFloat classN RcDouble
569 in squeese < allocatableRegsInClass classN
571 -- | Worst case displacement
572 -- node N of classN has n neighbors of class C.
574 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
575 -- This is a bit boring compared to what's in RegArchX86.
577 worst :: Int -> RegClass -> RegClass -> Int
578 worst n classN classC
582 RcInteger -> min n (allocatableRegsInClass RcInteger)
587 RcDouble -> min n (allocatableRegsInClass RcDouble)
592 -- The number of allocatable regs is hard coded here so we can do a fast comparision
593 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
594 -- free regs, but they can't be more or the register conflict graph won't color.
596 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
597 -- is too slow for us here.
599 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
602 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
603 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
605 #elif x86_64_TARGET_ARCH
606 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
607 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
609 #elif powerpc_TARGET_ARCH
610 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
611 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
614 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
617 {-# INLINE regClass #-}
618 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
619 trivColorable classN conflicts exclusions
620 = {-# SCC "trivColorable" #-}
624 NodeUFM _ _ left right
625 -> case isSqueesed cI cF right of
628 False -> isSqueesed cI' cF' left
629 True -> (# True, cI', cF' #)
632 -> case regClass reg of
634 -> case cI +# _ILIT(1) of
635 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
638 -> case cF +# _ILIT(1) of
639 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
642 -> (# False, cI, cF #)
644 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
645 (# False, cI', cF' #)
646 -> case isSqueesed cI' cF' exclusions of
647 (# s, _, _ #) -> not s
654 -- -----------------------------------------------------------------------------
655 -- Machine-specific register stuff
657 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
658 -- point registers. The mapping of STG registers to alpha machine registers
659 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
661 #if alpha_TARGET_ARCH
665 v0, f0, ra, pv, gp, sp, zeroh :: Reg
667 f0 = realReg (fReg 0)
668 ra = FixedReg ILIT(26)
670 gp = FixedReg ILIT(29)
671 sp = FixedReg ILIT(30)
672 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
674 t9, t10, t11, t12 :: Reg
682 Intel x86 architecture:
683 - All registers except 7 (esp) are available for use.
684 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
685 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
686 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
687 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
688 fp registers, and 3-operand insns for them, and we translate this into
689 real stack-based x86 fp code after register allocation.
691 The fp registers are all Double registers; we don't have any RcFloat class
692 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
698 fake0, fake1, fake2, fake3, fake4, fake5,
699 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
716 -- On x86, we might want to have an 8-bit RegClass, which would
717 -- contain just regs 1-4 (the others don't have 8-bit versions).
718 -- However, we can get away without this at the moment because the
719 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
720 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
721 regClass (VirtualRegI u) = RcInteger
722 regClass (VirtualRegHi u) = RcInteger
723 regClass (VirtualRegD u) = RcDouble
724 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
725 (ppr (VirtualRegF u))
728 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
729 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
731 showReg :: RegNo -> String
733 = if n >= 0 && n < 14
735 else "%unknown_x86_real_reg_" ++ show n
741 AMD x86_64 architecture:
742 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
743 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
744 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
748 #if x86_64_TARGET_ARCH
750 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
751 r8, r9, r10, r11, r12, r13, r14, r15,
752 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
753 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
788 -- so we can re-use some x86 code:
798 xmm n = RealReg (16+n)
800 -- On x86, we might want to have an 8-bit RegClass, which would
801 -- contain just regs 1-4 (the others don't have 8-bit versions).
802 -- However, we can get away without this at the moment because the
803 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
804 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
805 regClass (VirtualRegI u) = RcInteger
806 regClass (VirtualRegHi u) = RcInteger
807 regClass (VirtualRegD u) = RcDouble
808 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
809 (ppr (VirtualRegF u))
812 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
814 showReg :: RegNo -> String
816 | n >= 16 = "%xmm" ++ show (n-16)
817 | n >= 8 = "%r" ++ show n
818 | otherwise = regNames !! n
823 The SPARC has 64 registers of interest; 32 integer registers and 32
824 floating point registers. The mapping of STG registers to SPARC
825 machine registers is defined in StgRegs.h. We are, of course,
826 prepared for any eventuality.
828 The whole fp-register pairing thing on sparcs is a huge nuisance. See
829 fptools/ghc/includes/MachRegs.h for a description of what's going on
833 #if sparc_TARGET_ARCH
835 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
842 nCG_FirstFloatReg :: RegNo
843 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
845 regClass (VirtualRegI u) = RcInteger
846 regClass (VirtualRegF u) = RcFloat
847 regClass (VirtualRegD u) = RcDouble
848 regClass (RealReg i) | i < 32 = RcInteger
849 | i < nCG_FirstFloatReg = RcDouble
850 | otherwise = RcFloat
852 showReg :: RegNo -> String
854 | n >= 0 && n < 8 = "%g" ++ show n
855 | n >= 8 && n < 16 = "%o" ++ show (n-8)
856 | n >= 16 && n < 24 = "%l" ++ show (n-16)
857 | n >= 24 && n < 32 = "%i" ++ show (n-24)
858 | n >= 32 && n < 64 = "%f" ++ show (n-32)
859 | otherwise = "%unknown_sparc_real_reg_" ++ show n
861 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
863 f6 = RealReg (fReg 6)
864 f8 = RealReg (fReg 8)
865 f22 = RealReg (fReg 22)
866 f26 = RealReg (fReg 26)
867 f27 = RealReg (fReg 27)
870 -- g0 is useful for codegen; is always zero, and writes to it vanish.
871 g0 = RealReg (gReg 0)
872 g1 = RealReg (gReg 1)
873 g2 = RealReg (gReg 2)
875 -- FP, SP, int and float return (from C) regs.
876 fp = RealReg (iReg 6)
877 sp = RealReg (oReg 6)
878 o0 = RealReg (oReg 0)
879 o1 = RealReg (oReg 1)
880 f0 = RealReg (fReg 0)
881 f1 = RealReg (fReg 1)
886 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
890 #if powerpc_TARGET_ARCH
894 regClass (VirtualRegI u) = RcInteger
895 regClass (VirtualRegHi u) = RcInteger
896 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
897 (ppr (VirtualRegF u))
898 regClass (VirtualRegD u) = RcDouble
899 regClass (RealReg i) | i < 32 = RcInteger
900 | otherwise = RcDouble
902 showReg :: RegNo -> String
904 | n >= 0 && n <= 31 = "%r" ++ show n
905 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
906 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
913 f1 = RealReg $ fReg 1
914 f20 = RealReg $ fReg 20
915 f21 = RealReg $ fReg 21
919 Redefine the literals used for machine-registers with non-numeric
920 names in the header files. Gag me with a spoon, eh?
923 #if alpha_TARGET_ARCH
974 #if x86_64_TARGET_ARCH
1009 #if sparc_TARGET_ARCH
1077 #if powerpc_TARGET_ARCH
1111 #ifdef darwin_TARGET_OS
1181 -- allMachRegs is the complete set of machine regs.
1182 allMachRegNos :: [RegNo]
1184 = IF_ARCH_alpha( [0..63],
1185 IF_ARCH_i386( [0..13],
1186 IF_ARCH_x86_64( [0..31],
1187 IF_ARCH_sparc( ([0..31]
1188 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1189 ++ [nCG_FirstFloatReg .. f31]),
1190 IF_ARCH_powerpc([0..63],
1193 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1194 -- i.e., these are the regs for which we are prepared to allow the
1195 -- register allocator to attempt to map VRegs to.
1196 allocatableRegs :: [RegNo]
1198 = let isFree i = isFastTrue (freeReg i)
1199 in filter isFree allMachRegNos
1202 -- | The number of regs in each class.
1203 -- We go via top level CAFs to ensure that we're not recomputing
1204 -- the length of these lists each time the fn is called.
1205 allocatableRegsInClass :: RegClass -> Int
1206 allocatableRegsInClass cls
1208 RcInteger -> allocatableRegsInteger
1209 RcDouble -> allocatableRegsDouble
1211 allocatableRegsInteger
1212 = length $ filter (\r -> regClass r == RcInteger)
1213 $ map RealReg allocatableRegs
1215 allocatableRegsDouble
1216 = length $ filter (\r -> regClass r == RcDouble)
1217 $ map RealReg allocatableRegs
1220 -- these are the regs which we cannot assume stay alive over a
1222 callClobberedRegs :: [Reg]
1225 #if alpha_TARGET_ARCH
1226 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1227 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1228 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1229 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1230 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1231 #endif /* alpha_TARGET_ARCH */
1232 #if i386_TARGET_ARCH
1233 -- caller-saves registers
1234 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1235 #endif /* i386_TARGET_ARCH */
1236 #if x86_64_TARGET_ARCH
1237 -- caller-saves registers
1238 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1239 -- all xmm regs are caller-saves
1240 #endif /* x86_64_TARGET_ARCH */
1241 #if sparc_TARGET_ARCH
1244 [oReg i | i <- [0..5]] ++
1245 [gReg i | i <- [1..7]] ++
1246 [fReg i | i <- [0..31]] )
1247 #endif /* sparc_TARGET_ARCH */
1248 #if powerpc_TARGET_ARCH
1249 #if darwin_TARGET_OS
1250 map RealReg (0:[2..12] ++ map fReg [0..13])
1251 #elif linux_TARGET_OS
1252 map RealReg (0:[2..13] ++ map fReg [0..13])
1254 #endif /* powerpc_TARGET_ARCH */
1257 -- argRegs is the set of regs which are read for an n-argument call to C.
1258 -- For archs which pass all args on the stack (x86), is empty.
1259 -- Sparc passes up to the first 6 args in regs.
1260 -- Dunno about Alpha.
1261 argRegs :: RegNo -> [Reg]
1263 #if i386_TARGET_ARCH
1264 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1267 #if x86_64_TARGET_ARCH
1268 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1271 #if alpha_TARGET_ARCH
1273 argRegs 1 = freeMappedRegs [16, fReg 16]
1274 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1275 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1276 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1277 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1278 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1279 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1280 #endif /* alpha_TARGET_ARCH */
1282 #if sparc_TARGET_ARCH
1284 argRegs 1 = map (RealReg . oReg) [0]
1285 argRegs 2 = map (RealReg . oReg) [0,1]
1286 argRegs 3 = map (RealReg . oReg) [0,1,2]
1287 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1288 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1289 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1290 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1291 #endif /* sparc_TARGET_ARCH */
1293 #if powerpc_TARGET_ARCH
1295 argRegs 1 = map RealReg [3]
1296 argRegs 2 = map RealReg [3,4]
1297 argRegs 3 = map RealReg [3..5]
1298 argRegs 4 = map RealReg [3..6]
1299 argRegs 5 = map RealReg [3..7]
1300 argRegs 6 = map RealReg [3..8]
1301 argRegs 7 = map RealReg [3..9]
1302 argRegs 8 = map RealReg [3..10]
1303 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1304 #endif /* powerpc_TARGET_ARCH */
1307 -- all of the arg regs ??
1308 #if alpha_TARGET_ARCH
1309 allArgRegs :: [(Reg, Reg)]
1310 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1311 #endif /* alpha_TARGET_ARCH */
1313 #if sparc_TARGET_ARCH
1315 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1316 #endif /* sparc_TARGET_ARCH */
1318 #if i386_TARGET_ARCH
1320 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1323 #if x86_64_TARGET_ARCH
1325 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1326 allFPArgRegs :: [Reg]
1327 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1330 #if powerpc_TARGET_ARCH
1332 allArgRegs = map RealReg [3..10]
1333 allFPArgRegs :: [Reg]
1334 #if darwin_TARGET_OS
1335 allFPArgRegs = map (RealReg . fReg) [1..13]
1336 #elif linux_TARGET_OS
1337 allFPArgRegs = map (RealReg . fReg) [1..8]
1339 #endif /* powerpc_TARGET_ARCH */
1343 freeReg :: RegNo -> FastBool
1345 #if alpha_TARGET_ARCH
1346 freeReg 26 = fastBool False -- return address (ra)
1347 freeReg 28 = fastBool False -- reserved for the assembler (at)
1348 freeReg 29 = fastBool False -- global pointer (gp)
1349 freeReg 30 = fastBool False -- stack pointer (sp)
1350 freeReg 31 = fastBool False -- always zero (zeroh)
1351 freeReg 63 = fastBool False -- always zero (f31)
1354 #if i386_TARGET_ARCH
1355 freeReg esp = fastBool False -- %esp is the C stack pointer
1358 #if x86_64_TARGET_ARCH
1359 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1362 #if sparc_TARGET_ARCH
1363 freeReg g0 = fastBool False -- %g0 is always 0.
1364 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1365 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1366 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1367 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1368 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1369 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1370 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1371 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1372 freeReg f1 = fastBool False
1375 #if powerpc_TARGET_ARCH
1376 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1377 freeReg 1 = fastBool False -- The Stack Pointer
1378 #if !darwin_TARGET_OS
1379 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1380 freeReg 2 = fastBool False
1385 freeReg REG_Base = fastBool False
1388 freeReg REG_R1 = fastBool False
1391 freeReg REG_R2 = fastBool False
1394 freeReg REG_R3 = fastBool False
1397 freeReg REG_R4 = fastBool False
1400 freeReg REG_R5 = fastBool False
1403 freeReg REG_R6 = fastBool False
1406 freeReg REG_R7 = fastBool False
1409 freeReg REG_R8 = fastBool False
1412 freeReg REG_F1 = fastBool False
1415 freeReg REG_F2 = fastBool False
1418 freeReg REG_F3 = fastBool False
1421 freeReg REG_F4 = fastBool False
1424 freeReg REG_D1 = fastBool False
1427 freeReg REG_D2 = fastBool False
1430 freeReg REG_Sp = fastBool False
1433 freeReg REG_Su = fastBool False
1436 freeReg REG_SpLim = fastBool False
1439 freeReg REG_Hp = fastBool False
1442 freeReg REG_HpLim = fastBool False
1444 freeReg n = fastBool True
1447 -- | Returns 'Nothing' if this global register is not stored
1448 -- in a real machine register, otherwise returns @'Just' reg@, where
1449 -- reg is the machine register it is stored in.
1451 globalRegMaybe :: GlobalReg -> Maybe Reg
1454 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1457 globalRegMaybe (VanillaReg 1 _) = Just (RealReg REG_R1)
1460 globalRegMaybe (VanillaReg 2 _) = Just (RealReg REG_R2)
1463 globalRegMaybe (VanillaReg 3 _) = Just (RealReg REG_R3)
1466 globalRegMaybe (VanillaReg 4 _) = Just (RealReg REG_R4)
1469 globalRegMaybe (VanillaReg 5 _) = Just (RealReg REG_R5)
1472 globalRegMaybe (VanillaReg 6 _) = Just (RealReg REG_R6)
1475 globalRegMaybe (VanillaReg 7 _) = Just (RealReg REG_R7)
1478 globalRegMaybe (VanillaReg 8 _) = Just (RealReg REG_R8)
1481 globalRegMaybe (VanillaReg 9 _) = Just (RealReg REG_R9)
1484 globalRegMaybe (VanillaReg 10 _) = Just (RealReg REG_R10)
1487 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1490 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1493 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1496 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1499 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1502 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1505 globalRegMaybe Sp = Just (RealReg REG_Sp)
1508 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1511 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1514 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1517 globalRegMaybe Hp = Just (RealReg REG_Hp)
1520 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1522 #ifdef REG_CurrentTSO
1523 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1525 #ifdef REG_CurrentNursery
1526 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1528 globalRegMaybe _ = Nothing