1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Imm(..), strImmLit, litToImm,
36 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
37 RegClass(..), regClass,
43 get_GlobalReg_reg_or_addr,
45 -- * Machine-dependent register-related stuff
46 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
47 allocatableRegsInClass,
54 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
57 EABase(..), EAIndex(..),
58 eax, ebx, ecx, edx, esi, edi, ebp, esp,
59 fake0, fake1, fake2, fake3, fake4, fake5,
62 #if x86_64_TARGET_ARCH
63 EABase(..), EAIndex(..), ripRel,
64 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
65 eax, ebx, ecx, edx, esi, edi, ebp, esp,
66 r8, r9, r10, r11, r12, r13, r14, r15,
67 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
68 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
70 addrModeRegs, allFPArgRegs,
74 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
75 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
77 #if powerpc_TARGET_ARCH
86 #include "HsVersions.h"
89 # define STOLEN_X86_REGS 4
90 -- HACK: go for the max
93 #include "../includes/MachRegs.h"
96 import MachOp ( MachRep(..) )
97 import CgUtils ( get_GlobalReg_addr )
99 import CLabel ( CLabel, mkMainCapabilityLabel )
101 import Outputable ( Outputable(..), pprPanic, panic )
102 import qualified Outputable
108 import qualified UniqFM as S
111 #if powerpc_TARGET_ARCH
112 import Data.Word ( Word8, Word16, Word32 )
113 import Data.Int ( Int8, Int16, Int32 )
116 -- -----------------------------------------------------------------------------
121 | ImmInteger Integer -- Sigh.
122 | ImmCLbl CLabel -- AbstractC Label (with baggage)
123 | ImmLit Doc -- Simple string
124 | ImmIndex CLabel Int
127 | ImmConstantSum Imm Imm
128 | ImmConstantDiff Imm Imm
129 #if sparc_TARGET_ARCH
130 | LO Imm {- Possible restrictions... -}
133 #if powerpc_TARGET_ARCH
136 | HA Imm {- high halfword adjusted -}
138 strImmLit s = ImmLit (text s)
140 litToImm :: CmmLit -> Imm
141 litToImm (CmmInt i _) = ImmInteger i
142 litToImm (CmmFloat f F32) = ImmFloat f
143 litToImm (CmmFloat f F64) = ImmDouble f
144 litToImm (CmmLabel l) = ImmCLbl l
145 litToImm (CmmLabelOff l off) = ImmIndex l off
146 litToImm (CmmLabelDiffOff l1 l2 off)
148 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
151 -- -----------------------------------------------------------------------------
155 #if alpha_TARGET_ARCH
161 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
162 = AddrBaseIndex EABase EAIndex Displacement
165 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
166 data EAIndex = EAIndexNone | EAIndex Reg Int
167 type Displacement = Imm
170 #if sparc_TARGET_ARCH
175 #if powerpc_TARGET_ARCH
180 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
181 addrModeRegs :: AddrMode -> [Reg]
182 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
184 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
185 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
190 addrOffset :: AddrMode -> Int -> Maybe AddrMode
194 #if alpha_TARGET_ARCH
195 _ -> panic "MachMisc.addrOffset not defined for Alpha"
197 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
198 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
200 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
201 AddrBaseIndex r i (ImmInteger n)
202 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
204 AddrBaseIndex r i (ImmCLbl lbl)
205 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
207 AddrBaseIndex r i (ImmIndex lbl ix)
208 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
210 _ -> Nothing -- in theory, shouldn't happen
212 #if sparc_TARGET_ARCH
213 AddrRegImm r (ImmInt n)
214 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
215 | otherwise -> Nothing
218 AddrRegImm r (ImmInteger n)
219 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
220 | otherwise -> Nothing
221 where n2 = n + toInteger off
223 AddrRegReg r (RealReg 0)
224 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
225 | otherwise -> Nothing
229 #if powerpc_TARGET_ARCH
230 AddrRegImm r (ImmInt n)
231 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
232 | otherwise -> Nothing
235 AddrRegImm r (ImmInteger n)
236 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
237 | otherwise -> Nothing
238 where n2 = n + toInteger off
244 #if alpha_TARGET_ARCH
246 fits8Bits :: Integer -> Bool
247 fits8Bits i = i >= -256 && i < 256
251 #if sparc_TARGET_ARCH
253 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
254 fits13Bits :: Integral a => a -> Bool
255 fits13Bits x = x >= -4096 && x < 4096
259 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
260 ++show i++");\nprobably because of large constant data structures;" ++
261 "\nworkaround: use -fvia-C on this module.\n")
265 #if powerpc_TARGET_ARCH
266 fits16Bits :: Integral a => a -> Bool
267 fits16Bits x = x >= -32768 && x < 32768
269 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
271 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
273 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
274 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
275 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
276 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
277 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
278 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
280 narrowed = narrow rep signed
283 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
284 | otherwise = Nothing
286 | narrowed >= 0 && narrowed < 65536 = Just narrowed
287 | otherwise = Nothing
288 toI16 _ _ = Just narrowed
292 -- @spRel@ gives us a stack relative addressing mode for volatile
293 -- temporaries and for excess call arguments. @fpRel@, where
294 -- applicable, is the same but for the frame pointer.
296 spRel :: Int -- desired stack offset in words, positive or negative
300 #if defined(i386_TARGET_ARCH)
301 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
302 #elif defined(x86_64_TARGET_ARCH)
303 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
305 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
308 #if sparc_TARGET_ARCH
309 fpRel :: Int -> AddrMode
310 -- Duznae work for offsets greater than 13 bits; we just hope for
313 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
316 #if x86_64_TARGET_ARCH
317 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
320 -- -----------------------------------------------------------------------------
323 -- We map STG registers onto appropriate CmmExprs. Either they map
324 -- to real machine registers or stored as offsets from BaseReg. Given
325 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
326 -- register it is in, on this platform, or a CmmExpr denoting the
327 -- address in the register table holding it.
328 -- (See also get_GlobalReg_addr in CgUtils.)
330 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
331 get_GlobalReg_reg_or_addr mid
332 = case globalRegMaybe mid of
334 Nothing -> Right (get_GlobalReg_addr mid)
336 -- ---------------------------------------------------------------------------
339 -- RealRegs are machine regs which are available for allocation, in
340 -- the usual way. We know what class they are, because that's part of
341 -- the processor's architecture.
343 -- VirtualRegs are virtual registers. The register allocator will
344 -- eventually have to map them into RealRegs, or into spill slots.
345 -- VirtualRegs are allocated on the fly, usually to represent a single
346 -- value in the abstract assembly code (i.e. dynamic registers are
347 -- usually single assignment). With the new register allocator, the
348 -- single assignment restriction isn't necessary to get correct code,
349 -- although a better register allocation will result if single
350 -- assignment is used -- because the allocator maps a VirtualReg into
351 -- a single RealReg, even if the VirtualReg has multiple live ranges.
353 -- Virtual regs can be of either class, so that info is attached.
355 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
356 -- when supplied with the vreg for the lower-half of the quantity.
357 -- (NB. Not reversible).
358 getHiVRegFromLo (VirtualRegI u)
359 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
360 getHiVRegFromLo other
361 = pprPanic "getHiVRegFromLo" (ppr other)
369 instance Uniquable RegClass where
370 getUnique RcInteger = mkUnique 'L' 0
371 getUnique RcFloat = mkUnique 'L' 1
372 getUnique RcDouble = mkUnique 'L' 2
377 = RealReg {-# UNPACK #-} !RegNo
378 | VirtualRegI {-# UNPACK #-} !Unique
379 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
380 | VirtualRegF {-# UNPACK #-} !Unique
381 | VirtualRegD {-# UNPACK #-} !Unique
384 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
385 -- in the register allocator.
386 instance Uniquable Reg where
387 getUnique (RealReg i) = mkUnique 'C' i
388 getUnique (VirtualRegI u) = u
389 getUnique (VirtualRegHi u) = u
390 getUnique (VirtualRegF u) = u
391 getUnique (VirtualRegD u) = u
393 unRealReg (RealReg i) = i
394 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
396 mkVReg :: Unique -> MachRep -> Reg
399 #if sparc_TARGET_ARCH
405 other -> VirtualRegI u
407 isVirtualReg :: Reg -> Bool
408 isVirtualReg (RealReg _) = False
409 isVirtualReg (VirtualRegI _) = True
410 isVirtualReg (VirtualRegHi _) = True
411 isVirtualReg (VirtualRegF _) = True
412 isVirtualReg (VirtualRegD _) = True
414 isRealReg :: Reg -> Bool
415 isRealReg = not . isVirtualReg
417 renameVirtualReg :: Unique -> Reg -> Reg
420 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
421 VirtualRegI _ -> VirtualRegI u
422 VirtualRegHi _ -> VirtualRegHi u
423 VirtualRegF _ -> VirtualRegF u
424 VirtualRegD _ -> VirtualRegD u
426 instance Show Reg where
427 show (RealReg i) = showReg i
428 show (VirtualRegI u) = "%vI_" ++ show u
429 show (VirtualRegHi u) = "%vHi_" ++ show u
430 show (VirtualRegF u) = "%vF_" ++ show u
431 show (VirtualRegD u) = "%vD_" ++ show u
433 instance Outputable RegClass where
434 ppr RcInteger = Outputable.text "I"
435 ppr RcFloat = Outputable.text "F"
436 ppr RcDouble = Outputable.text "D"
438 instance Outputable Reg where
439 ppr r = Outputable.text (show r)
444 -- trivColorable function for the graph coloring allocator
445 -- This gets hammered by scanGraph during register allocation,
446 -- so needs to be fairly efficient.
448 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
449 -- (which are disjoint) ie. x86, x86_64 and ppc
453 -- Doing a nice fold over the UniqSet makes trivColorable use
454 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
456 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
457 trivColorable classN conflicts exclusions
460 acc :: Reg -> (Int, Int) -> (Int, Int)
463 RcInteger -> (cd+1, cf)
464 RcDouble -> (cd, cf+1)
465 _ -> panic "MachRegs.trivColorable: reg class not handled"
467 tmp = foldUniqSet acc (0, 0) conflicts
468 (countInt, countFloat) = foldUniqSet acc tmp exclusions
470 squeese = worst countInt classN RcInteger
471 + worst countFloat classN RcDouble
473 in squeese < allocatableRegsInClass classN
475 -- | Worst case displacement
476 -- node N of classN has n neighbors of class C.
478 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
479 -- This is a bit boring compared to what's in RegArchX86.
481 worst :: Int -> RegClass -> RegClass -> Int
482 worst n classN classC
486 RcInteger -> min n (allocatableRegsInClass RcInteger)
491 RcDouble -> min n (allocatableRegsInClass RcDouble)
496 -- The number of allocatable regs is hard coded here so we can do a fast comparision
497 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
498 -- free regs, but they can't be more or the register conflict graph won't color.
500 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
501 -- is too slow for us here.
503 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
506 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
507 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
509 #elif x86_64_TARGET_ARCH
510 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
511 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
513 #elif powerpc_TARGET_ARCH
514 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
515 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
518 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
521 {-# INLINE regClass #-}
522 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
523 trivColorable classN (MkUniqFM conflicts) (MkUniqFM exclusions)
524 = {-# SCC "trivColorable" #-}
526 {-# INLINE isSqueesed #-}
529 S.NodeUFM _ _ left right
530 -> case isSqueesed cI cF right of
533 False -> isSqueesed cI' cF' left
534 True -> (# True, cI', cF' #)
536 S.LeafUFM _ (Lazy reg)
537 -> case regClass reg of
539 -> case cI +# _ILIT(1) of
540 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
543 -> case cF +# _ILIT(1) of
544 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
547 -> (# False, cI, cF #)
549 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
550 (# False, cI', cF' #)
551 -> case isSqueesed cI' cF' exclusions of
552 (# s, _, _ #) -> not s
559 -- -----------------------------------------------------------------------------
560 -- Machine-specific register stuff
562 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
563 -- point registers. The mapping of STG registers to alpha machine registers
564 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
566 #if alpha_TARGET_ARCH
570 v0, f0, ra, pv, gp, sp, zeroh :: Reg
572 f0 = realReg (fReg 0)
573 ra = FixedReg ILIT(26)
575 gp = FixedReg ILIT(29)
576 sp = FixedReg ILIT(30)
577 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
579 t9, t10, t11, t12 :: Reg
587 Intel x86 architecture:
588 - All registers except 7 (esp) are available for use.
589 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
590 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
591 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
592 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
593 fp registers, and 3-operand insns for them, and we translate this into
594 real stack-based x86 fp code after register allocation.
596 The fp registers are all Double registers; we don't have any RcFloat class
597 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
603 fake0, fake1, fake2, fake3, fake4, fake5,
604 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
621 -- On x86, we might want to have an 8-bit RegClass, which would
622 -- contain just regs 1-4 (the others don't have 8-bit versions).
623 -- However, we can get away without this at the moment because the
624 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
625 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
626 regClass (VirtualRegI u) = RcInteger
627 regClass (VirtualRegHi u) = RcInteger
628 regClass (VirtualRegD u) = RcDouble
629 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
630 (ppr (VirtualRegF u))
633 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
634 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
636 showReg :: RegNo -> String
638 = if n >= 0 && n < 14
640 else "%unknown_x86_real_reg_" ++ show n
646 AMD x86_64 architecture:
647 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
648 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
649 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
653 #if x86_64_TARGET_ARCH
655 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
656 r8, r9, r10, r11, r12, r13, r14, r15,
657 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
658 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
693 -- so we can re-use some x86 code:
703 xmm n = RealReg (16+n)
705 -- On x86, we might want to have an 8-bit RegClass, which would
706 -- contain just regs 1-4 (the others don't have 8-bit versions).
707 -- However, we can get away without this at the moment because the
708 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
709 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
710 regClass (VirtualRegI u) = RcInteger
711 regClass (VirtualRegHi u) = RcInteger
712 regClass (VirtualRegD u) = RcDouble
713 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
714 (ppr (VirtualRegF u))
717 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
719 showReg :: RegNo -> String
721 | n >= 16 = "%xmm" ++ show (n-16)
722 | n >= 8 = "%r" ++ show n
723 | otherwise = regNames !! n
728 The SPARC has 64 registers of interest; 32 integer registers and 32
729 floating point registers. The mapping of STG registers to SPARC
730 machine registers is defined in StgRegs.h. We are, of course,
731 prepared for any eventuality.
733 The whole fp-register pairing thing on sparcs is a huge nuisance. See
734 fptools/ghc/includes/MachRegs.h for a description of what's going on
738 #if sparc_TARGET_ARCH
740 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
747 nCG_FirstFloatReg :: RegNo
748 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
750 regClass (VirtualRegI u) = RcInteger
751 regClass (VirtualRegF u) = RcFloat
752 regClass (VirtualRegD u) = RcDouble
753 regClass (RealReg i) | i < 32 = RcInteger
754 | i < nCG_FirstFloatReg = RcDouble
755 | otherwise = RcFloat
757 showReg :: RegNo -> String
759 | n >= 0 && n < 8 = "%g" ++ show n
760 | n >= 8 && n < 16 = "%o" ++ show (n-8)
761 | n >= 16 && n < 24 = "%l" ++ show (n-16)
762 | n >= 24 && n < 32 = "%i" ++ show (n-24)
763 | n >= 32 && n < 64 = "%f" ++ show (n-32)
764 | otherwise = "%unknown_sparc_real_reg_" ++ show n
766 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
768 f6 = RealReg (fReg 6)
769 f8 = RealReg (fReg 8)
770 f22 = RealReg (fReg 22)
771 f26 = RealReg (fReg 26)
772 f27 = RealReg (fReg 27)
775 -- g0 is useful for codegen; is always zero, and writes to it vanish.
776 g0 = RealReg (gReg 0)
777 g1 = RealReg (gReg 1)
778 g2 = RealReg (gReg 2)
780 -- FP, SP, int and float return (from C) regs.
781 fp = RealReg (iReg 6)
782 sp = RealReg (oReg 6)
783 o0 = RealReg (oReg 0)
784 o1 = RealReg (oReg 1)
785 f0 = RealReg (fReg 0)
786 f1 = RealReg (fReg 1)
791 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
795 #if powerpc_TARGET_ARCH
799 regClass (VirtualRegI u) = RcInteger
800 regClass (VirtualRegHi u) = RcInteger
801 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
802 (ppr (VirtualRegF u))
803 regClass (VirtualRegD u) = RcDouble
804 regClass (RealReg i) | i < 32 = RcInteger
805 | otherwise = RcDouble
807 showReg :: RegNo -> String
809 | n >= 0 && n <= 31 = "%r" ++ show n
810 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
811 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
818 f1 = RealReg $ fReg 1
819 f20 = RealReg $ fReg 20
820 f21 = RealReg $ fReg 21
824 Redefine the literals used for machine-registers with non-numeric
825 names in the header files. Gag me with a spoon, eh?
828 #if alpha_TARGET_ARCH
879 #if x86_64_TARGET_ARCH
914 #if sparc_TARGET_ARCH
982 #if powerpc_TARGET_ARCH
1016 #ifdef darwin_TARGET_OS
1086 -- allMachRegs is the complete set of machine regs.
1087 allMachRegNos :: [RegNo]
1089 = IF_ARCH_alpha( [0..63],
1090 IF_ARCH_i386( [0..13],
1091 IF_ARCH_x86_64( [0..31],
1092 IF_ARCH_sparc( ([0..31]
1093 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1094 ++ [nCG_FirstFloatReg .. f31]),
1095 IF_ARCH_powerpc([0..63],
1098 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1099 -- i.e., these are the regs for which we are prepared to allow the
1100 -- register allocator to attempt to map VRegs to.
1101 allocatableRegs :: [RegNo]
1103 = let isFree i = isFastTrue (freeReg i)
1104 in filter isFree allMachRegNos
1107 -- | The number of regs in each class.
1108 -- We go via top level CAFs to ensure that we're not recomputing
1109 -- the length of these lists each time the fn is called.
1110 allocatableRegsInClass :: RegClass -> Int
1111 allocatableRegsInClass cls
1113 RcInteger -> allocatableRegsInteger
1114 RcDouble -> allocatableRegsDouble
1116 allocatableRegsInteger
1117 = length $ filter (\r -> regClass r == RcInteger)
1118 $ map RealReg allocatableRegs
1120 allocatableRegsDouble
1121 = length $ filter (\r -> regClass r == RcDouble)
1122 $ map RealReg allocatableRegs
1125 -- these are the regs which we cannot assume stay alive over a
1127 callClobberedRegs :: [Reg]
1130 #if alpha_TARGET_ARCH
1131 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1132 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1133 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1134 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1135 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1136 #endif /* alpha_TARGET_ARCH */
1137 #if i386_TARGET_ARCH
1138 -- caller-saves registers
1139 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1140 #endif /* i386_TARGET_ARCH */
1141 #if x86_64_TARGET_ARCH
1142 -- caller-saves registers
1143 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1144 -- all xmm regs are caller-saves
1145 #endif /* x86_64_TARGET_ARCH */
1146 #if sparc_TARGET_ARCH
1149 [oReg i | i <- [0..5]] ++
1150 [gReg i | i <- [1..7]] ++
1151 [fReg i | i <- [0..31]] )
1152 #endif /* sparc_TARGET_ARCH */
1153 #if powerpc_TARGET_ARCH
1154 #if darwin_TARGET_OS
1155 map RealReg (0:[2..12] ++ map fReg [0..13])
1156 #elif linux_TARGET_OS
1157 map RealReg (0:[2..13] ++ map fReg [0..13])
1159 #endif /* powerpc_TARGET_ARCH */
1162 -- argRegs is the set of regs which are read for an n-argument call to C.
1163 -- For archs which pass all args on the stack (x86), is empty.
1164 -- Sparc passes up to the first 6 args in regs.
1165 -- Dunno about Alpha.
1166 argRegs :: RegNo -> [Reg]
1168 #if i386_TARGET_ARCH
1169 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1172 #if x86_64_TARGET_ARCH
1173 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1176 #if alpha_TARGET_ARCH
1178 argRegs 1 = freeMappedRegs [16, fReg 16]
1179 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1180 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1181 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1182 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1183 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1184 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1185 #endif /* alpha_TARGET_ARCH */
1187 #if sparc_TARGET_ARCH
1189 argRegs 1 = map (RealReg . oReg) [0]
1190 argRegs 2 = map (RealReg . oReg) [0,1]
1191 argRegs 3 = map (RealReg . oReg) [0,1,2]
1192 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1193 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1194 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1195 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1196 #endif /* sparc_TARGET_ARCH */
1198 #if powerpc_TARGET_ARCH
1200 argRegs 1 = map RealReg [3]
1201 argRegs 2 = map RealReg [3,4]
1202 argRegs 3 = map RealReg [3..5]
1203 argRegs 4 = map RealReg [3..6]
1204 argRegs 5 = map RealReg [3..7]
1205 argRegs 6 = map RealReg [3..8]
1206 argRegs 7 = map RealReg [3..9]
1207 argRegs 8 = map RealReg [3..10]
1208 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1209 #endif /* powerpc_TARGET_ARCH */
1212 -- all of the arg regs ??
1213 #if alpha_TARGET_ARCH
1214 allArgRegs :: [(Reg, Reg)]
1215 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1216 #endif /* alpha_TARGET_ARCH */
1218 #if sparc_TARGET_ARCH
1220 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1221 #endif /* sparc_TARGET_ARCH */
1223 #if i386_TARGET_ARCH
1225 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1228 #if x86_64_TARGET_ARCH
1230 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1231 allFPArgRegs :: [Reg]
1232 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1235 #if powerpc_TARGET_ARCH
1237 allArgRegs = map RealReg [3..10]
1238 allFPArgRegs :: [Reg]
1239 #if darwin_TARGET_OS
1240 allFPArgRegs = map (RealReg . fReg) [1..13]
1241 #elif linux_TARGET_OS
1242 allFPArgRegs = map (RealReg . fReg) [1..8]
1244 #endif /* powerpc_TARGET_ARCH */
1248 freeReg :: RegNo -> FastBool
1250 #if alpha_TARGET_ARCH
1251 freeReg 26 = fastBool False -- return address (ra)
1252 freeReg 28 = fastBool False -- reserved for the assembler (at)
1253 freeReg 29 = fastBool False -- global pointer (gp)
1254 freeReg 30 = fastBool False -- stack pointer (sp)
1255 freeReg 31 = fastBool False -- always zero (zeroh)
1256 freeReg 63 = fastBool False -- always zero (f31)
1259 #if i386_TARGET_ARCH
1260 freeReg esp = fastBool False -- %esp is the C stack pointer
1263 #if x86_64_TARGET_ARCH
1264 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1267 #if sparc_TARGET_ARCH
1268 freeReg g0 = fastBool False -- %g0 is always 0.
1269 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1270 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1271 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1272 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1273 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1274 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1275 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1276 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1277 freeReg f1 = fastBool False
1280 #if powerpc_TARGET_ARCH
1281 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1282 freeReg 1 = fastBool False -- The Stack Pointer
1283 #if !darwin_TARGET_OS
1284 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1285 freeReg 2 = fastBool False
1290 freeReg REG_Base = fastBool False
1293 freeReg REG_R1 = fastBool False
1296 freeReg REG_R2 = fastBool False
1299 freeReg REG_R3 = fastBool False
1302 freeReg REG_R4 = fastBool False
1305 freeReg REG_R5 = fastBool False
1308 freeReg REG_R6 = fastBool False
1311 freeReg REG_R7 = fastBool False
1314 freeReg REG_R8 = fastBool False
1317 freeReg REG_F1 = fastBool False
1320 freeReg REG_F2 = fastBool False
1323 freeReg REG_F3 = fastBool False
1326 freeReg REG_F4 = fastBool False
1329 freeReg REG_D1 = fastBool False
1332 freeReg REG_D2 = fastBool False
1335 freeReg REG_Sp = fastBool False
1338 freeReg REG_Su = fastBool False
1341 freeReg REG_SpLim = fastBool False
1344 freeReg REG_Hp = fastBool False
1347 freeReg REG_HpLim = fastBool False
1349 freeReg n = fastBool True
1352 -- | Returns 'Nothing' if this global register is not stored
1353 -- in a real machine register, otherwise returns @'Just' reg@, where
1354 -- reg is the machine register it is stored in.
1356 globalRegMaybe :: GlobalReg -> Maybe Reg
1359 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1362 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1365 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1368 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1371 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1374 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1377 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1380 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1383 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1386 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1389 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1392 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1395 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1398 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1401 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1404 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1407 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1410 globalRegMaybe Sp = Just (RealReg REG_Sp)
1413 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1416 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1419 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1422 globalRegMaybe Hp = Just (RealReg REG_Hp)
1425 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1427 #ifdef REG_CurrentTSO
1428 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1430 #ifdef REG_CurrentNursery
1431 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1433 globalRegMaybe _ = Nothing