1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Imm(..), strImmLit, litToImm,
36 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
37 RegClass(..), regClass,
43 get_GlobalReg_reg_or_addr,
45 -- * Machine-dependent register-related stuff
46 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
47 allocatableRegsInClass,
54 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
57 EABase(..), EAIndex(..),
58 eax, ebx, ecx, edx, esi, edi, ebp, esp,
59 fake0, fake1, fake2, fake3, fake4, fake5,
62 #if x86_64_TARGET_ARCH
63 EABase(..), EAIndex(..), ripRel,
64 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
65 eax, ebx, ecx, edx, esi, edi, ebp, esp,
66 r8, r9, r10, r11, r12, r13, r14, r15,
67 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
68 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
70 addrModeRegs, allFPArgRegs,
74 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
75 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
77 #if powerpc_TARGET_ARCH
86 #include "HsVersions.h"
89 # define STOLEN_X86_REGS 4
90 -- HACK: go for the max
93 #include "../includes/MachRegs.h"
96 import MachOp ( MachRep(..) )
97 import CgUtils ( get_GlobalReg_addr )
99 import CLabel ( CLabel, mkMainCapabilityLabel )
101 import Outputable ( Outputable(..), pprPanic, panic )
102 import qualified Outputable
110 #if powerpc_TARGET_ARCH
111 import Data.Word ( Word8, Word16, Word32 )
112 import Data.Int ( Int8, Int16, Int32 )
115 -- -----------------------------------------------------------------------------
120 | ImmInteger Integer -- Sigh.
121 | ImmCLbl CLabel -- AbstractC Label (with baggage)
122 | ImmLit Doc -- Simple string
123 | ImmIndex CLabel Int
126 | ImmConstantSum Imm Imm
127 | ImmConstantDiff Imm Imm
128 #if sparc_TARGET_ARCH
129 | LO Imm {- Possible restrictions... -}
132 #if powerpc_TARGET_ARCH
135 | HA Imm {- high halfword adjusted -}
137 strImmLit s = ImmLit (text s)
139 litToImm :: CmmLit -> Imm
140 litToImm (CmmInt i _) = ImmInteger i
141 litToImm (CmmFloat f F32) = ImmFloat f
142 litToImm (CmmFloat f F64) = ImmDouble f
143 litToImm (CmmLabel l) = ImmCLbl l
144 litToImm (CmmLabelOff l off) = ImmIndex l off
145 litToImm (CmmLabelDiffOff l1 l2 off)
147 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
150 -- -----------------------------------------------------------------------------
154 #if alpha_TARGET_ARCH
160 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
161 = AddrBaseIndex EABase EAIndex Displacement
164 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
165 data EAIndex = EAIndexNone | EAIndex Reg Int
166 type Displacement = Imm
169 #if sparc_TARGET_ARCH
174 #if powerpc_TARGET_ARCH
179 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
180 addrModeRegs :: AddrMode -> [Reg]
181 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
183 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
184 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
189 addrOffset :: AddrMode -> Int -> Maybe AddrMode
193 #if alpha_TARGET_ARCH
194 _ -> panic "MachMisc.addrOffset not defined for Alpha"
196 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
197 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
199 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
200 AddrBaseIndex r i (ImmInteger n)
201 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
203 AddrBaseIndex r i (ImmCLbl lbl)
204 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
206 AddrBaseIndex r i (ImmIndex lbl ix)
207 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
209 _ -> Nothing -- in theory, shouldn't happen
211 #if sparc_TARGET_ARCH
212 AddrRegImm r (ImmInt n)
213 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
214 | otherwise -> Nothing
217 AddrRegImm r (ImmInteger n)
218 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
219 | otherwise -> Nothing
220 where n2 = n + toInteger off
222 AddrRegReg r (RealReg 0)
223 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
224 | otherwise -> Nothing
228 #if powerpc_TARGET_ARCH
229 AddrRegImm r (ImmInt n)
230 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
231 | otherwise -> Nothing
234 AddrRegImm r (ImmInteger n)
235 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
236 | otherwise -> Nothing
237 where n2 = n + toInteger off
243 #if alpha_TARGET_ARCH
245 fits8Bits :: Integer -> Bool
246 fits8Bits i = i >= -256 && i < 256
250 #if sparc_TARGET_ARCH
252 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
253 fits13Bits :: Integral a => a -> Bool
254 fits13Bits x = x >= -4096 && x < 4096
258 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
259 ++show i++");\nprobably because of large constant data structures;" ++
260 "\nworkaround: use -fvia-C on this module.\n")
264 #if powerpc_TARGET_ARCH
265 fits16Bits :: Integral a => a -> Bool
266 fits16Bits x = x >= -32768 && x < 32768
268 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
270 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
272 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
273 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
274 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
275 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
276 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
277 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
279 narrowed = narrow rep signed
282 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
283 | otherwise = Nothing
285 | narrowed >= 0 && narrowed < 65536 = Just narrowed
286 | otherwise = Nothing
287 toI16 _ _ = Just narrowed
291 -- @spRel@ gives us a stack relative addressing mode for volatile
292 -- temporaries and for excess call arguments. @fpRel@, where
293 -- applicable, is the same but for the frame pointer.
295 spRel :: Int -- desired stack offset in words, positive or negative
299 #if defined(i386_TARGET_ARCH)
300 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
301 #elif defined(x86_64_TARGET_ARCH)
302 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
304 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
307 #if sparc_TARGET_ARCH
308 fpRel :: Int -> AddrMode
309 -- Duznae work for offsets greater than 13 bits; we just hope for
312 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
315 #if x86_64_TARGET_ARCH
316 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
319 -- -----------------------------------------------------------------------------
322 -- We map STG registers onto appropriate CmmExprs. Either they map
323 -- to real machine registers or stored as offsets from BaseReg. Given
324 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
325 -- register it is in, on this platform, or a CmmExpr denoting the
326 -- address in the register table holding it.
327 -- (See also get_GlobalReg_addr in CgUtils.)
329 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
330 get_GlobalReg_reg_or_addr mid
331 = case globalRegMaybe mid of
333 Nothing -> Right (get_GlobalReg_addr mid)
335 -- ---------------------------------------------------------------------------
338 -- RealRegs are machine regs which are available for allocation, in
339 -- the usual way. We know what class they are, because that's part of
340 -- the processor's architecture.
342 -- VirtualRegs are virtual registers. The register allocator will
343 -- eventually have to map them into RealRegs, or into spill slots.
344 -- VirtualRegs are allocated on the fly, usually to represent a single
345 -- value in the abstract assembly code (i.e. dynamic registers are
346 -- usually single assignment). With the new register allocator, the
347 -- single assignment restriction isn't necessary to get correct code,
348 -- although a better register allocation will result if single
349 -- assignment is used -- because the allocator maps a VirtualReg into
350 -- a single RealReg, even if the VirtualReg has multiple live ranges.
352 -- Virtual regs can be of either class, so that info is attached.
354 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
355 -- when supplied with the vreg for the lower-half of the quantity.
356 -- (NB. Not reversible).
357 getHiVRegFromLo (VirtualRegI u)
358 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
359 getHiVRegFromLo other
360 = pprPanic "getHiVRegFromLo" (ppr other)
368 instance Uniquable RegClass where
369 getUnique RcInteger = mkUnique 'L' 0
370 getUnique RcFloat = mkUnique 'L' 1
371 getUnique RcDouble = mkUnique 'L' 2
376 = RealReg {-# UNPACK #-} !RegNo
377 | VirtualRegI {-# UNPACK #-} !Unique
378 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
379 | VirtualRegF {-# UNPACK #-} !Unique
380 | VirtualRegD {-# UNPACK #-} !Unique
383 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
384 -- in the register allocator.
385 instance Uniquable Reg where
386 getUnique (RealReg i) = mkUnique 'C' i
387 getUnique (VirtualRegI u) = u
388 getUnique (VirtualRegHi u) = u
389 getUnique (VirtualRegF u) = u
390 getUnique (VirtualRegD u) = u
392 unRealReg (RealReg i) = i
393 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
395 mkVReg :: Unique -> MachRep -> Reg
398 #if sparc_TARGET_ARCH
404 other -> VirtualRegI u
406 isVirtualReg :: Reg -> Bool
407 isVirtualReg (RealReg _) = False
408 isVirtualReg (VirtualRegI _) = True
409 isVirtualReg (VirtualRegHi _) = True
410 isVirtualReg (VirtualRegF _) = True
411 isVirtualReg (VirtualRegD _) = True
413 isRealReg :: Reg -> Bool
414 isRealReg = not . isVirtualReg
416 renameVirtualReg :: Unique -> Reg -> Reg
419 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
420 VirtualRegI _ -> VirtualRegI u
421 VirtualRegHi _ -> VirtualRegHi u
422 VirtualRegF _ -> VirtualRegF u
423 VirtualRegD _ -> VirtualRegD u
425 instance Show Reg where
426 show (RealReg i) = showReg i
427 show (VirtualRegI u) = "%vI_" ++ show u
428 show (VirtualRegHi u) = "%vHi_" ++ show u
429 show (VirtualRegF u) = "%vF_" ++ show u
430 show (VirtualRegD u) = "%vD_" ++ show u
432 instance Outputable RegClass where
433 ppr RcInteger = Outputable.text "I"
434 ppr RcFloat = Outputable.text "F"
435 ppr RcDouble = Outputable.text "D"
437 instance Outputable Reg where
438 ppr r = Outputable.text (show r)
443 -- trivColorable function for the graph coloring allocator
444 -- This gets hammered by scanGraph during register allocation,
445 -- so needs to be fairly efficient.
447 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
448 -- (which are disjoint) ie. x86, x86_64 and ppc
452 -- Doing a nice fold over the UniqSet makes trivColorable use
453 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
455 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
456 trivColorable classN conflicts exclusions
459 acc :: Reg -> (Int, Int) -> (Int, Int)
462 RcInteger -> (cd+1, cf)
463 RcDouble -> (cd, cf+1)
464 _ -> panic "MachRegs.trivColorable: reg class not handled"
466 tmp = foldUniqSet acc (0, 0) conflicts
467 (countInt, countFloat) = foldUniqSet acc tmp exclusions
469 squeese = worst countInt classN RcInteger
470 + worst countFloat classN RcDouble
472 in squeese < allocatableRegsInClass classN
474 -- | Worst case displacement
475 -- node N of classN has n neighbors of class C.
477 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
478 -- This is a bit boring compared to what's in RegArchX86.
480 worst :: Int -> RegClass -> RegClass -> Int
481 worst n classN classC
485 RcInteger -> min n (allocatableRegsInClass RcInteger)
490 RcDouble -> min n (allocatableRegsInClass RcDouble)
495 -- The number of allocatable regs is hard coded here so we can do a fast comparision
496 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
497 -- free regs, but they can't be more or the register conflict graph won't color.
499 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
500 -- is too slow for us here.
502 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
505 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
506 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
509 #if x86_64_TARGET_ARCH
510 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
511 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
514 #if powerpc_TARGET_ARCH
515 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
516 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
519 {-# INLINE regClass #-}
520 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
521 trivColorable classN conflicts exclusions
522 = {-# SCC "trivColorable" #-}
524 {-# INLINE isSqueesed #-}
527 NodeUFM _ _ left right
528 -> case isSqueesed cI cF right of
531 False -> isSqueesed cI' cF' left
532 True -> (# True, cI', cF' #)
535 -> case regClass reg of
537 -> case cI +# _ILIT(1) of
538 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
541 -> case cF +# _ILIT(1) of
542 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
545 -> (# False, cI, cF #)
547 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
548 (# False, cI', cF' #)
549 -> case isSqueesed cI' cF' exclusions of
550 (# s, _, _ #) -> not s
557 -- -----------------------------------------------------------------------------
558 -- Machine-specific register stuff
560 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
561 -- point registers. The mapping of STG registers to alpha machine registers
562 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
564 #if alpha_TARGET_ARCH
568 v0, f0, ra, pv, gp, sp, zeroh :: Reg
570 f0 = realReg (fReg 0)
571 ra = FixedReg ILIT(26)
573 gp = FixedReg ILIT(29)
574 sp = FixedReg ILIT(30)
575 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
577 t9, t10, t11, t12 :: Reg
585 Intel x86 architecture:
586 - All registers except 7 (esp) are available for use.
587 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
588 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
589 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
590 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
591 fp registers, and 3-operand insns for them, and we translate this into
592 real stack-based x86 fp code after register allocation.
594 The fp registers are all Double registers; we don't have any RcFloat class
595 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
601 fake0, fake1, fake2, fake3, fake4, fake5,
602 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
619 -- On x86, we might want to have an 8-bit RegClass, which would
620 -- contain just regs 1-4 (the others don't have 8-bit versions).
621 -- However, we can get away without this at the moment because the
622 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
623 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
624 regClass (VirtualRegI u) = RcInteger
625 regClass (VirtualRegHi u) = RcInteger
626 regClass (VirtualRegD u) = RcDouble
627 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
628 (ppr (VirtualRegF u))
631 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
632 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
634 showReg :: RegNo -> String
636 = if n >= 0 && n < 14
638 else "%unknown_x86_real_reg_" ++ show n
644 AMD x86_64 architecture:
645 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
646 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
647 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
651 #if x86_64_TARGET_ARCH
653 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
654 r8, r9, r10, r11, r12, r13, r14, r15,
655 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
656 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
691 -- so we can re-use some x86 code:
701 xmm n = RealReg (16+n)
703 -- On x86, we might want to have an 8-bit RegClass, which would
704 -- contain just regs 1-4 (the others don't have 8-bit versions).
705 -- However, we can get away without this at the moment because the
706 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
707 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
708 regClass (VirtualRegI u) = RcInteger
709 regClass (VirtualRegHi u) = RcInteger
710 regClass (VirtualRegD u) = RcDouble
711 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
712 (ppr (VirtualRegF u))
715 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
717 showReg :: RegNo -> String
719 | n >= 16 = "%xmm" ++ show (n-16)
720 | n >= 8 = "%r" ++ show n
721 | otherwise = regNames !! n
726 The SPARC has 64 registers of interest; 32 integer registers and 32
727 floating point registers. The mapping of STG registers to SPARC
728 machine registers is defined in StgRegs.h. We are, of course,
729 prepared for any eventuality.
731 The whole fp-register pairing thing on sparcs is a huge nuisance. See
732 fptools/ghc/includes/MachRegs.h for a description of what's going on
736 #if sparc_TARGET_ARCH
738 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
745 nCG_FirstFloatReg :: RegNo
746 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
748 regClass (VirtualRegI u) = RcInteger
749 regClass (VirtualRegF u) = RcFloat
750 regClass (VirtualRegD u) = RcDouble
751 regClass (RealReg i) | i < 32 = RcInteger
752 | i < nCG_FirstFloatReg = RcDouble
753 | otherwise = RcFloat
755 showReg :: RegNo -> String
757 | n >= 0 && n < 8 = "%g" ++ show n
758 | n >= 8 && n < 16 = "%o" ++ show (n-8)
759 | n >= 16 && n < 24 = "%l" ++ show (n-16)
760 | n >= 24 && n < 32 = "%i" ++ show (n-24)
761 | n >= 32 && n < 64 = "%f" ++ show (n-32)
762 | otherwise = "%unknown_sparc_real_reg_" ++ show n
764 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
766 f6 = RealReg (fReg 6)
767 f8 = RealReg (fReg 8)
768 f22 = RealReg (fReg 22)
769 f26 = RealReg (fReg 26)
770 f27 = RealReg (fReg 27)
773 -- g0 is useful for codegen; is always zero, and writes to it vanish.
774 g0 = RealReg (gReg 0)
775 g1 = RealReg (gReg 1)
776 g2 = RealReg (gReg 2)
778 -- FP, SP, int and float return (from C) regs.
779 fp = RealReg (iReg 6)
780 sp = RealReg (oReg 6)
781 o0 = RealReg (oReg 0)
782 o1 = RealReg (oReg 1)
783 f0 = RealReg (fReg 0)
784 f1 = RealReg (fReg 1)
789 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
793 #if powerpc_TARGET_ARCH
797 regClass (VirtualRegI u) = RcInteger
798 regClass (VirtualRegHi u) = RcInteger
799 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
800 (ppr (VirtualRegF u))
801 regClass (VirtualRegD u) = RcDouble
802 regClass (RealReg i) | i < 32 = RcInteger
803 | otherwise = RcDouble
805 showReg :: RegNo -> String
807 | n >= 0 && n <= 31 = "%r" ++ show n
808 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
809 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
816 f1 = RealReg $ fReg 1
817 f20 = RealReg $ fReg 20
818 f21 = RealReg $ fReg 21
822 Redefine the literals used for machine-registers with non-numeric
823 names in the header files. Gag me with a spoon, eh?
826 #if alpha_TARGET_ARCH
877 #if x86_64_TARGET_ARCH
912 #if sparc_TARGET_ARCH
980 #if powerpc_TARGET_ARCH
1014 #ifdef darwin_TARGET_OS
1084 -- allMachRegs is the complete set of machine regs.
1085 allMachRegNos :: [RegNo]
1087 = IF_ARCH_alpha( [0..63],
1088 IF_ARCH_i386( [0..13],
1089 IF_ARCH_x86_64( [0..31],
1090 IF_ARCH_sparc( ([0..31]
1091 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1092 ++ [nCG_FirstFloatReg .. f31]),
1093 IF_ARCH_powerpc([0..63],
1096 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1097 -- i.e., these are the regs for which we are prepared to allow the
1098 -- register allocator to attempt to map VRegs to.
1099 allocatableRegs :: [RegNo]
1101 = let isFree i = isFastTrue (freeReg i)
1102 in filter isFree allMachRegNos
1105 -- | The number of regs in each class.
1106 -- We go via top level CAFs to ensure that we're not recomputing
1107 -- the length of these lists each time the fn is called.
1108 allocatableRegsInClass :: RegClass -> Int
1109 allocatableRegsInClass cls
1111 RcInteger -> allocatableRegsInteger
1112 RcDouble -> allocatableRegsDouble
1114 allocatableRegsInteger
1115 = length $ filter (\r -> regClass r == RcInteger)
1116 $ map RealReg allocatableRegs
1118 allocatableRegsDouble
1119 = length $ filter (\r -> regClass r == RcDouble)
1120 $ map RealReg allocatableRegs
1123 -- these are the regs which we cannot assume stay alive over a
1125 callClobberedRegs :: [Reg]
1128 #if alpha_TARGET_ARCH
1129 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1130 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1131 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1132 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1133 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1134 #endif /* alpha_TARGET_ARCH */
1135 #if i386_TARGET_ARCH
1136 -- caller-saves registers
1137 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1138 #endif /* i386_TARGET_ARCH */
1139 #if x86_64_TARGET_ARCH
1140 -- caller-saves registers
1141 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1142 -- all xmm regs are caller-saves
1143 #endif /* x86_64_TARGET_ARCH */
1144 #if sparc_TARGET_ARCH
1147 [oReg i | i <- [0..5]] ++
1148 [gReg i | i <- [1..7]] ++
1149 [fReg i | i <- [0..31]] )
1150 #endif /* sparc_TARGET_ARCH */
1151 #if powerpc_TARGET_ARCH
1152 #if darwin_TARGET_OS
1153 map RealReg (0:[2..12] ++ map fReg [0..13])
1154 #elif linux_TARGET_OS
1155 map RealReg (0:[2..13] ++ map fReg [0..13])
1157 #endif /* powerpc_TARGET_ARCH */
1160 -- argRegs is the set of regs which are read for an n-argument call to C.
1161 -- For archs which pass all args on the stack (x86), is empty.
1162 -- Sparc passes up to the first 6 args in regs.
1163 -- Dunno about Alpha.
1164 argRegs :: RegNo -> [Reg]
1166 #if i386_TARGET_ARCH
1167 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1170 #if x86_64_TARGET_ARCH
1171 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1174 #if alpha_TARGET_ARCH
1176 argRegs 1 = freeMappedRegs [16, fReg 16]
1177 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1178 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1179 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1180 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1181 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1182 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1183 #endif /* alpha_TARGET_ARCH */
1185 #if sparc_TARGET_ARCH
1187 argRegs 1 = map (RealReg . oReg) [0]
1188 argRegs 2 = map (RealReg . oReg) [0,1]
1189 argRegs 3 = map (RealReg . oReg) [0,1,2]
1190 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1191 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1192 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1193 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1194 #endif /* sparc_TARGET_ARCH */
1196 #if powerpc_TARGET_ARCH
1198 argRegs 1 = map RealReg [3]
1199 argRegs 2 = map RealReg [3,4]
1200 argRegs 3 = map RealReg [3..5]
1201 argRegs 4 = map RealReg [3..6]
1202 argRegs 5 = map RealReg [3..7]
1203 argRegs 6 = map RealReg [3..8]
1204 argRegs 7 = map RealReg [3..9]
1205 argRegs 8 = map RealReg [3..10]
1206 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1207 #endif /* powerpc_TARGET_ARCH */
1210 -- all of the arg regs ??
1211 #if alpha_TARGET_ARCH
1212 allArgRegs :: [(Reg, Reg)]
1213 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1214 #endif /* alpha_TARGET_ARCH */
1216 #if sparc_TARGET_ARCH
1218 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1219 #endif /* sparc_TARGET_ARCH */
1221 #if i386_TARGET_ARCH
1223 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1226 #if x86_64_TARGET_ARCH
1228 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1229 allFPArgRegs :: [Reg]
1230 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1233 #if powerpc_TARGET_ARCH
1235 allArgRegs = map RealReg [3..10]
1236 allFPArgRegs :: [Reg]
1237 #if darwin_TARGET_OS
1238 allFPArgRegs = map (RealReg . fReg) [1..13]
1239 #elif linux_TARGET_OS
1240 allFPArgRegs = map (RealReg . fReg) [1..8]
1242 #endif /* powerpc_TARGET_ARCH */
1246 freeReg :: RegNo -> FastBool
1248 #if alpha_TARGET_ARCH
1249 freeReg 26 = fastBool False -- return address (ra)
1250 freeReg 28 = fastBool False -- reserved for the assembler (at)
1251 freeReg 29 = fastBool False -- global pointer (gp)
1252 freeReg 30 = fastBool False -- stack pointer (sp)
1253 freeReg 31 = fastBool False -- always zero (zeroh)
1254 freeReg 63 = fastBool False -- always zero (f31)
1257 #if i386_TARGET_ARCH
1258 freeReg esp = fastBool False -- %esp is the C stack pointer
1261 #if x86_64_TARGET_ARCH
1262 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1265 #if sparc_TARGET_ARCH
1266 freeReg g0 = fastBool False -- %g0 is always 0.
1267 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1268 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1269 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1270 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1271 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1272 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1273 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1274 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1275 freeReg f1 = fastBool False
1278 #if powerpc_TARGET_ARCH
1279 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1280 freeReg 1 = fastBool False -- The Stack Pointer
1281 #if !darwin_TARGET_OS
1282 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1283 freeReg 2 = fastBool False
1288 freeReg REG_Base = fastBool False
1291 freeReg REG_R1 = fastBool False
1294 freeReg REG_R2 = fastBool False
1297 freeReg REG_R3 = fastBool False
1300 freeReg REG_R4 = fastBool False
1303 freeReg REG_R5 = fastBool False
1306 freeReg REG_R6 = fastBool False
1309 freeReg REG_R7 = fastBool False
1312 freeReg REG_R8 = fastBool False
1315 freeReg REG_F1 = fastBool False
1318 freeReg REG_F2 = fastBool False
1321 freeReg REG_F3 = fastBool False
1324 freeReg REG_F4 = fastBool False
1327 freeReg REG_D1 = fastBool False
1330 freeReg REG_D2 = fastBool False
1333 freeReg REG_Sp = fastBool False
1336 freeReg REG_Su = fastBool False
1339 freeReg REG_SpLim = fastBool False
1342 freeReg REG_Hp = fastBool False
1345 freeReg REG_HpLim = fastBool False
1347 freeReg n = fastBool True
1350 -- | Returns 'Nothing' if this global register is not stored
1351 -- in a real machine register, otherwise returns @'Just' reg@, where
1352 -- reg is the machine register it is stored in.
1354 globalRegMaybe :: GlobalReg -> Maybe Reg
1357 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1360 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1363 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1366 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1369 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1372 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1375 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1378 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1381 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1384 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1387 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1390 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1393 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1396 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1399 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1402 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1405 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1408 globalRegMaybe Sp = Just (RealReg REG_Sp)
1411 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1414 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1417 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1420 globalRegMaybe Hp = Just (RealReg REG_Hp)
1423 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1425 #ifdef REG_CurrentTSO
1426 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1428 #ifdef REG_CurrentNursery
1429 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1431 globalRegMaybe _ = Nothing