1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
30 RegClass(..), regClass,
36 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 EABase(..), EAIndex(..),
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 EABase(..), EAIndex(..), ripRel,
56 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 r8, r9, r10, r11, r12, r13, r14, r15,
59 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
60 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
62 addrModeRegs, allFPArgRegs,
66 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
67 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
69 #if powerpc_TARGET_ARCH
78 #include "HsVersions.h"
81 # define STOLEN_X86_REGS 4
82 -- HACK: go for the max
88 import MachOp ( MachRep(..) )
89 import CgUtils ( get_GlobalReg_addr )
91 import CLabel ( CLabel, mkMainCapabilityLabel )
93 import Outputable ( Outputable(..), pprPanic, panic )
94 import qualified Outputable
100 #if powerpc_TARGET_ARCH
101 import Data.Word ( Word8, Word16, Word32 )
102 import Data.Int ( Int8, Int16, Int32 )
105 -- -----------------------------------------------------------------------------
110 | ImmInteger Integer -- Sigh.
111 | ImmCLbl CLabel -- AbstractC Label (with baggage)
112 | ImmLit Doc -- Simple string
113 | ImmIndex CLabel Int
116 | ImmConstantSum Imm Imm
117 | ImmConstantDiff Imm Imm
118 #if sparc_TARGET_ARCH
119 | LO Imm {- Possible restrictions... -}
122 #if powerpc_TARGET_ARCH
125 | HA Imm {- high halfword adjusted -}
127 strImmLit s = ImmLit (text s)
129 litToImm :: CmmLit -> Imm
130 litToImm (CmmInt i _) = ImmInteger i
131 litToImm (CmmFloat f F32) = ImmFloat f
132 litToImm (CmmFloat f F64) = ImmDouble f
133 litToImm (CmmLabel l) = ImmCLbl l
134 litToImm (CmmLabelOff l off) = ImmIndex l off
135 litToImm (CmmLabelDiffOff l1 l2 off)
137 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
140 -- -----------------------------------------------------------------------------
144 #if alpha_TARGET_ARCH
150 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
151 = AddrBaseIndex EABase EAIndex Displacement
154 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
155 data EAIndex = EAIndexNone | EAIndex Reg Int
156 type Displacement = Imm
159 #if sparc_TARGET_ARCH
164 #if powerpc_TARGET_ARCH
169 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
170 addrModeRegs :: AddrMode -> [Reg]
171 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
173 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
174 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
179 addrOffset :: AddrMode -> Int -> Maybe AddrMode
183 #if alpha_TARGET_ARCH
184 _ -> panic "MachMisc.addrOffset not defined for Alpha"
186 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
187 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
189 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
190 AddrBaseIndex r i (ImmInteger n)
191 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
193 AddrBaseIndex r i (ImmCLbl lbl)
194 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
196 AddrBaseIndex r i (ImmIndex lbl ix)
197 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
199 _ -> Nothing -- in theory, shouldn't happen
201 #if sparc_TARGET_ARCH
202 AddrRegImm r (ImmInt n)
203 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
204 | otherwise -> Nothing
207 AddrRegImm r (ImmInteger n)
208 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
209 | otherwise -> Nothing
210 where n2 = n + toInteger off
212 AddrRegReg r (RealReg 0)
213 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
214 | otherwise -> Nothing
218 #if powerpc_TARGET_ARCH
219 AddrRegImm r (ImmInt n)
220 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
221 | otherwise -> Nothing
224 AddrRegImm r (ImmInteger n)
225 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
226 | otherwise -> Nothing
227 where n2 = n + toInteger off
233 #if alpha_TARGET_ARCH
235 fits8Bits :: Integer -> Bool
236 fits8Bits i = i >= -256 && i < 256
240 #if sparc_TARGET_ARCH
242 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
243 fits13Bits :: Integral a => a -> Bool
244 fits13Bits x = x >= -4096 && x < 4096
248 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
249 ++show i++");\nprobably because of large constant data structures;" ++
250 "\nworkaround: use -fvia-C on this module.\n")
254 #if powerpc_TARGET_ARCH
255 fits16Bits :: Integral a => a -> Bool
256 fits16Bits x = x >= -32768 && x < 32768
258 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
260 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
262 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
263 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
264 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
265 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
266 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
267 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
269 narrowed = narrow rep signed
272 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
273 | otherwise = Nothing
275 | narrowed >= 0 && narrowed < 65536 = Just narrowed
276 | otherwise = Nothing
277 toI16 _ _ = Just narrowed
281 -- @spRel@ gives us a stack relative addressing mode for volatile
282 -- temporaries and for excess call arguments. @fpRel@, where
283 -- applicable, is the same but for the frame pointer.
285 spRel :: Int -- desired stack offset in words, positive or negative
289 #if defined(i386_TARGET_ARCH)
290 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
291 #elif defined(x86_64_TARGET_ARCH)
292 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
294 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
297 #if sparc_TARGET_ARCH
298 fpRel :: Int -> AddrMode
299 -- Duznae work for offsets greater than 13 bits; we just hope for
302 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
305 #if x86_64_TARGET_ARCH
306 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
309 -- -----------------------------------------------------------------------------
312 -- We map STG registers onto appropriate CmmExprs. Either they map
313 -- to real machine registers or stored as offsets from BaseReg. Given
314 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
315 -- register it is in, on this platform, or a CmmExpr denoting the
316 -- address in the register table holding it.
317 -- (See also get_GlobalReg_addr in CgUtils.)
319 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
320 get_GlobalReg_reg_or_addr mid
321 = case globalRegMaybe mid of
323 Nothing -> Right (get_GlobalReg_addr mid)
325 -- ---------------------------------------------------------------------------
328 -- RealRegs are machine regs which are available for allocation, in
329 -- the usual way. We know what class they are, because that's part of
330 -- the processor's architecture.
332 -- VirtualRegs are virtual registers. The register allocator will
333 -- eventually have to map them into RealRegs, or into spill slots.
334 -- VirtualRegs are allocated on the fly, usually to represent a single
335 -- value in the abstract assembly code (i.e. dynamic registers are
336 -- usually single assignment). With the new register allocator, the
337 -- single assignment restriction isn't necessary to get correct code,
338 -- although a better register allocation will result if single
339 -- assignment is used -- because the allocator maps a VirtualReg into
340 -- a single RealReg, even if the VirtualReg has multiple live ranges.
342 -- Virtual regs can be of either class, so that info is attached.
344 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
345 -- when supplied with the vreg for the lower-half of the quantity.
346 -- (NB. Not reversible).
347 getHiVRegFromLo (VirtualRegI u)
348 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
349 getHiVRegFromLo other
350 = pprPanic "getHiVRegFromLo" (ppr other)
358 instance Uniquable RegClass where
359 getUnique RcInteger = mkUnique 'L' 0
360 getUnique RcFloat = mkUnique 'L' 1
361 getUnique RcDouble = mkUnique 'L' 2
366 = RealReg {-# UNPACK #-} !RegNo
367 | VirtualRegI {-# UNPACK #-} !Unique
368 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
369 | VirtualRegF {-# UNPACK #-} !Unique
370 | VirtualRegD {-# UNPACK #-} !Unique
373 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
374 -- in the register allocator.
375 instance Uniquable Reg where
376 getUnique (RealReg i) = mkUnique 'C' i
377 getUnique (VirtualRegI u) = u
378 getUnique (VirtualRegHi u) = u
379 getUnique (VirtualRegF u) = u
380 getUnique (VirtualRegD u) = u
382 unRealReg (RealReg i) = i
383 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
385 mkVReg :: Unique -> MachRep -> Reg
388 #if sparc_TARGET_ARCH
394 other -> VirtualRegI u
396 isVirtualReg :: Reg -> Bool
397 isVirtualReg (RealReg _) = False
398 isVirtualReg (VirtualRegI _) = True
399 isVirtualReg (VirtualRegHi _) = True
400 isVirtualReg (VirtualRegF _) = True
401 isVirtualReg (VirtualRegD _) = True
403 isRealReg :: Reg -> Bool
404 isRealReg = not . isVirtualReg
406 renameVirtualReg :: Unique -> Reg -> Reg
409 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
410 VirtualRegI _ -> VirtualRegI u
411 VirtualRegHi _ -> VirtualRegHi u
412 VirtualRegF _ -> VirtualRegF u
413 VirtualRegD _ -> VirtualRegD u
415 instance Show Reg where
416 show (RealReg i) = showReg i
417 show (VirtualRegI u) = "%vI_" ++ show u
418 show (VirtualRegHi u) = "%vHi_" ++ show u
419 show (VirtualRegF u) = "%vF_" ++ show u
420 show (VirtualRegD u) = "%vD_" ++ show u
422 instance Outputable RegClass where
423 ppr RcInteger = Outputable.text "I"
424 ppr RcFloat = Outputable.text "F"
425 ppr RcDouble = Outputable.text "D"
427 instance Outputable Reg where
428 ppr r = Outputable.text (show r)
433 -- trivColorable function for the graph coloring allocator
434 -- This gets hammered by scanGraph during register allocation,
435 -- so needs to be fairly efficient.
437 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
438 -- (which are disjoint) ie. x86, x86_64 and ppc
440 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
441 trivColorable classN conflicts exclusions
445 RcInteger -> (cd+1, cf)
446 RcDouble -> (cd, cf+1)
447 _ -> panic "MachRegs.trivColorable: reg class not handled"
449 tmp = foldUniqSet acc (0, 0) conflicts
450 (rsD, rsFP) = foldUniqSet acc tmp exclusions
452 squeese = worst rsD classN RcInteger
453 + worst rsFP classN RcDouble
455 in squeese < allocatableRegsInClass classN
458 -- | Worst case displacement
459 -- node N of classN has n neighbors of class C.
461 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
462 -- This is a bit boring compared to what's in RegArchX86.
464 worst :: Int -> RegClass -> RegClass -> Int
465 worst n classN classC
469 RcInteger -> min n (allocatableRegsInClass RcInteger)
474 RcDouble -> min n (allocatableRegsInClass RcDouble)
478 -- -----------------------------------------------------------------------------
479 -- Machine-specific register stuff
481 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
482 -- point registers. The mapping of STG registers to alpha machine registers
483 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
485 #if alpha_TARGET_ARCH
489 v0, f0, ra, pv, gp, sp, zeroh :: Reg
491 f0 = realReg (fReg 0)
492 ra = FixedReg ILIT(26)
494 gp = FixedReg ILIT(29)
495 sp = FixedReg ILIT(30)
496 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
498 t9, t10, t11, t12 :: Reg
506 Intel x86 architecture:
507 - All registers except 7 (esp) are available for use.
508 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
509 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
510 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
511 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
512 fp registers, and 3-operand insns for them, and we translate this into
513 real stack-based x86 fp code after register allocation.
515 The fp registers are all Double registers; we don't have any RcFloat class
516 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
522 fake0, fake1, fake2, fake3, fake4, fake5,
523 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
540 -- On x86, we might want to have an 8-bit RegClass, which would
541 -- contain just regs 1-4 (the others don't have 8-bit versions).
542 -- However, we can get away without this at the moment because the
543 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
544 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
545 regClass (VirtualRegI u) = RcInteger
546 regClass (VirtualRegHi u) = RcInteger
547 regClass (VirtualRegD u) = RcDouble
548 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
549 (ppr (VirtualRegF u))
552 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
553 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
555 showReg :: RegNo -> String
557 = if n >= 0 && n < 14
559 else "%unknown_x86_real_reg_" ++ show n
565 AMD x86_64 architecture:
566 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
567 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
568 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
572 #if x86_64_TARGET_ARCH
574 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
575 r8, r9, r10, r11, r12, r13, r14, r15,
576 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
577 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
612 -- so we can re-use some x86 code:
622 xmm n = RealReg (16+n)
624 -- On x86, we might want to have an 8-bit RegClass, which would
625 -- contain just regs 1-4 (the others don't have 8-bit versions).
626 -- However, we can get away without this at the moment because the
627 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
628 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
629 regClass (VirtualRegI u) = RcInteger
630 regClass (VirtualRegHi u) = RcInteger
631 regClass (VirtualRegD u) = RcDouble
632 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
633 (ppr (VirtualRegF u))
636 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
638 showReg :: RegNo -> String
640 | n >= 16 = "%xmm" ++ show (n-16)
641 | n >= 8 = "%r" ++ show n
642 | otherwise = regNames !! n
647 The SPARC has 64 registers of interest; 32 integer registers and 32
648 floating point registers. The mapping of STG registers to SPARC
649 machine registers is defined in StgRegs.h. We are, of course,
650 prepared for any eventuality.
652 The whole fp-register pairing thing on sparcs is a huge nuisance. See
653 fptools/ghc/includes/MachRegs.h for a description of what's going on
657 #if sparc_TARGET_ARCH
659 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
666 nCG_FirstFloatReg :: RegNo
667 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
669 regClass (VirtualRegI u) = RcInteger
670 regClass (VirtualRegF u) = RcFloat
671 regClass (VirtualRegD u) = RcDouble
672 regClass (RealReg i) | i < 32 = RcInteger
673 | i < nCG_FirstFloatReg = RcDouble
674 | otherwise = RcFloat
676 showReg :: RegNo -> String
678 | n >= 0 && n < 8 = "%g" ++ show n
679 | n >= 8 && n < 16 = "%o" ++ show (n-8)
680 | n >= 16 && n < 24 = "%l" ++ show (n-16)
681 | n >= 24 && n < 32 = "%i" ++ show (n-24)
682 | n >= 32 && n < 64 = "%f" ++ show (n-32)
683 | otherwise = "%unknown_sparc_real_reg_" ++ show n
685 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
687 f6 = RealReg (fReg 6)
688 f8 = RealReg (fReg 8)
689 f22 = RealReg (fReg 22)
690 f26 = RealReg (fReg 26)
691 f27 = RealReg (fReg 27)
694 -- g0 is useful for codegen; is always zero, and writes to it vanish.
695 g0 = RealReg (gReg 0)
696 g1 = RealReg (gReg 1)
697 g2 = RealReg (gReg 2)
699 -- FP, SP, int and float return (from C) regs.
700 fp = RealReg (iReg 6)
701 sp = RealReg (oReg 6)
702 o0 = RealReg (oReg 0)
703 o1 = RealReg (oReg 1)
704 f0 = RealReg (fReg 0)
705 f1 = RealReg (fReg 1)
710 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
714 #if powerpc_TARGET_ARCH
718 regClass (VirtualRegI u) = RcInteger
719 regClass (VirtualRegHi u) = RcInteger
720 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
721 (ppr (VirtualRegF u))
722 regClass (VirtualRegD u) = RcDouble
723 regClass (RealReg i) | i < 32 = RcInteger
724 | otherwise = RcDouble
726 showReg :: RegNo -> String
728 | n >= 0 && n <= 31 = "%r" ++ show n
729 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
730 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
737 f1 = RealReg $ fReg 1
738 f20 = RealReg $ fReg 20
739 f21 = RealReg $ fReg 21
743 Redefine the literals used for machine-registers with non-numeric
744 names in the header files. Gag me with a spoon, eh?
747 #if alpha_TARGET_ARCH
798 #if x86_64_TARGET_ARCH
833 #if sparc_TARGET_ARCH
901 #if powerpc_TARGET_ARCH
935 #ifdef darwin_TARGET_OS
1005 -- allMachRegs is the complete set of machine regs.
1006 allMachRegNos :: [RegNo]
1008 = IF_ARCH_alpha( [0..63],
1009 IF_ARCH_i386( [0..13],
1010 IF_ARCH_x86_64( [0..31],
1011 IF_ARCH_sparc( ([0..31]
1012 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1013 ++ [nCG_FirstFloatReg .. f31]),
1014 IF_ARCH_powerpc([0..63],
1017 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1018 -- i.e., these are the regs for which we are prepared to allow the
1019 -- register allocator to attempt to map VRegs to.
1020 allocatableRegs :: [RegNo]
1022 = let isFree i = isFastTrue (freeReg i)
1023 in filter isFree allMachRegNos
1026 -- | The number of regs in each class.
1027 -- We go via top level CAFs to ensure that we're not recomputing
1028 -- the length of these lists each time the fn is called.
1029 allocatableRegsInClass :: RegClass -> Int
1030 allocatableRegsInClass cls
1032 RcInteger -> allocatableRegsInteger
1033 RcDouble -> allocatableRegsDouble
1035 allocatableRegsInteger
1036 = length $ filter (\r -> regClass r == RcInteger)
1037 $ map RealReg allocatableRegs
1039 allocatableRegsDouble
1040 = length $ filter (\r -> regClass r == RcDouble)
1041 $ map RealReg allocatableRegs
1044 -- these are the regs which we cannot assume stay alive over a
1046 callClobberedRegs :: [Reg]
1049 #if alpha_TARGET_ARCH
1050 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1051 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1052 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1053 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1054 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1055 #endif /* alpha_TARGET_ARCH */
1056 #if i386_TARGET_ARCH
1057 -- caller-saves registers
1058 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1059 #endif /* i386_TARGET_ARCH */
1060 #if x86_64_TARGET_ARCH
1061 -- caller-saves registers
1062 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1063 -- all xmm regs are caller-saves
1064 #endif /* x86_64_TARGET_ARCH */
1065 #if sparc_TARGET_ARCH
1068 [oReg i | i <- [0..5]] ++
1069 [gReg i | i <- [1..7]] ++
1070 [fReg i | i <- [0..31]] )
1071 #endif /* sparc_TARGET_ARCH */
1072 #if powerpc_TARGET_ARCH
1073 #if darwin_TARGET_OS
1074 map RealReg (0:[2..12] ++ map fReg [0..13])
1075 #elif linux_TARGET_OS
1076 map RealReg (0:[2..13] ++ map fReg [0..13])
1078 #endif /* powerpc_TARGET_ARCH */
1081 -- argRegs is the set of regs which are read for an n-argument call to C.
1082 -- For archs which pass all args on the stack (x86), is empty.
1083 -- Sparc passes up to the first 6 args in regs.
1084 -- Dunno about Alpha.
1085 argRegs :: RegNo -> [Reg]
1087 #if i386_TARGET_ARCH
1088 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1091 #if x86_64_TARGET_ARCH
1092 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1095 #if alpha_TARGET_ARCH
1097 argRegs 1 = freeMappedRegs [16, fReg 16]
1098 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1099 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1100 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1101 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1102 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1103 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1104 #endif /* alpha_TARGET_ARCH */
1106 #if sparc_TARGET_ARCH
1108 argRegs 1 = map (RealReg . oReg) [0]
1109 argRegs 2 = map (RealReg . oReg) [0,1]
1110 argRegs 3 = map (RealReg . oReg) [0,1,2]
1111 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1112 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1113 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1114 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1115 #endif /* sparc_TARGET_ARCH */
1117 #if powerpc_TARGET_ARCH
1119 argRegs 1 = map RealReg [3]
1120 argRegs 2 = map RealReg [3,4]
1121 argRegs 3 = map RealReg [3..5]
1122 argRegs 4 = map RealReg [3..6]
1123 argRegs 5 = map RealReg [3..7]
1124 argRegs 6 = map RealReg [3..8]
1125 argRegs 7 = map RealReg [3..9]
1126 argRegs 8 = map RealReg [3..10]
1127 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1128 #endif /* powerpc_TARGET_ARCH */
1131 -- all of the arg regs ??
1132 #if alpha_TARGET_ARCH
1133 allArgRegs :: [(Reg, Reg)]
1134 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1135 #endif /* alpha_TARGET_ARCH */
1137 #if sparc_TARGET_ARCH
1139 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1140 #endif /* sparc_TARGET_ARCH */
1142 #if i386_TARGET_ARCH
1144 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1147 #if x86_64_TARGET_ARCH
1149 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1150 allFPArgRegs :: [Reg]
1151 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1154 #if powerpc_TARGET_ARCH
1156 allArgRegs = map RealReg [3..10]
1157 allFPArgRegs :: [Reg]
1158 #if darwin_TARGET_OS
1159 allFPArgRegs = map (RealReg . fReg) [1..13]
1160 #elif linux_TARGET_OS
1161 allFPArgRegs = map (RealReg . fReg) [1..8]
1163 #endif /* powerpc_TARGET_ARCH */
1167 freeReg :: RegNo -> FastBool
1169 #if alpha_TARGET_ARCH
1170 freeReg 26 = fastBool False -- return address (ra)
1171 freeReg 28 = fastBool False -- reserved for the assembler (at)
1172 freeReg 29 = fastBool False -- global pointer (gp)
1173 freeReg 30 = fastBool False -- stack pointer (sp)
1174 freeReg 31 = fastBool False -- always zero (zeroh)
1175 freeReg 63 = fastBool False -- always zero (f31)
1178 #if i386_TARGET_ARCH
1179 freeReg esp = fastBool False -- %esp is the C stack pointer
1182 #if x86_64_TARGET_ARCH
1183 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1186 #if sparc_TARGET_ARCH
1187 freeReg g0 = fastBool False -- %g0 is always 0.
1188 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1189 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1190 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1191 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1192 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1193 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1194 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1195 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1196 freeReg f1 = fastBool False
1199 #if powerpc_TARGET_ARCH
1200 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1201 freeReg 1 = fastBool False -- The Stack Pointer
1202 #if !darwin_TARGET_OS
1203 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1204 freeReg 2 = fastBool False
1209 freeReg REG_Base = fastBool False
1212 freeReg REG_R1 = fastBool False
1215 freeReg REG_R2 = fastBool False
1218 freeReg REG_R3 = fastBool False
1221 freeReg REG_R4 = fastBool False
1224 freeReg REG_R5 = fastBool False
1227 freeReg REG_R6 = fastBool False
1230 freeReg REG_R7 = fastBool False
1233 freeReg REG_R8 = fastBool False
1236 freeReg REG_F1 = fastBool False
1239 freeReg REG_F2 = fastBool False
1242 freeReg REG_F3 = fastBool False
1245 freeReg REG_F4 = fastBool False
1248 freeReg REG_D1 = fastBool False
1251 freeReg REG_D2 = fastBool False
1254 freeReg REG_Sp = fastBool False
1257 freeReg REG_Su = fastBool False
1260 freeReg REG_SpLim = fastBool False
1263 freeReg REG_Hp = fastBool False
1266 freeReg REG_HpLim = fastBool False
1268 freeReg n = fastBool True
1271 -- | Returns 'Nothing' if this global register is not stored
1272 -- in a real machine register, otherwise returns @'Just' reg@, where
1273 -- reg is the machine register it is stored in.
1275 globalRegMaybe :: GlobalReg -> Maybe Reg
1278 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1281 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1284 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1287 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1290 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1293 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1296 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1299 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1302 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1305 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1308 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1311 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1314 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1317 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1320 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1323 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1326 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1329 globalRegMaybe Sp = Just (RealReg REG_Sp)
1332 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1335 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1338 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1341 globalRegMaybe Hp = Just (RealReg REG_Hp)
1344 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1346 #ifdef REG_CurrentTSO
1347 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1349 #ifdef REG_CurrentNursery
1350 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1352 globalRegMaybe _ = Nothing