1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
37 -- * Machine-dependent register-related stuff
38 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
45 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
48 EABase(..), EAIndex(..),
49 eax, ebx, ecx, edx, esi, edi, ebp, esp,
50 fake0, fake1, fake2, fake3, fake4, fake5,
53 #if x86_64_TARGET_ARCH
54 EABase(..), EAIndex(..), ripRel,
55 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
56 eax, ebx, ecx, edx, esi, edi, ebp, esp,
57 r8, r9, r10, r11, r12, r13, r14, r15,
58 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
59 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
61 addrModeRegs, allFPArgRegs,
65 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
66 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
68 #if powerpc_TARGET_ARCH
77 #include "HsVersions.h"
80 # define STOLEN_X86_REGS 4
81 -- HACK: go for the max
87 import MachOp ( MachRep(..) )
88 import CgUtils ( get_GlobalReg_addr )
90 import CLabel ( CLabel, mkMainCapabilityLabel )
92 import Outputable ( Outputable(..), pprPanic, panic )
93 import qualified Outputable
98 #if powerpc_TARGET_ARCH
99 import Data.Word ( Word8, Word16, Word32 )
100 import Data.Int ( Int8, Int16, Int32 )
103 -- -----------------------------------------------------------------------------
108 | ImmInteger Integer -- Sigh.
109 | ImmCLbl CLabel -- AbstractC Label (with baggage)
110 | ImmLit Doc -- Simple string
111 | ImmIndex CLabel Int
114 | ImmConstantSum Imm Imm
115 | ImmConstantDiff Imm Imm
116 #if sparc_TARGET_ARCH
117 | LO Imm {- Possible restrictions... -}
120 #if powerpc_TARGET_ARCH
123 | HA Imm {- high halfword adjusted -}
125 strImmLit s = ImmLit (text s)
127 litToImm :: CmmLit -> Imm
128 litToImm (CmmInt i _) = ImmInteger i
129 litToImm (CmmFloat f F32) = ImmFloat f
130 litToImm (CmmFloat f F64) = ImmDouble f
131 litToImm (CmmLabel l) = ImmCLbl l
132 litToImm (CmmLabelOff l off) = ImmIndex l off
133 litToImm (CmmLabelDiffOff l1 l2 off)
135 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
138 -- -----------------------------------------------------------------------------
142 #if alpha_TARGET_ARCH
148 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
149 = AddrBaseIndex EABase EAIndex Displacement
152 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
153 data EAIndex = EAIndexNone | EAIndex Reg Int
154 type Displacement = Imm
157 #if sparc_TARGET_ARCH
162 #if powerpc_TARGET_ARCH
167 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
168 addrModeRegs :: AddrMode -> [Reg]
169 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
171 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
172 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
177 addrOffset :: AddrMode -> Int -> Maybe AddrMode
181 #if alpha_TARGET_ARCH
182 _ -> panic "MachMisc.addrOffset not defined for Alpha"
184 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
185 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
187 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
188 AddrBaseIndex r i (ImmInteger n)
189 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
191 AddrBaseIndex r i (ImmCLbl lbl)
192 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
194 AddrBaseIndex r i (ImmIndex lbl ix)
195 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
197 _ -> Nothing -- in theory, shouldn't happen
199 #if sparc_TARGET_ARCH
200 AddrRegImm r (ImmInt n)
201 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
202 | otherwise -> Nothing
205 AddrRegImm r (ImmInteger n)
206 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
207 | otherwise -> Nothing
208 where n2 = n + toInteger off
210 AddrRegReg r (RealReg 0)
211 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
212 | otherwise -> Nothing
216 #if powerpc_TARGET_ARCH
217 AddrRegImm r (ImmInt n)
218 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
219 | otherwise -> Nothing
222 AddrRegImm r (ImmInteger n)
223 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
224 | otherwise -> Nothing
225 where n2 = n + toInteger off
231 #if alpha_TARGET_ARCH
233 fits8Bits :: Integer -> Bool
234 fits8Bits i = i >= -256 && i < 256
238 #if sparc_TARGET_ARCH
240 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
241 fits13Bits :: Integral a => a -> Bool
242 fits13Bits x = x >= -4096 && x < 4096
246 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
247 ++show i++");\nprobably because of large constant data structures;" ++
248 "\nworkaround: use -fvia-C on this module.\n")
252 #if powerpc_TARGET_ARCH
253 fits16Bits :: Integral a => a -> Bool
254 fits16Bits x = x >= -32768 && x < 32768
256 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
258 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
260 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
261 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
262 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
263 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
264 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
265 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
267 narrowed = narrow rep signed
270 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
271 | otherwise = Nothing
273 | narrowed >= 0 && narrowed < 65536 = Just narrowed
274 | otherwise = Nothing
275 toI16 _ _ = Just narrowed
279 -- @spRel@ gives us a stack relative addressing mode for volatile
280 -- temporaries and for excess call arguments. @fpRel@, where
281 -- applicable, is the same but for the frame pointer.
283 spRel :: Int -- desired stack offset in words, positive or negative
287 #if defined(i386_TARGET_ARCH)
288 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
289 #elif defined(x86_64_TARGET_ARCH)
290 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
292 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
295 #if sparc_TARGET_ARCH
296 fpRel :: Int -> AddrMode
297 -- Duznae work for offsets greater than 13 bits; we just hope for
300 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
303 #if x86_64_TARGET_ARCH
304 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
307 -- -----------------------------------------------------------------------------
310 -- We map STG registers onto appropriate CmmExprs. Either they map
311 -- to real machine registers or stored as offsets from BaseReg. Given
312 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
313 -- register it is in, on this platform, or a CmmExpr denoting the
314 -- address in the register table holding it.
315 -- (See also get_GlobalReg_addr in CgUtils.)
317 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
318 get_GlobalReg_reg_or_addr mid
319 = case globalRegMaybe mid of
321 Nothing -> Right (get_GlobalReg_addr mid)
323 -- ---------------------------------------------------------------------------
326 -- RealRegs are machine regs which are available for allocation, in
327 -- the usual way. We know what class they are, because that's part of
328 -- the processor's architecture.
330 -- VirtualRegs are virtual registers. The register allocator will
331 -- eventually have to map them into RealRegs, or into spill slots.
332 -- VirtualRegs are allocated on the fly, usually to represent a single
333 -- value in the abstract assembly code (i.e. dynamic registers are
334 -- usually single assignment). With the new register allocator, the
335 -- single assignment restriction isn't necessary to get correct code,
336 -- although a better register allocation will result if single
337 -- assignment is used -- because the allocator maps a VirtualReg into
338 -- a single RealReg, even if the VirtualReg has multiple live ranges.
340 -- Virtual regs can be of either class, so that info is attached.
342 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
343 -- when supplied with the vreg for the lower-half of the quantity.
344 -- (NB. Not reversible).
345 getHiVRegFromLo (VirtualRegI u)
346 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
347 getHiVRegFromLo other
348 = pprPanic "getHiVRegFromLo" (ppr other)
359 = RealReg {-# UNPACK #-} !RegNo
360 | VirtualRegI {-# UNPACK #-} !Unique
361 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
362 | VirtualRegF {-# UNPACK #-} !Unique
363 | VirtualRegD {-# UNPACK #-} !Unique
366 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
367 -- in the register allocator.
368 instance Uniquable Reg where
369 getUnique (RealReg i) = mkUnique 'C' i
370 getUnique (VirtualRegI u) = u
371 getUnique (VirtualRegHi u) = u
372 getUnique (VirtualRegF u) = u
373 getUnique (VirtualRegD u) = u
375 unRealReg (RealReg i) = i
376 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
378 mkVReg :: Unique -> MachRep -> Reg
381 #if sparc_TARGET_ARCH
387 other -> VirtualRegI u
389 isVirtualReg :: Reg -> Bool
390 isVirtualReg (RealReg _) = False
391 isVirtualReg (VirtualRegI _) = True
392 isVirtualReg (VirtualRegHi _) = True
393 isVirtualReg (VirtualRegF _) = True
394 isVirtualReg (VirtualRegD _) = True
396 isRealReg :: Reg -> Bool
397 isRealReg = not . isVirtualReg
399 instance Show Reg where
400 show (RealReg i) = showReg i
401 show (VirtualRegI u) = "%vI_" ++ show u
402 show (VirtualRegHi u) = "%vHi_" ++ show u
403 show (VirtualRegF u) = "%vF_" ++ show u
404 show (VirtualRegD u) = "%vD_" ++ show u
406 instance Outputable Reg where
407 ppr r = Outputable.text (show r)
410 -- -----------------------------------------------------------------------------
411 -- Machine-specific register stuff
413 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
414 -- point registers. The mapping of STG registers to alpha machine registers
415 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
417 #if alpha_TARGET_ARCH
421 v0, f0, ra, pv, gp, sp, zeroh :: Reg
423 f0 = realReg (fReg 0)
424 ra = FixedReg ILIT(26)
426 gp = FixedReg ILIT(29)
427 sp = FixedReg ILIT(30)
428 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
430 t9, t10, t11, t12 :: Reg
438 Intel x86 architecture:
439 - All registers except 7 (esp) are available for use.
440 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
441 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
442 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
443 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
444 fp registers, and 3-operand insns for them, and we translate this into
445 real stack-based x86 fp code after register allocation.
447 The fp registers are all Double registers; we don't have any RcFloat class
448 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
454 fake0, fake1, fake2, fake3, fake4, fake5,
455 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
471 -- On x86, we might want to have an 8-bit RegClass, which would
472 -- contain just regs 1-4 (the others don't have 8-bit versions).
473 -- However, we can get away without this at the moment because the
474 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
475 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
476 regClass (VirtualRegI u) = RcInteger
477 regClass (VirtualRegHi u) = RcInteger
478 regClass (VirtualRegD u) = RcDouble
479 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
480 (ppr (VirtualRegF u))
483 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
484 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
486 showReg :: RegNo -> String
488 = if n >= 0 && n < 14
490 else "%unknown_x86_real_reg_" ++ show n
495 AMD x86_64 architecture:
496 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
497 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
498 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
502 #if x86_64_TARGET_ARCH
504 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
505 r8, r9, r10, r11, r12, r13, r14, r15,
506 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
507 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
542 -- so we can re-use some x86 code:
552 xmm n = RealReg (16+n)
554 -- On x86, we might want to have an 8-bit RegClass, which would
555 -- contain just regs 1-4 (the others don't have 8-bit versions).
556 -- However, we can get away without this at the moment because the
557 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
558 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
559 regClass (VirtualRegI u) = RcInteger
560 regClass (VirtualRegHi u) = RcInteger
561 regClass (VirtualRegD u) = RcDouble
562 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
563 (ppr (VirtualRegF u))
566 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
568 showReg :: RegNo -> String
570 | n >= 16 = "%xmm" ++ show (n-16)
571 | n >= 8 = "%r" ++ show n
572 | otherwise = regNames !! n
577 The SPARC has 64 registers of interest; 32 integer registers and 32
578 floating point registers. The mapping of STG registers to SPARC
579 machine registers is defined in StgRegs.h. We are, of course,
580 prepared for any eventuality.
582 The whole fp-register pairing thing on sparcs is a huge nuisance. See
583 fptools/ghc/includes/MachRegs.h for a description of what's going on
587 #if sparc_TARGET_ARCH
589 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
596 nCG_FirstFloatReg :: RegNo
597 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
599 regClass (VirtualRegI u) = RcInteger
600 regClass (VirtualRegF u) = RcFloat
601 regClass (VirtualRegD u) = RcDouble
602 regClass (RealReg i) | i < 32 = RcInteger
603 | i < nCG_FirstFloatReg = RcDouble
604 | otherwise = RcFloat
606 showReg :: RegNo -> String
608 | n >= 0 && n < 8 = "%g" ++ show n
609 | n >= 8 && n < 16 = "%o" ++ show (n-8)
610 | n >= 16 && n < 24 = "%l" ++ show (n-16)
611 | n >= 24 && n < 32 = "%i" ++ show (n-24)
612 | n >= 32 && n < 64 = "%f" ++ show (n-32)
613 | otherwise = "%unknown_sparc_real_reg_" ++ show n
615 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
617 f6 = RealReg (fReg 6)
618 f8 = RealReg (fReg 8)
619 f22 = RealReg (fReg 22)
620 f26 = RealReg (fReg 26)
621 f27 = RealReg (fReg 27)
624 -- g0 is useful for codegen; is always zero, and writes to it vanish.
625 g0 = RealReg (gReg 0)
626 g1 = RealReg (gReg 1)
627 g2 = RealReg (gReg 2)
629 -- FP, SP, int and float return (from C) regs.
630 fp = RealReg (iReg 6)
631 sp = RealReg (oReg 6)
632 o0 = RealReg (oReg 0)
633 o1 = RealReg (oReg 1)
634 f0 = RealReg (fReg 0)
635 f1 = RealReg (fReg 1)
640 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
644 #if powerpc_TARGET_ARCH
648 regClass (VirtualRegI u) = RcInteger
649 regClass (VirtualRegHi u) = RcInteger
650 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
651 (ppr (VirtualRegF u))
652 regClass (VirtualRegD u) = RcDouble
653 regClass (RealReg i) | i < 32 = RcInteger
654 | otherwise = RcDouble
656 showReg :: RegNo -> String
658 | n >= 0 && n <= 31 = "%r" ++ show n
659 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
660 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
667 f1 = RealReg $ fReg 1
668 f20 = RealReg $ fReg 20
669 f21 = RealReg $ fReg 21
673 Redefine the literals used for machine-registers with non-numeric
674 names in the header files. Gag me with a spoon, eh?
677 #if alpha_TARGET_ARCH
728 #if x86_64_TARGET_ARCH
763 #if sparc_TARGET_ARCH
831 #if powerpc_TARGET_ARCH
865 #ifdef darwin_TARGET_OS
935 -- allMachRegs is the complete set of machine regs.
936 allMachRegNos :: [RegNo]
938 = IF_ARCH_alpha( [0..63],
939 IF_ARCH_i386( [0..13],
940 IF_ARCH_x86_64( [0..31],
941 IF_ARCH_sparc( ([0..31]
942 ++ [f0,f2 .. nCG_FirstFloatReg-1]
943 ++ [nCG_FirstFloatReg .. f31]),
944 IF_ARCH_powerpc([0..63],
947 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
948 -- i.e., these are the regs for which we are prepared to allow the
949 -- register allocator to attempt to map VRegs to.
950 allocatableRegs :: [RegNo]
952 = let isFree i = isFastTrue (freeReg i)
953 in filter isFree allMachRegNos
955 -- these are the regs which we cannot assume stay alive over a
957 callClobberedRegs :: [Reg]
960 #if alpha_TARGET_ARCH
961 [0, 1, 2, 3, 4, 5, 6, 7, 8,
962 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
963 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
964 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
965 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
966 #endif /* alpha_TARGET_ARCH */
968 -- caller-saves registers
969 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
970 #endif /* i386_TARGET_ARCH */
971 #if x86_64_TARGET_ARCH
972 -- caller-saves registers
973 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
974 -- all xmm regs are caller-saves
975 #endif /* x86_64_TARGET_ARCH */
976 #if sparc_TARGET_ARCH
979 [oReg i | i <- [0..5]] ++
980 [gReg i | i <- [1..7]] ++
981 [fReg i | i <- [0..31]] )
982 #endif /* sparc_TARGET_ARCH */
983 #if powerpc_TARGET_ARCH
985 map RealReg (0:[2..12] ++ map fReg [0..13])
986 #elif linux_TARGET_OS
987 map RealReg (0:[2..13] ++ map fReg [0..13])
989 #endif /* powerpc_TARGET_ARCH */
992 -- argRegs is the set of regs which are read for an n-argument call to C.
993 -- For archs which pass all args on the stack (x86), is empty.
994 -- Sparc passes up to the first 6 args in regs.
995 -- Dunno about Alpha.
996 argRegs :: RegNo -> [Reg]
999 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1002 #if x86_64_TARGET_ARCH
1003 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1006 #if alpha_TARGET_ARCH
1008 argRegs 1 = freeMappedRegs [16, fReg 16]
1009 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1010 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1011 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1012 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1013 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1014 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1015 #endif /* alpha_TARGET_ARCH */
1017 #if sparc_TARGET_ARCH
1019 argRegs 1 = map (RealReg . oReg) [0]
1020 argRegs 2 = map (RealReg . oReg) [0,1]
1021 argRegs 3 = map (RealReg . oReg) [0,1,2]
1022 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1023 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1024 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1025 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1026 #endif /* sparc_TARGET_ARCH */
1028 #if powerpc_TARGET_ARCH
1030 argRegs 1 = map RealReg [3]
1031 argRegs 2 = map RealReg [3,4]
1032 argRegs 3 = map RealReg [3..5]
1033 argRegs 4 = map RealReg [3..6]
1034 argRegs 5 = map RealReg [3..7]
1035 argRegs 6 = map RealReg [3..8]
1036 argRegs 7 = map RealReg [3..9]
1037 argRegs 8 = map RealReg [3..10]
1038 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1039 #endif /* powerpc_TARGET_ARCH */
1042 -- all of the arg regs ??
1043 #if alpha_TARGET_ARCH
1044 allArgRegs :: [(Reg, Reg)]
1045 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1046 #endif /* alpha_TARGET_ARCH */
1048 #if sparc_TARGET_ARCH
1050 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1051 #endif /* sparc_TARGET_ARCH */
1053 #if i386_TARGET_ARCH
1055 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1058 #if x86_64_TARGET_ARCH
1060 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1061 allFPArgRegs :: [Reg]
1062 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1065 #if powerpc_TARGET_ARCH
1067 allArgRegs = map RealReg [3..10]
1068 allFPArgRegs :: [Reg]
1069 #if darwin_TARGET_OS
1070 allFPArgRegs = map (RealReg . fReg) [1..13]
1071 #elif linux_TARGET_OS
1072 allFPArgRegs = map (RealReg . fReg) [1..8]
1074 #endif /* powerpc_TARGET_ARCH */
1078 freeReg :: RegNo -> FastBool
1080 #if alpha_TARGET_ARCH
1081 freeReg 26 = fastBool False -- return address (ra)
1082 freeReg 28 = fastBool False -- reserved for the assembler (at)
1083 freeReg 29 = fastBool False -- global pointer (gp)
1084 freeReg 30 = fastBool False -- stack pointer (sp)
1085 freeReg 31 = fastBool False -- always zero (zeroh)
1086 freeReg 63 = fastBool False -- always zero (f31)
1089 #if i386_TARGET_ARCH
1090 freeReg esp = fastBool False -- %esp is the C stack pointer
1093 #if x86_64_TARGET_ARCH
1094 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1097 #if sparc_TARGET_ARCH
1098 freeReg g0 = fastBool False -- %g0 is always 0.
1099 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1100 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1101 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1102 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1103 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1104 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1105 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1106 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1107 freeReg f1 = fastBool False
1110 #if powerpc_TARGET_ARCH
1111 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1112 freeReg 1 = fastBool False -- The Stack Pointer
1113 #if !darwin_TARGET_OS
1114 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1115 freeReg 2 = fastBool False
1120 freeReg REG_Base = fastBool False
1123 freeReg REG_R1 = fastBool False
1126 freeReg REG_R2 = fastBool False
1129 freeReg REG_R3 = fastBool False
1132 freeReg REG_R4 = fastBool False
1135 freeReg REG_R5 = fastBool False
1138 freeReg REG_R6 = fastBool False
1141 freeReg REG_R7 = fastBool False
1144 freeReg REG_R8 = fastBool False
1147 freeReg REG_F1 = fastBool False
1150 freeReg REG_F2 = fastBool False
1153 freeReg REG_F3 = fastBool False
1156 freeReg REG_F4 = fastBool False
1159 freeReg REG_D1 = fastBool False
1162 freeReg REG_D2 = fastBool False
1165 freeReg REG_Sp = fastBool False
1168 freeReg REG_Su = fastBool False
1171 freeReg REG_SpLim = fastBool False
1174 freeReg REG_Hp = fastBool False
1177 freeReg REG_HpLim = fastBool False
1179 freeReg n = fastBool True
1182 -- | Returns 'Nothing' if this global register is not stored
1183 -- in a real machine register, otherwise returns @'Just' reg@, where
1184 -- reg is the machine register it is stored in.
1186 globalRegMaybe :: GlobalReg -> Maybe Reg
1189 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1192 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1195 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1198 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1201 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1204 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1207 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1210 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1213 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1216 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1219 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1222 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1225 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1228 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1231 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1234 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1237 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1240 globalRegMaybe Sp = Just (RealReg REG_Sp)
1243 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1246 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1249 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1252 globalRegMaybe Hp = Just (RealReg REG_Hp)
1255 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1257 #ifdef REG_CurrentTSO
1258 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1260 #ifdef REG_CurrentNursery
1261 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1263 globalRegMaybe _ = Nothing