1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
36 callerSaves, callerSaveVolatileRegs,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 EABase(..), EAIndex(..),
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 EABase(..), EAIndex(..), ripRel,
56 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 r8, r9, r10, r11, r12, r13, r14, r15,
59 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
60 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
62 addrModeRegs, allFPArgRegs,
66 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
67 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
69 #if powerpc_TARGET_ARCH
78 #include "HsVersions.h"
81 # define STOLEN_X86_REGS 4
82 -- HACK: go for the max
85 #include "../includes/MachRegs.h"
88 import MachOp ( MachRep(..) )
90 import CLabel ( CLabel, mkMainCapabilityLabel )
92 import Outputable ( Outputable(..), pprPanic, panic )
93 import qualified Outputable
98 #if powerpc_TARGET_ARCH
99 #if __GLASGOW_HASKELL__ >= 504
100 import Data.Word ( Word8, Word16, Word32 )
101 import Data.Int ( Int8, Int16, Int32 )
103 import Word ( Word8, Word16, Word32 )
104 import Int ( Int8, Int16, Int32 )
108 -- -----------------------------------------------------------------------------
113 | ImmInteger Integer -- Sigh.
114 | ImmCLbl CLabel -- AbstractC Label (with baggage)
115 | ImmLit Doc -- Simple string
116 | ImmIndex CLabel Int
119 | ImmConstantSum Imm Imm
120 | ImmConstantDiff Imm Imm
121 #if sparc_TARGET_ARCH
122 | LO Imm {- Possible restrictions... -}
125 #if powerpc_TARGET_ARCH
128 | HA Imm {- high halfword adjusted -}
130 strImmLit s = ImmLit (text s)
132 litToImm :: CmmLit -> Imm
133 litToImm (CmmInt i _) = ImmInteger i
134 litToImm (CmmFloat f F32) = ImmFloat f
135 litToImm (CmmFloat f F64) = ImmDouble f
136 litToImm (CmmLabel l) = ImmCLbl l
137 litToImm (CmmLabelOff l off) = ImmIndex l off
138 litToImm (CmmLabelDiffOff l1 l2 off)
140 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
143 -- -----------------------------------------------------------------------------
147 #if alpha_TARGET_ARCH
153 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
154 = AddrBaseIndex EABase EAIndex Displacement
157 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
158 data EAIndex = EAIndexNone | EAIndex Reg Int
159 type Displacement = Imm
162 #if sparc_TARGET_ARCH
167 #if powerpc_TARGET_ARCH
172 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
173 addrModeRegs :: AddrMode -> [Reg]
174 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
176 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
177 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
182 addrOffset :: AddrMode -> Int -> Maybe AddrMode
186 #if alpha_TARGET_ARCH
187 _ -> panic "MachMisc.addrOffset not defined for Alpha"
189 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
190 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
192 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
193 AddrBaseIndex r i (ImmInteger n)
194 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
196 AddrBaseIndex r i (ImmCLbl lbl)
197 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
199 AddrBaseIndex r i (ImmIndex lbl ix)
200 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
202 _ -> Nothing -- in theory, shouldn't happen
204 #if sparc_TARGET_ARCH
205 AddrRegImm r (ImmInt n)
206 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
207 | otherwise -> Nothing
210 AddrRegImm r (ImmInteger n)
211 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
212 | otherwise -> Nothing
213 where n2 = n + toInteger off
215 AddrRegReg r (RealReg 0)
216 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
217 | otherwise -> Nothing
221 #if powerpc_TARGET_ARCH
222 AddrRegImm r (ImmInt n)
223 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
224 | otherwise -> Nothing
227 AddrRegImm r (ImmInteger n)
228 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
229 | otherwise -> Nothing
230 where n2 = n + toInteger off
236 #if alpha_TARGET_ARCH
238 fits8Bits :: Integer -> Bool
239 fits8Bits i = i >= -256 && i < 256
243 #if sparc_TARGET_ARCH
245 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
246 fits13Bits :: Integral a => a -> Bool
247 fits13Bits x = x >= -4096 && x < 4096
251 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
252 ++show i++");\nprobably because of large constant data structures;" ++
253 "\nworkaround: use -fvia-C on this module.\n")
257 #if powerpc_TARGET_ARCH
258 fits16Bits :: Integral a => a -> Bool
259 fits16Bits x = x >= -32768 && x < 32768
261 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
263 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
265 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
266 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
267 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
268 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
269 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
270 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
272 narrowed = narrow rep signed
275 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
276 | otherwise = Nothing
278 | narrowed >= 0 && narrowed < 65536 = Just narrowed
279 | otherwise = Nothing
280 toI16 _ _ = Just narrowed
284 -- @spRel@ gives us a stack relative addressing mode for volatile
285 -- temporaries and for excess call arguments. @fpRel@, where
286 -- applicable, is the same but for the frame pointer.
288 spRel :: Int -- desired stack offset in words, positive or negative
292 #if defined(i386_TARGET_ARCH)
293 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
294 #elif defined(x86_64_TARGET_ARCH)
295 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
297 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
300 #if sparc_TARGET_ARCH
301 fpRel :: Int -> AddrMode
302 -- Duznae work for offsets greater than 13 bits; we just hope for
305 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
308 #if x86_64_TARGET_ARCH
309 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
312 -- -----------------------------------------------------------------------------
315 -- We map STG registers onto appropriate CmmExprs. Either they map
316 -- to real machine registers or stored as offsets from BaseReg. Given
317 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
318 -- register it is in, on this platform, or a StixExpr denoting the
319 -- address in the register table holding it. get_MagicId_addr always
320 -- produces the register table address for it.
322 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
323 get_GlobalReg_addr :: GlobalReg -> CmmExpr
324 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
326 get_GlobalReg_reg_or_addr mid
327 = case globalRegMaybe mid of
329 Nothing -> Right (get_GlobalReg_addr mid)
331 get_GlobalReg_addr BaseReg = regTableOffset 0
332 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
333 (globalRegRep mid) (baseRegOffset mid)
335 -- Calculate a literal representing an offset into the register table.
336 -- Used when we don't have an actual BaseReg to offset from.
338 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
340 get_Regtable_addr_from_offset rep offset
341 = case globalRegMaybe BaseReg of
342 Nothing -> regTableOffset offset
343 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
345 -- -----------------------------------------------------------------------------
346 -- caller-save registers
348 -- Here we generate the sequence of saves/restores required around a
349 -- foreign call instruction.
351 callerSaveVolatileRegs :: Maybe [GlobalReg] -> ([CmmStmt], [CmmStmt])
352 callerSaveVolatileRegs vols = (caller_save, caller_load)
354 caller_save = foldr ($!) [] (map callerSaveGlobalReg regs_to_save)
355 caller_load = foldr ($!) [] (map callerRestoreGlobalReg regs_to_save)
357 system_regs = [Sp,SpLim,Hp,HpLim,CurrentTSO,CurrentNursery,
358 {-SparkHd,SparkTl,SparkBase,SparkLim,-}BaseReg ]
360 regs_to_save = system_regs ++ vol_list
362 vol_list = case vols of Nothing -> all_of_em; Just regs -> regs
364 all_of_em = [ VanillaReg n | n <- [0..mAX_Vanilla_REG] ]
365 ++ [ FloatReg n | n <- [0..mAX_Float_REG] ]
366 ++ [ DoubleReg n | n <- [0..mAX_Double_REG] ]
367 ++ [ LongReg n | n <- [0..mAX_Long_REG] ]
369 callerSaveGlobalReg reg next
371 CmmStore (get_GlobalReg_addr reg)
372 (CmmReg (CmmGlobal reg)) : next
375 callerRestoreGlobalReg reg next
377 CmmAssign (CmmGlobal reg)
378 (CmmLoad (get_GlobalReg_addr reg) (globalRegRep reg))
383 -- ---------------------------------------------------------------------------
386 -- RealRegs are machine regs which are available for allocation, in
387 -- the usual way. We know what class they are, because that's part of
388 -- the processor's architecture.
390 -- VirtualRegs are virtual registers. The register allocator will
391 -- eventually have to map them into RealRegs, or into spill slots.
392 -- VirtualRegs are allocated on the fly, usually to represent a single
393 -- value in the abstract assembly code (i.e. dynamic registers are
394 -- usually single assignment). With the new register allocator, the
395 -- single assignment restriction isn't necessary to get correct code,
396 -- although a better register allocation will result if single
397 -- assignment is used -- because the allocator maps a VirtualReg into
398 -- a single RealReg, even if the VirtualReg has multiple live ranges.
400 -- Virtual regs can be of either class, so that info is attached.
402 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
403 -- when supplied with the vreg for the lower-half of the quantity.
404 -- (NB. Not reversible).
405 getHiVRegFromLo (VirtualRegI u)
406 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
407 getHiVRegFromLo other
408 = pprPanic "getHiVRegFromLo" (ppr other)
419 = RealReg {-# UNPACK #-} !RegNo
420 | VirtualRegI {-# UNPACK #-} !Unique
421 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
422 | VirtualRegF {-# UNPACK #-} !Unique
423 | VirtualRegD {-# UNPACK #-} !Unique
426 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
427 -- in the register allocator.
428 instance Uniquable Reg where
429 getUnique (RealReg i) = mkUnique 'C' i
430 getUnique (VirtualRegI u) = u
431 getUnique (VirtualRegHi u) = u
432 getUnique (VirtualRegF u) = u
433 getUnique (VirtualRegD u) = u
435 unRealReg (RealReg i) = i
436 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
438 mkVReg :: Unique -> MachRep -> Reg
441 #if sparc_TARGET_ARCH
447 other -> VirtualRegI u
449 isVirtualReg :: Reg -> Bool
450 isVirtualReg (RealReg _) = False
451 isVirtualReg (VirtualRegI _) = True
452 isVirtualReg (VirtualRegHi _) = True
453 isVirtualReg (VirtualRegF _) = True
454 isVirtualReg (VirtualRegD _) = True
456 isRealReg :: Reg -> Bool
457 isRealReg = not . isVirtualReg
459 instance Show Reg where
460 show (RealReg i) = showReg i
461 show (VirtualRegI u) = "%vI_" ++ show u
462 show (VirtualRegHi u) = "%vHi_" ++ show u
463 show (VirtualRegF u) = "%vF_" ++ show u
464 show (VirtualRegD u) = "%vD_" ++ show u
466 instance Outputable Reg where
467 ppr r = Outputable.text (show r)
470 -- -----------------------------------------------------------------------------
471 -- Machine-specific register stuff
473 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
474 -- point registers. The mapping of STG registers to alpha machine registers
475 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
477 #if alpha_TARGET_ARCH
481 v0, f0, ra, pv, gp, sp, zeroh :: Reg
483 f0 = realReg (fReg 0)
484 ra = FixedReg ILIT(26)
486 gp = FixedReg ILIT(29)
487 sp = FixedReg ILIT(30)
488 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
490 t9, t10, t11, t12 :: Reg
498 Intel x86 architecture:
499 - All registers except 7 (esp) are available for use.
500 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
501 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
502 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
503 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
504 fp registers, and 3-operand insns for them, and we translate this into
505 real stack-based x86 fp code after register allocation.
507 The fp registers are all Double registers; we don't have any RcFloat class
508 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
514 fake0, fake1, fake2, fake3, fake4, fake5,
515 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
531 -- On x86, we might want to have an 8-bit RegClass, which would
532 -- contain just regs 1-4 (the others don't have 8-bit versions).
533 -- However, we can get away without this at the moment because the
534 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
535 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
536 regClass (VirtualRegI u) = RcInteger
537 regClass (VirtualRegHi u) = RcInteger
538 regClass (VirtualRegD u) = RcDouble
539 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
540 (ppr (VirtualRegF u))
543 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
544 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
546 showReg :: RegNo -> String
548 = if n >= 0 && n < 14
550 else "%unknown_x86_real_reg_" ++ show n
555 AMD x86_64 architecture:
556 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
557 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
558 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
562 #if x86_64_TARGET_ARCH
564 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
565 r8, r9, r10, r11, r12, r13, r14, r15,
566 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
567 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
602 -- so we can re-use some x86 code:
612 xmm n = RealReg (16+n)
614 -- On x86, we might want to have an 8-bit RegClass, which would
615 -- contain just regs 1-4 (the others don't have 8-bit versions).
616 -- However, we can get away without this at the moment because the
617 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
618 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
619 regClass (VirtualRegI u) = RcInteger
620 regClass (VirtualRegHi u) = RcInteger
621 regClass (VirtualRegD u) = RcDouble
622 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
623 (ppr (VirtualRegF u))
626 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
628 showReg :: RegNo -> String
630 | n >= 16 = "%xmm" ++ show (n-16)
631 | n >= 8 = "%r" ++ show n
632 | otherwise = regNames !! n
637 The SPARC has 64 registers of interest; 32 integer registers and 32
638 floating point registers. The mapping of STG registers to SPARC
639 machine registers is defined in StgRegs.h. We are, of course,
640 prepared for any eventuality.
642 The whole fp-register pairing thing on sparcs is a huge nuisance. See
643 fptools/ghc/includes/MachRegs.h for a description of what's going on
647 #if sparc_TARGET_ARCH
649 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
656 nCG_FirstFloatReg :: RegNo
657 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
659 regClass (VirtualRegI u) = RcInteger
660 regClass (VirtualRegF u) = RcFloat
661 regClass (VirtualRegD u) = RcDouble
662 regClass (RealReg i) | i < 32 = RcInteger
663 | i < nCG_FirstFloatReg = RcDouble
664 | otherwise = RcFloat
666 showReg :: RegNo -> String
668 | n >= 0 && n < 8 = "%g" ++ show n
669 | n >= 8 && n < 16 = "%o" ++ show (n-8)
670 | n >= 16 && n < 24 = "%l" ++ show (n-16)
671 | n >= 24 && n < 32 = "%i" ++ show (n-24)
672 | n >= 32 && n < 64 = "%f" ++ show (n-32)
673 | otherwise = "%unknown_sparc_real_reg_" ++ show n
675 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
677 f6 = RealReg (fReg 6)
678 f8 = RealReg (fReg 8)
679 f22 = RealReg (fReg 22)
680 f26 = RealReg (fReg 26)
681 f27 = RealReg (fReg 27)
684 -- g0 is useful for codegen; is always zero, and writes to it vanish.
685 g0 = RealReg (gReg 0)
686 g1 = RealReg (gReg 1)
687 g2 = RealReg (gReg 2)
689 -- FP, SP, int and float return (from C) regs.
690 fp = RealReg (iReg 6)
691 sp = RealReg (oReg 6)
692 o0 = RealReg (oReg 0)
693 o1 = RealReg (oReg 1)
694 f0 = RealReg (fReg 0)
695 f1 = RealReg (fReg 1)
700 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
704 #if powerpc_TARGET_ARCH
708 regClass (VirtualRegI u) = RcInteger
709 regClass (VirtualRegHi u) = RcInteger
710 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
711 (ppr (VirtualRegF u))
712 regClass (VirtualRegD u) = RcDouble
713 regClass (RealReg i) | i < 32 = RcInteger
714 | otherwise = RcDouble
716 showReg :: RegNo -> String
718 | n >= 0 && n <= 31 = "%r" ++ show n
719 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
720 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
727 f1 = RealReg $ fReg 1
728 f20 = RealReg $ fReg 20
729 f21 = RealReg $ fReg 21
733 Redefine the literals used for machine-registers with non-numeric
734 names in the header files. Gag me with a spoon, eh?
737 #if alpha_TARGET_ARCH
788 #if x86_64_TARGET_ARCH
823 #if sparc_TARGET_ARCH
891 #if powerpc_TARGET_ARCH
925 #ifdef darwin_TARGET_OS
995 -- allMachRegs is the complete set of machine regs.
996 allMachRegNos :: [RegNo]
998 = IF_ARCH_alpha( [0..63],
999 IF_ARCH_i386( [0..13],
1000 IF_ARCH_x86_64( [0..31],
1001 IF_ARCH_sparc( ([0..31]
1002 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1003 ++ [nCG_FirstFloatReg .. f31]),
1004 IF_ARCH_powerpc([0..63],
1007 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1008 -- i.e., these are the regs for which we are prepared to allow the
1009 -- register allocator to attempt to map VRegs to.
1010 allocatableRegs :: [RegNo]
1012 = let isFree i = isFastTrue (freeReg i)
1013 in filter isFree allMachRegNos
1015 -- these are the regs which we cannot assume stay alive over a
1017 callClobberedRegs :: [Reg]
1020 #if alpha_TARGET_ARCH
1021 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1022 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1023 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1024 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1025 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1026 #endif /* alpha_TARGET_ARCH */
1027 #if i386_TARGET_ARCH
1028 -- caller-saves registers
1029 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1030 #endif /* i386_TARGET_ARCH */
1031 #if x86_64_TARGET_ARCH
1032 -- caller-saves registers
1033 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1034 -- all xmm regs are caller-saves
1035 #endif /* x86_64_TARGET_ARCH */
1036 #if sparc_TARGET_ARCH
1039 [oReg i | i <- [0..5]] ++
1040 [gReg i | i <- [1..7]] ++
1041 [fReg i | i <- [0..31]] )
1042 #endif /* sparc_TARGET_ARCH */
1043 #if powerpc_TARGET_ARCH
1044 #if darwin_TARGET_OS
1045 map RealReg (0:[2..12] ++ map fReg [0..13])
1046 #elif linux_TARGET_OS
1047 map RealReg (0:[2..13] ++ map fReg [0..13])
1049 #endif /* powerpc_TARGET_ARCH */
1052 -- argRegs is the set of regs which are read for an n-argument call to C.
1053 -- For archs which pass all args on the stack (x86), is empty.
1054 -- Sparc passes up to the first 6 args in regs.
1055 -- Dunno about Alpha.
1056 argRegs :: RegNo -> [Reg]
1058 #if i386_TARGET_ARCH
1059 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1062 #if x86_64_TARGET_ARCH
1063 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1066 #if alpha_TARGET_ARCH
1068 argRegs 1 = freeMappedRegs [16, fReg 16]
1069 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1070 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1071 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1072 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1073 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1074 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1075 #endif /* alpha_TARGET_ARCH */
1077 #if sparc_TARGET_ARCH
1079 argRegs 1 = map (RealReg . oReg) [0]
1080 argRegs 2 = map (RealReg . oReg) [0,1]
1081 argRegs 3 = map (RealReg . oReg) [0,1,2]
1082 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1083 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1084 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1085 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1086 #endif /* sparc_TARGET_ARCH */
1088 #if powerpc_TARGET_ARCH
1090 argRegs 1 = map RealReg [3]
1091 argRegs 2 = map RealReg [3,4]
1092 argRegs 3 = map RealReg [3..5]
1093 argRegs 4 = map RealReg [3..6]
1094 argRegs 5 = map RealReg [3..7]
1095 argRegs 6 = map RealReg [3..8]
1096 argRegs 7 = map RealReg [3..9]
1097 argRegs 8 = map RealReg [3..10]
1098 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1099 #endif /* powerpc_TARGET_ARCH */
1102 -- all of the arg regs ??
1103 #if alpha_TARGET_ARCH
1104 allArgRegs :: [(Reg, Reg)]
1105 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1106 #endif /* alpha_TARGET_ARCH */
1108 #if sparc_TARGET_ARCH
1110 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1111 #endif /* sparc_TARGET_ARCH */
1113 #if i386_TARGET_ARCH
1115 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1118 #if x86_64_TARGET_ARCH
1120 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1121 allFPArgRegs :: [Reg]
1122 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1125 #if powerpc_TARGET_ARCH
1127 allArgRegs = map RealReg [3..10]
1128 allFPArgRegs :: [Reg]
1129 #if darwin_TARGET_OS
1130 allFPArgRegs = map (RealReg . fReg) [1..13]
1131 #elif linux_TARGET_OS
1132 allFPArgRegs = map (RealReg . fReg) [1..8]
1134 #endif /* powerpc_TARGET_ARCH */
1138 freeReg :: RegNo -> FastBool
1140 #if alpha_TARGET_ARCH
1141 freeReg 26 = fastBool False -- return address (ra)
1142 freeReg 28 = fastBool False -- reserved for the assembler (at)
1143 freeReg 29 = fastBool False -- global pointer (gp)
1144 freeReg 30 = fastBool False -- stack pointer (sp)
1145 freeReg 31 = fastBool False -- always zero (zeroh)
1146 freeReg 63 = fastBool False -- always zero (f31)
1149 #if i386_TARGET_ARCH
1150 freeReg esp = fastBool False -- %esp is the C stack pointer
1153 #if x86_64_TARGET_ARCH
1154 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1157 #if sparc_TARGET_ARCH
1158 freeReg g0 = fastBool False -- %g0 is always 0.
1159 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1160 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1161 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1162 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1163 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1164 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1165 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1166 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1167 freeReg f1 = fastBool False
1170 #if powerpc_TARGET_ARCH
1171 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1172 freeReg 1 = fastBool False -- The Stack Pointer
1173 #if !darwin_TARGET_OS
1174 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1175 freeReg 2 = fastBool False
1180 freeReg REG_Base = fastBool False
1183 freeReg REG_R1 = fastBool False
1186 freeReg REG_R2 = fastBool False
1189 freeReg REG_R3 = fastBool False
1192 freeReg REG_R4 = fastBool False
1195 freeReg REG_R5 = fastBool False
1198 freeReg REG_R6 = fastBool False
1201 freeReg REG_R7 = fastBool False
1204 freeReg REG_R8 = fastBool False
1207 freeReg REG_F1 = fastBool False
1210 freeReg REG_F2 = fastBool False
1213 freeReg REG_F3 = fastBool False
1216 freeReg REG_F4 = fastBool False
1219 freeReg REG_D1 = fastBool False
1222 freeReg REG_D2 = fastBool False
1225 freeReg REG_Sp = fastBool False
1228 freeReg REG_Su = fastBool False
1231 freeReg REG_SpLim = fastBool False
1234 freeReg REG_Hp = fastBool False
1237 freeReg REG_HpLim = fastBool False
1239 freeReg n = fastBool True
1242 -- -----------------------------------------------------------------------------
1243 -- Information about global registers
1245 baseRegOffset :: GlobalReg -> Int
1247 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1248 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1249 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1250 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1251 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1252 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1253 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1254 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1255 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1256 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1257 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1258 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1259 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1260 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1261 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1262 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1263 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1264 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1265 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1266 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1267 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1268 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1269 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1270 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1271 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1272 baseRegOffset GCFun = oFFSET_stgGCFun
1274 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1275 baseRegOffset _ = panic "baseRegOffset:other"
1279 -- | Returns 'True' if this global register is stored in a caller-saves
1280 -- machine register.
1282 callerSaves :: GlobalReg -> Bool
1284 #ifdef CALLER_SAVES_Base
1285 callerSaves BaseReg = True
1287 #ifdef CALLER_SAVES_R1
1288 callerSaves (VanillaReg 1) = True
1290 #ifdef CALLER_SAVES_R2
1291 callerSaves (VanillaReg 2) = True
1293 #ifdef CALLER_SAVES_R3
1294 callerSaves (VanillaReg 3) = True
1296 #ifdef CALLER_SAVES_R4
1297 callerSaves (VanillaReg 4) = True
1299 #ifdef CALLER_SAVES_R5
1300 callerSaves (VanillaReg 5) = True
1302 #ifdef CALLER_SAVES_R6
1303 callerSaves (VanillaReg 6) = True
1305 #ifdef CALLER_SAVES_R7
1306 callerSaves (VanillaReg 7) = True
1308 #ifdef CALLER_SAVES_R8
1309 callerSaves (VanillaReg 8) = True
1311 #ifdef CALLER_SAVES_F1
1312 callerSaves (FloatReg 1) = True
1314 #ifdef CALLER_SAVES_F2
1315 callerSaves (FloatReg 2) = True
1317 #ifdef CALLER_SAVES_F3
1318 callerSaves (FloatReg 3) = True
1320 #ifdef CALLER_SAVES_F4
1321 callerSaves (FloatReg 4) = True
1323 #ifdef CALLER_SAVES_D1
1324 callerSaves (DoubleReg 1) = True
1326 #ifdef CALLER_SAVES_D2
1327 callerSaves (DoubleReg 2) = True
1329 #ifdef CALLER_SAVES_L1
1330 callerSaves (LongReg 1) = True
1332 #ifdef CALLER_SAVES_Sp
1333 callerSaves Sp = True
1335 #ifdef CALLER_SAVES_SpLim
1336 callerSaves SpLim = True
1338 #ifdef CALLER_SAVES_Hp
1339 callerSaves Hp = True
1341 #ifdef CALLER_SAVES_HpLim
1342 callerSaves HpLim = True
1344 #ifdef CALLER_SAVES_CurrentTSO
1345 callerSaves CurrentTSO = True
1347 #ifdef CALLER_SAVES_CurrentNursery
1348 callerSaves CurrentNursery = True
1350 callerSaves _ = False
1353 -- | Returns 'Nothing' if this global register is not stored
1354 -- in a real machine register, otherwise returns @'Just' reg@, where
1355 -- reg is the machine register it is stored in.
1357 globalRegMaybe :: GlobalReg -> Maybe Reg
1360 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1363 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1366 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1369 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1372 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1375 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1378 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1381 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1384 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1387 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1390 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1393 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1396 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1399 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1402 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1405 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1408 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1411 globalRegMaybe Sp = Just (RealReg REG_Sp)
1414 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1417 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1420 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1423 globalRegMaybe Hp = Just (RealReg REG_Hp)
1426 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1428 #ifdef REG_CurrentTSO
1429 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1431 #ifdef REG_CurrentNursery
1432 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1434 globalRegMaybe _ = Nothing