1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
36 callerSaves, callerSaveVolatileRegs,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 EABase(..), EAIndex(..),
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 EABase(..), EAIndex(..), ripRel,
56 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 r8, r9, r10, r11, r12, r13, r14, r15,
59 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
60 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
62 addrModeRegs, allFPArgRegs,
66 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
67 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
69 #if powerpc_TARGET_ARCH
78 #include "HsVersions.h"
81 # define STOLEN_X86_REGS 4
82 -- HACK: go for the max
85 #include "../includes/MachRegs.h"
88 import MachOp ( MachRep(..) )
90 import CLabel ( CLabel, mkMainCapabilityLabel )
92 import Outputable ( Outputable(..), pprPanic, panic )
93 import qualified Outputable
98 #if powerpc_TARGET_ARCH
99 import Data.Word ( Word8, Word16, Word32 )
100 import Data.Int ( Int8, Int16, Int32 )
103 -- -----------------------------------------------------------------------------
108 | ImmInteger Integer -- Sigh.
109 | ImmCLbl CLabel -- AbstractC Label (with baggage)
110 | ImmLit Doc -- Simple string
111 | ImmIndex CLabel Int
114 | ImmConstantSum Imm Imm
115 | ImmConstantDiff Imm Imm
116 #if sparc_TARGET_ARCH
117 | LO Imm {- Possible restrictions... -}
120 #if powerpc_TARGET_ARCH
123 | HA Imm {- high halfword adjusted -}
125 strImmLit s = ImmLit (text s)
127 litToImm :: CmmLit -> Imm
128 litToImm (CmmInt i _) = ImmInteger i
129 litToImm (CmmFloat f F32) = ImmFloat f
130 litToImm (CmmFloat f F64) = ImmDouble f
131 litToImm (CmmLabel l) = ImmCLbl l
132 litToImm (CmmLabelOff l off) = ImmIndex l off
133 litToImm (CmmLabelDiffOff l1 l2 off)
135 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
138 -- -----------------------------------------------------------------------------
142 #if alpha_TARGET_ARCH
148 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
149 = AddrBaseIndex EABase EAIndex Displacement
152 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
153 data EAIndex = EAIndexNone | EAIndex Reg Int
154 type Displacement = Imm
157 #if sparc_TARGET_ARCH
162 #if powerpc_TARGET_ARCH
167 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
168 addrModeRegs :: AddrMode -> [Reg]
169 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
171 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
172 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
177 addrOffset :: AddrMode -> Int -> Maybe AddrMode
181 #if alpha_TARGET_ARCH
182 _ -> panic "MachMisc.addrOffset not defined for Alpha"
184 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
185 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
187 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
188 AddrBaseIndex r i (ImmInteger n)
189 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
191 AddrBaseIndex r i (ImmCLbl lbl)
192 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
194 AddrBaseIndex r i (ImmIndex lbl ix)
195 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
197 _ -> Nothing -- in theory, shouldn't happen
199 #if sparc_TARGET_ARCH
200 AddrRegImm r (ImmInt n)
201 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
202 | otherwise -> Nothing
205 AddrRegImm r (ImmInteger n)
206 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
207 | otherwise -> Nothing
208 where n2 = n + toInteger off
210 AddrRegReg r (RealReg 0)
211 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
212 | otherwise -> Nothing
216 #if powerpc_TARGET_ARCH
217 AddrRegImm r (ImmInt n)
218 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
219 | otherwise -> Nothing
222 AddrRegImm r (ImmInteger n)
223 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
224 | otherwise -> Nothing
225 where n2 = n + toInteger off
231 #if alpha_TARGET_ARCH
233 fits8Bits :: Integer -> Bool
234 fits8Bits i = i >= -256 && i < 256
238 #if sparc_TARGET_ARCH
240 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
241 fits13Bits :: Integral a => a -> Bool
242 fits13Bits x = x >= -4096 && x < 4096
246 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
247 ++show i++");\nprobably because of large constant data structures;" ++
248 "\nworkaround: use -fvia-C on this module.\n")
252 #if powerpc_TARGET_ARCH
253 fits16Bits :: Integral a => a -> Bool
254 fits16Bits x = x >= -32768 && x < 32768
256 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
258 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
260 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
261 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
262 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
263 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
264 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
265 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
267 narrowed = narrow rep signed
270 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
271 | otherwise = Nothing
273 | narrowed >= 0 && narrowed < 65536 = Just narrowed
274 | otherwise = Nothing
275 toI16 _ _ = Just narrowed
279 -- @spRel@ gives us a stack relative addressing mode for volatile
280 -- temporaries and for excess call arguments. @fpRel@, where
281 -- applicable, is the same but for the frame pointer.
283 spRel :: Int -- desired stack offset in words, positive or negative
287 #if defined(i386_TARGET_ARCH)
288 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
289 #elif defined(x86_64_TARGET_ARCH)
290 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
292 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
295 #if sparc_TARGET_ARCH
296 fpRel :: Int -> AddrMode
297 -- Duznae work for offsets greater than 13 bits; we just hope for
300 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
303 #if x86_64_TARGET_ARCH
304 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
307 -- -----------------------------------------------------------------------------
310 -- We map STG registers onto appropriate CmmExprs. Either they map
311 -- to real machine registers or stored as offsets from BaseReg. Given
312 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
313 -- register it is in, on this platform, or a StixExpr denoting the
314 -- address in the register table holding it. get_MagicId_addr always
315 -- produces the register table address for it.
317 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
318 get_GlobalReg_addr :: GlobalReg -> CmmExpr
319 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
321 get_GlobalReg_reg_or_addr mid
322 = case globalRegMaybe mid of
324 Nothing -> Right (get_GlobalReg_addr mid)
326 get_GlobalReg_addr BaseReg = regTableOffset 0
327 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
328 (globalRegRep mid) (baseRegOffset mid)
330 -- Calculate a literal representing an offset into the register table.
331 -- Used when we don't have an actual BaseReg to offset from.
333 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
335 get_Regtable_addr_from_offset rep offset
336 = case globalRegMaybe BaseReg of
337 Nothing -> regTableOffset offset
338 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
340 -- -----------------------------------------------------------------------------
341 -- caller-save registers
343 -- Here we generate the sequence of saves/restores required around a
344 -- foreign call instruction.
346 -- TODO: reconcile with includes/Regs.h
347 -- * Regs.h claims that BaseReg should be saved last and loaded first
348 -- * This might not have been tickled before since BaseReg is callee save
349 -- * Regs.h saves SparkHd, ParkT1, SparkBase and SparkLim
350 callerSaveVolatileRegs :: Maybe [GlobalReg] -> ([CmmStmt], [CmmStmt])
351 callerSaveVolatileRegs vols = (caller_save, caller_load)
353 caller_save = foldr ($!) [] (map callerSaveGlobalReg regs_to_save)
354 caller_load = foldr ($!) [] (map callerRestoreGlobalReg regs_to_save)
356 system_regs = [Sp,SpLim,Hp,HpLim,CurrentTSO,CurrentNursery,
357 {-SparkHd,SparkTl,SparkBase,SparkLim,-}BaseReg ]
359 regs_to_save = system_regs ++ vol_list
361 vol_list = case vols of Nothing -> all_of_em; Just regs -> regs
363 all_of_em = [ VanillaReg n | n <- [0..mAX_Vanilla_REG] ]
364 ++ [ FloatReg n | n <- [0..mAX_Float_REG] ]
365 ++ [ DoubleReg n | n <- [0..mAX_Double_REG] ]
366 ++ [ LongReg n | n <- [0..mAX_Long_REG] ]
368 callerSaveGlobalReg reg next
370 CmmStore (get_GlobalReg_addr reg)
371 (CmmReg (CmmGlobal reg)) : next
374 callerRestoreGlobalReg reg next
376 CmmAssign (CmmGlobal reg)
377 (CmmLoad (get_GlobalReg_addr reg) (globalRegRep reg))
382 -- ---------------------------------------------------------------------------
385 -- RealRegs are machine regs which are available for allocation, in
386 -- the usual way. We know what class they are, because that's part of
387 -- the processor's architecture.
389 -- VirtualRegs are virtual registers. The register allocator will
390 -- eventually have to map them into RealRegs, or into spill slots.
391 -- VirtualRegs are allocated on the fly, usually to represent a single
392 -- value in the abstract assembly code (i.e. dynamic registers are
393 -- usually single assignment). With the new register allocator, the
394 -- single assignment restriction isn't necessary to get correct code,
395 -- although a better register allocation will result if single
396 -- assignment is used -- because the allocator maps a VirtualReg into
397 -- a single RealReg, even if the VirtualReg has multiple live ranges.
399 -- Virtual regs can be of either class, so that info is attached.
401 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
402 -- when supplied with the vreg for the lower-half of the quantity.
403 -- (NB. Not reversible).
404 getHiVRegFromLo (VirtualRegI u)
405 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
406 getHiVRegFromLo other
407 = pprPanic "getHiVRegFromLo" (ppr other)
418 = RealReg {-# UNPACK #-} !RegNo
419 | VirtualRegI {-# UNPACK #-} !Unique
420 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
421 | VirtualRegF {-# UNPACK #-} !Unique
422 | VirtualRegD {-# UNPACK #-} !Unique
425 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
426 -- in the register allocator.
427 instance Uniquable Reg where
428 getUnique (RealReg i) = mkUnique 'C' i
429 getUnique (VirtualRegI u) = u
430 getUnique (VirtualRegHi u) = u
431 getUnique (VirtualRegF u) = u
432 getUnique (VirtualRegD u) = u
434 unRealReg (RealReg i) = i
435 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
437 mkVReg :: Unique -> MachRep -> Reg
440 #if sparc_TARGET_ARCH
446 other -> VirtualRegI u
448 isVirtualReg :: Reg -> Bool
449 isVirtualReg (RealReg _) = False
450 isVirtualReg (VirtualRegI _) = True
451 isVirtualReg (VirtualRegHi _) = True
452 isVirtualReg (VirtualRegF _) = True
453 isVirtualReg (VirtualRegD _) = True
455 isRealReg :: Reg -> Bool
456 isRealReg = not . isVirtualReg
458 instance Show Reg where
459 show (RealReg i) = showReg i
460 show (VirtualRegI u) = "%vI_" ++ show u
461 show (VirtualRegHi u) = "%vHi_" ++ show u
462 show (VirtualRegF u) = "%vF_" ++ show u
463 show (VirtualRegD u) = "%vD_" ++ show u
465 instance Outputable Reg where
466 ppr r = Outputable.text (show r)
469 -- -----------------------------------------------------------------------------
470 -- Machine-specific register stuff
472 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
473 -- point registers. The mapping of STG registers to alpha machine registers
474 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
476 #if alpha_TARGET_ARCH
480 v0, f0, ra, pv, gp, sp, zeroh :: Reg
482 f0 = realReg (fReg 0)
483 ra = FixedReg ILIT(26)
485 gp = FixedReg ILIT(29)
486 sp = FixedReg ILIT(30)
487 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
489 t9, t10, t11, t12 :: Reg
497 Intel x86 architecture:
498 - All registers except 7 (esp) are available for use.
499 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
500 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
501 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
502 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
503 fp registers, and 3-operand insns for them, and we translate this into
504 real stack-based x86 fp code after register allocation.
506 The fp registers are all Double registers; we don't have any RcFloat class
507 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
513 fake0, fake1, fake2, fake3, fake4, fake5,
514 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
530 -- On x86, we might want to have an 8-bit RegClass, which would
531 -- contain just regs 1-4 (the others don't have 8-bit versions).
532 -- However, we can get away without this at the moment because the
533 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
534 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
535 regClass (VirtualRegI u) = RcInteger
536 regClass (VirtualRegHi u) = RcInteger
537 regClass (VirtualRegD u) = RcDouble
538 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
539 (ppr (VirtualRegF u))
542 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
543 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
545 showReg :: RegNo -> String
547 = if n >= 0 && n < 14
549 else "%unknown_x86_real_reg_" ++ show n
554 AMD x86_64 architecture:
555 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
556 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
557 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
561 #if x86_64_TARGET_ARCH
563 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
564 r8, r9, r10, r11, r12, r13, r14, r15,
565 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
566 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
601 -- so we can re-use some x86 code:
611 xmm n = RealReg (16+n)
613 -- On x86, we might want to have an 8-bit RegClass, which would
614 -- contain just regs 1-4 (the others don't have 8-bit versions).
615 -- However, we can get away without this at the moment because the
616 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
617 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
618 regClass (VirtualRegI u) = RcInteger
619 regClass (VirtualRegHi u) = RcInteger
620 regClass (VirtualRegD u) = RcDouble
621 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
622 (ppr (VirtualRegF u))
625 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
627 showReg :: RegNo -> String
629 | n >= 16 = "%xmm" ++ show (n-16)
630 | n >= 8 = "%r" ++ show n
631 | otherwise = regNames !! n
636 The SPARC has 64 registers of interest; 32 integer registers and 32
637 floating point registers. The mapping of STG registers to SPARC
638 machine registers is defined in StgRegs.h. We are, of course,
639 prepared for any eventuality.
641 The whole fp-register pairing thing on sparcs is a huge nuisance. See
642 fptools/ghc/includes/MachRegs.h for a description of what's going on
646 #if sparc_TARGET_ARCH
648 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
655 nCG_FirstFloatReg :: RegNo
656 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
658 regClass (VirtualRegI u) = RcInteger
659 regClass (VirtualRegF u) = RcFloat
660 regClass (VirtualRegD u) = RcDouble
661 regClass (RealReg i) | i < 32 = RcInteger
662 | i < nCG_FirstFloatReg = RcDouble
663 | otherwise = RcFloat
665 showReg :: RegNo -> String
667 | n >= 0 && n < 8 = "%g" ++ show n
668 | n >= 8 && n < 16 = "%o" ++ show (n-8)
669 | n >= 16 && n < 24 = "%l" ++ show (n-16)
670 | n >= 24 && n < 32 = "%i" ++ show (n-24)
671 | n >= 32 && n < 64 = "%f" ++ show (n-32)
672 | otherwise = "%unknown_sparc_real_reg_" ++ show n
674 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
676 f6 = RealReg (fReg 6)
677 f8 = RealReg (fReg 8)
678 f22 = RealReg (fReg 22)
679 f26 = RealReg (fReg 26)
680 f27 = RealReg (fReg 27)
683 -- g0 is useful for codegen; is always zero, and writes to it vanish.
684 g0 = RealReg (gReg 0)
685 g1 = RealReg (gReg 1)
686 g2 = RealReg (gReg 2)
688 -- FP, SP, int and float return (from C) regs.
689 fp = RealReg (iReg 6)
690 sp = RealReg (oReg 6)
691 o0 = RealReg (oReg 0)
692 o1 = RealReg (oReg 1)
693 f0 = RealReg (fReg 0)
694 f1 = RealReg (fReg 1)
699 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
703 #if powerpc_TARGET_ARCH
707 regClass (VirtualRegI u) = RcInteger
708 regClass (VirtualRegHi u) = RcInteger
709 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
710 (ppr (VirtualRegF u))
711 regClass (VirtualRegD u) = RcDouble
712 regClass (RealReg i) | i < 32 = RcInteger
713 | otherwise = RcDouble
715 showReg :: RegNo -> String
717 | n >= 0 && n <= 31 = "%r" ++ show n
718 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
719 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
726 f1 = RealReg $ fReg 1
727 f20 = RealReg $ fReg 20
728 f21 = RealReg $ fReg 21
732 Redefine the literals used for machine-registers with non-numeric
733 names in the header files. Gag me with a spoon, eh?
736 #if alpha_TARGET_ARCH
787 #if x86_64_TARGET_ARCH
822 #if sparc_TARGET_ARCH
890 #if powerpc_TARGET_ARCH
924 #ifdef darwin_TARGET_OS
994 -- allMachRegs is the complete set of machine regs.
995 allMachRegNos :: [RegNo]
997 = IF_ARCH_alpha( [0..63],
998 IF_ARCH_i386( [0..13],
999 IF_ARCH_x86_64( [0..31],
1000 IF_ARCH_sparc( ([0..31]
1001 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1002 ++ [nCG_FirstFloatReg .. f31]),
1003 IF_ARCH_powerpc([0..63],
1006 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1007 -- i.e., these are the regs for which we are prepared to allow the
1008 -- register allocator to attempt to map VRegs to.
1009 allocatableRegs :: [RegNo]
1011 = let isFree i = isFastTrue (freeReg i)
1012 in filter isFree allMachRegNos
1014 -- these are the regs which we cannot assume stay alive over a
1016 callClobberedRegs :: [Reg]
1019 #if alpha_TARGET_ARCH
1020 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1021 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1022 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1023 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1024 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1025 #endif /* alpha_TARGET_ARCH */
1026 #if i386_TARGET_ARCH
1027 -- caller-saves registers
1028 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1029 #endif /* i386_TARGET_ARCH */
1030 #if x86_64_TARGET_ARCH
1031 -- caller-saves registers
1032 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1033 -- all xmm regs are caller-saves
1034 #endif /* x86_64_TARGET_ARCH */
1035 #if sparc_TARGET_ARCH
1038 [oReg i | i <- [0..5]] ++
1039 [gReg i | i <- [1..7]] ++
1040 [fReg i | i <- [0..31]] )
1041 #endif /* sparc_TARGET_ARCH */
1042 #if powerpc_TARGET_ARCH
1043 #if darwin_TARGET_OS
1044 map RealReg (0:[2..12] ++ map fReg [0..13])
1045 #elif linux_TARGET_OS
1046 map RealReg (0:[2..13] ++ map fReg [0..13])
1048 #endif /* powerpc_TARGET_ARCH */
1051 -- argRegs is the set of regs which are read for an n-argument call to C.
1052 -- For archs which pass all args on the stack (x86), is empty.
1053 -- Sparc passes up to the first 6 args in regs.
1054 -- Dunno about Alpha.
1055 argRegs :: RegNo -> [Reg]
1057 #if i386_TARGET_ARCH
1058 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1061 #if x86_64_TARGET_ARCH
1062 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1065 #if alpha_TARGET_ARCH
1067 argRegs 1 = freeMappedRegs [16, fReg 16]
1068 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1069 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1070 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1071 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1072 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1073 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1074 #endif /* alpha_TARGET_ARCH */
1076 #if sparc_TARGET_ARCH
1078 argRegs 1 = map (RealReg . oReg) [0]
1079 argRegs 2 = map (RealReg . oReg) [0,1]
1080 argRegs 3 = map (RealReg . oReg) [0,1,2]
1081 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1082 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1083 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1084 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1085 #endif /* sparc_TARGET_ARCH */
1087 #if powerpc_TARGET_ARCH
1089 argRegs 1 = map RealReg [3]
1090 argRegs 2 = map RealReg [3,4]
1091 argRegs 3 = map RealReg [3..5]
1092 argRegs 4 = map RealReg [3..6]
1093 argRegs 5 = map RealReg [3..7]
1094 argRegs 6 = map RealReg [3..8]
1095 argRegs 7 = map RealReg [3..9]
1096 argRegs 8 = map RealReg [3..10]
1097 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1098 #endif /* powerpc_TARGET_ARCH */
1101 -- all of the arg regs ??
1102 #if alpha_TARGET_ARCH
1103 allArgRegs :: [(Reg, Reg)]
1104 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1105 #endif /* alpha_TARGET_ARCH */
1107 #if sparc_TARGET_ARCH
1109 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1110 #endif /* sparc_TARGET_ARCH */
1112 #if i386_TARGET_ARCH
1114 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1117 #if x86_64_TARGET_ARCH
1119 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1120 allFPArgRegs :: [Reg]
1121 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1124 #if powerpc_TARGET_ARCH
1126 allArgRegs = map RealReg [3..10]
1127 allFPArgRegs :: [Reg]
1128 #if darwin_TARGET_OS
1129 allFPArgRegs = map (RealReg . fReg) [1..13]
1130 #elif linux_TARGET_OS
1131 allFPArgRegs = map (RealReg . fReg) [1..8]
1133 #endif /* powerpc_TARGET_ARCH */
1137 freeReg :: RegNo -> FastBool
1139 #if alpha_TARGET_ARCH
1140 freeReg 26 = fastBool False -- return address (ra)
1141 freeReg 28 = fastBool False -- reserved for the assembler (at)
1142 freeReg 29 = fastBool False -- global pointer (gp)
1143 freeReg 30 = fastBool False -- stack pointer (sp)
1144 freeReg 31 = fastBool False -- always zero (zeroh)
1145 freeReg 63 = fastBool False -- always zero (f31)
1148 #if i386_TARGET_ARCH
1149 freeReg esp = fastBool False -- %esp is the C stack pointer
1152 #if x86_64_TARGET_ARCH
1153 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1156 #if sparc_TARGET_ARCH
1157 freeReg g0 = fastBool False -- %g0 is always 0.
1158 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1159 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1160 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1161 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1162 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1163 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1164 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1165 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1166 freeReg f1 = fastBool False
1169 #if powerpc_TARGET_ARCH
1170 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1171 freeReg 1 = fastBool False -- The Stack Pointer
1172 #if !darwin_TARGET_OS
1173 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1174 freeReg 2 = fastBool False
1179 freeReg REG_Base = fastBool False
1182 freeReg REG_R1 = fastBool False
1185 freeReg REG_R2 = fastBool False
1188 freeReg REG_R3 = fastBool False
1191 freeReg REG_R4 = fastBool False
1194 freeReg REG_R5 = fastBool False
1197 freeReg REG_R6 = fastBool False
1200 freeReg REG_R7 = fastBool False
1203 freeReg REG_R8 = fastBool False
1206 freeReg REG_F1 = fastBool False
1209 freeReg REG_F2 = fastBool False
1212 freeReg REG_F3 = fastBool False
1215 freeReg REG_F4 = fastBool False
1218 freeReg REG_D1 = fastBool False
1221 freeReg REG_D2 = fastBool False
1224 freeReg REG_Sp = fastBool False
1227 freeReg REG_Su = fastBool False
1230 freeReg REG_SpLim = fastBool False
1233 freeReg REG_Hp = fastBool False
1236 freeReg REG_HpLim = fastBool False
1238 freeReg n = fastBool True
1241 -- -----------------------------------------------------------------------------
1242 -- Information about global registers
1244 baseRegOffset :: GlobalReg -> Int
1246 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1247 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1248 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1249 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1250 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1251 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1252 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1253 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1254 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1255 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1256 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1257 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1258 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1259 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1260 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1261 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1262 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1263 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1264 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1265 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1266 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1267 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1268 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1269 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1270 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1271 baseRegOffset GCFun = oFFSET_stgGCFun
1273 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1274 baseRegOffset _ = panic "baseRegOffset:other"
1278 -- | Returns 'True' if this global register is stored in a caller-saves
1279 -- machine register.
1281 callerSaves :: GlobalReg -> Bool
1283 #ifdef CALLER_SAVES_Base
1284 callerSaves BaseReg = True
1286 #ifdef CALLER_SAVES_R1
1287 callerSaves (VanillaReg 1) = True
1289 #ifdef CALLER_SAVES_R2
1290 callerSaves (VanillaReg 2) = True
1292 #ifdef CALLER_SAVES_R3
1293 callerSaves (VanillaReg 3) = True
1295 #ifdef CALLER_SAVES_R4
1296 callerSaves (VanillaReg 4) = True
1298 #ifdef CALLER_SAVES_R5
1299 callerSaves (VanillaReg 5) = True
1301 #ifdef CALLER_SAVES_R6
1302 callerSaves (VanillaReg 6) = True
1304 #ifdef CALLER_SAVES_R7
1305 callerSaves (VanillaReg 7) = True
1307 #ifdef CALLER_SAVES_R8
1308 callerSaves (VanillaReg 8) = True
1310 #ifdef CALLER_SAVES_F1
1311 callerSaves (FloatReg 1) = True
1313 #ifdef CALLER_SAVES_F2
1314 callerSaves (FloatReg 2) = True
1316 #ifdef CALLER_SAVES_F3
1317 callerSaves (FloatReg 3) = True
1319 #ifdef CALLER_SAVES_F4
1320 callerSaves (FloatReg 4) = True
1322 #ifdef CALLER_SAVES_D1
1323 callerSaves (DoubleReg 1) = True
1325 #ifdef CALLER_SAVES_D2
1326 callerSaves (DoubleReg 2) = True
1328 #ifdef CALLER_SAVES_L1
1329 callerSaves (LongReg 1) = True
1331 #ifdef CALLER_SAVES_Sp
1332 callerSaves Sp = True
1334 #ifdef CALLER_SAVES_SpLim
1335 callerSaves SpLim = True
1337 #ifdef CALLER_SAVES_Hp
1338 callerSaves Hp = True
1340 #ifdef CALLER_SAVES_HpLim
1341 callerSaves HpLim = True
1343 #ifdef CALLER_SAVES_CurrentTSO
1344 callerSaves CurrentTSO = True
1346 #ifdef CALLER_SAVES_CurrentNursery
1347 callerSaves CurrentNursery = True
1349 callerSaves _ = False
1352 -- | Returns 'Nothing' if this global register is not stored
1353 -- in a real machine register, otherwise returns @'Just' reg@, where
1354 -- reg is the machine register it is stored in.
1356 globalRegMaybe :: GlobalReg -> Maybe Reg
1359 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1362 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1365 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1368 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1371 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1374 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1377 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1380 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1383 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1386 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1389 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1392 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1395 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1398 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1401 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1404 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1407 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1410 globalRegMaybe Sp = Just (RealReg REG_Sp)
1413 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1416 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1419 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1422 globalRegMaybe Hp = Just (RealReg REG_Hp)
1425 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1427 #ifdef REG_CurrentTSO
1428 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1430 #ifdef REG_CurrentNursery
1431 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1433 globalRegMaybe _ = Nothing