1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
36 callerSaves, callerSaveVolatileRegs,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 EABase(..), EAIndex(..),
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 EABase(..), EAIndex(..), ripRel,
56 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 r8, r9, r10, r11, r12, r13, r14, r15,
59 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
60 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
62 addrModeRegs, allFPArgRegs,
66 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
67 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
69 #if powerpc_TARGET_ARCH
78 #include "HsVersions.h"
81 # define STOLEN_X86_REGS 4
82 -- HACK: go for the max
85 #include "../includes/MachRegs.h"
88 import MachOp ( MachRep(..) )
90 import CLabel ( CLabel, mkMainCapabilityLabel )
92 import Outputable ( Outputable(..), pprPanic, panic )
93 import qualified Outputable
98 #if powerpc_TARGET_ARCH
99 import Data.Word ( Word8, Word16, Word32 )
100 import Data.Int ( Int8, Int16, Int32 )
103 -- -----------------------------------------------------------------------------
108 | ImmInteger Integer -- Sigh.
109 | ImmCLbl CLabel -- AbstractC Label (with baggage)
110 | ImmLit Doc -- Simple string
111 | ImmIndex CLabel Int
114 | ImmConstantSum Imm Imm
115 | ImmConstantDiff Imm Imm
116 #if sparc_TARGET_ARCH
117 | LO Imm {- Possible restrictions... -}
120 #if powerpc_TARGET_ARCH
123 | HA Imm {- high halfword adjusted -}
125 strImmLit s = ImmLit (text s)
127 litToImm :: CmmLit -> Imm
128 litToImm (CmmInt i _) = ImmInteger i
129 litToImm (CmmFloat f F32) = ImmFloat f
130 litToImm (CmmFloat f F64) = ImmDouble f
131 litToImm (CmmLabel l) = ImmCLbl l
132 litToImm (CmmLabelOff l off) = ImmIndex l off
133 litToImm (CmmLabelDiffOff l1 l2 off)
135 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
138 -- -----------------------------------------------------------------------------
142 #if alpha_TARGET_ARCH
148 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
149 = AddrBaseIndex EABase EAIndex Displacement
152 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
153 data EAIndex = EAIndexNone | EAIndex Reg Int
154 type Displacement = Imm
157 #if sparc_TARGET_ARCH
162 #if powerpc_TARGET_ARCH
167 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
168 addrModeRegs :: AddrMode -> [Reg]
169 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
171 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
172 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
177 addrOffset :: AddrMode -> Int -> Maybe AddrMode
181 #if alpha_TARGET_ARCH
182 _ -> panic "MachMisc.addrOffset not defined for Alpha"
184 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
185 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
187 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
188 AddrBaseIndex r i (ImmInteger n)
189 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
191 AddrBaseIndex r i (ImmCLbl lbl)
192 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
194 AddrBaseIndex r i (ImmIndex lbl ix)
195 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
197 _ -> Nothing -- in theory, shouldn't happen
199 #if sparc_TARGET_ARCH
200 AddrRegImm r (ImmInt n)
201 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
202 | otherwise -> Nothing
205 AddrRegImm r (ImmInteger n)
206 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
207 | otherwise -> Nothing
208 where n2 = n + toInteger off
210 AddrRegReg r (RealReg 0)
211 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
212 | otherwise -> Nothing
216 #if powerpc_TARGET_ARCH
217 AddrRegImm r (ImmInt n)
218 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
219 | otherwise -> Nothing
222 AddrRegImm r (ImmInteger n)
223 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
224 | otherwise -> Nothing
225 where n2 = n + toInteger off
231 #if alpha_TARGET_ARCH
233 fits8Bits :: Integer -> Bool
234 fits8Bits i = i >= -256 && i < 256
238 #if sparc_TARGET_ARCH
240 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
241 fits13Bits :: Integral a => a -> Bool
242 fits13Bits x = x >= -4096 && x < 4096
246 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
247 ++show i++");\nprobably because of large constant data structures;" ++
248 "\nworkaround: use -fvia-C on this module.\n")
252 #if powerpc_TARGET_ARCH
253 fits16Bits :: Integral a => a -> Bool
254 fits16Bits x = x >= -32768 && x < 32768
256 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
258 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
260 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
261 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
262 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
263 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
264 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
265 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
267 narrowed = narrow rep signed
270 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
271 | otherwise = Nothing
273 | narrowed >= 0 && narrowed < 65536 = Just narrowed
274 | otherwise = Nothing
275 toI16 _ _ = Just narrowed
279 -- @spRel@ gives us a stack relative addressing mode for volatile
280 -- temporaries and for excess call arguments. @fpRel@, where
281 -- applicable, is the same but for the frame pointer.
283 spRel :: Int -- desired stack offset in words, positive or negative
287 #if defined(i386_TARGET_ARCH)
288 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
289 #elif defined(x86_64_TARGET_ARCH)
290 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
292 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
295 #if sparc_TARGET_ARCH
296 fpRel :: Int -> AddrMode
297 -- Duznae work for offsets greater than 13 bits; we just hope for
300 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
303 #if x86_64_TARGET_ARCH
304 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
307 -- -----------------------------------------------------------------------------
310 -- We map STG registers onto appropriate CmmExprs. Either they map
311 -- to real machine registers or stored as offsets from BaseReg. Given
312 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
313 -- register it is in, on this platform, or a StixExpr denoting the
314 -- address in the register table holding it. get_MagicId_addr always
315 -- produces the register table address for it.
317 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
318 get_GlobalReg_addr :: GlobalReg -> CmmExpr
319 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
321 get_GlobalReg_reg_or_addr mid
322 = case globalRegMaybe mid of
324 Nothing -> Right (get_GlobalReg_addr mid)
326 get_GlobalReg_addr BaseReg = regTableOffset 0
327 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
328 (globalRegRep mid) (baseRegOffset mid)
330 -- Calculate a literal representing an offset into the register table.
331 -- Used when we don't have an actual BaseReg to offset from.
333 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
335 get_Regtable_addr_from_offset rep offset
336 = case globalRegMaybe BaseReg of
337 Nothing -> regTableOffset offset
338 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
340 -- -----------------------------------------------------------------------------
341 -- caller-save registers
343 -- Here we generate the sequence of saves/restores required around a
344 -- foreign call instruction.
346 callerSaveVolatileRegs :: Maybe [GlobalReg] -> ([CmmStmt], [CmmStmt])
347 callerSaveVolatileRegs vols = (caller_save, caller_load)
349 caller_save = foldr ($!) [] (map callerSaveGlobalReg regs_to_save)
350 caller_load = foldr ($!) [] (map callerRestoreGlobalReg regs_to_save)
352 system_regs = [Sp,SpLim,Hp,HpLim,CurrentTSO,CurrentNursery,
353 {-SparkHd,SparkTl,SparkBase,SparkLim,-}BaseReg ]
355 regs_to_save = system_regs ++ vol_list
357 vol_list = case vols of Nothing -> all_of_em; Just regs -> regs
359 all_of_em = [ VanillaReg n | n <- [0..mAX_Vanilla_REG] ]
360 ++ [ FloatReg n | n <- [0..mAX_Float_REG] ]
361 ++ [ DoubleReg n | n <- [0..mAX_Double_REG] ]
362 ++ [ LongReg n | n <- [0..mAX_Long_REG] ]
364 callerSaveGlobalReg reg next
366 CmmStore (get_GlobalReg_addr reg)
367 (CmmReg (CmmGlobal reg)) : next
370 callerRestoreGlobalReg reg next
372 CmmAssign (CmmGlobal reg)
373 (CmmLoad (get_GlobalReg_addr reg) (globalRegRep reg))
378 -- ---------------------------------------------------------------------------
381 -- RealRegs are machine regs which are available for allocation, in
382 -- the usual way. We know what class they are, because that's part of
383 -- the processor's architecture.
385 -- VirtualRegs are virtual registers. The register allocator will
386 -- eventually have to map them into RealRegs, or into spill slots.
387 -- VirtualRegs are allocated on the fly, usually to represent a single
388 -- value in the abstract assembly code (i.e. dynamic registers are
389 -- usually single assignment). With the new register allocator, the
390 -- single assignment restriction isn't necessary to get correct code,
391 -- although a better register allocation will result if single
392 -- assignment is used -- because the allocator maps a VirtualReg into
393 -- a single RealReg, even if the VirtualReg has multiple live ranges.
395 -- Virtual regs can be of either class, so that info is attached.
397 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
398 -- when supplied with the vreg for the lower-half of the quantity.
399 -- (NB. Not reversible).
400 getHiVRegFromLo (VirtualRegI u)
401 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
402 getHiVRegFromLo other
403 = pprPanic "getHiVRegFromLo" (ppr other)
414 = RealReg {-# UNPACK #-} !RegNo
415 | VirtualRegI {-# UNPACK #-} !Unique
416 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
417 | VirtualRegF {-# UNPACK #-} !Unique
418 | VirtualRegD {-# UNPACK #-} !Unique
421 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
422 -- in the register allocator.
423 instance Uniquable Reg where
424 getUnique (RealReg i) = mkUnique 'C' i
425 getUnique (VirtualRegI u) = u
426 getUnique (VirtualRegHi u) = u
427 getUnique (VirtualRegF u) = u
428 getUnique (VirtualRegD u) = u
430 unRealReg (RealReg i) = i
431 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
433 mkVReg :: Unique -> MachRep -> Reg
436 #if sparc_TARGET_ARCH
442 other -> VirtualRegI u
444 isVirtualReg :: Reg -> Bool
445 isVirtualReg (RealReg _) = False
446 isVirtualReg (VirtualRegI _) = True
447 isVirtualReg (VirtualRegHi _) = True
448 isVirtualReg (VirtualRegF _) = True
449 isVirtualReg (VirtualRegD _) = True
451 isRealReg :: Reg -> Bool
452 isRealReg = not . isVirtualReg
454 instance Show Reg where
455 show (RealReg i) = showReg i
456 show (VirtualRegI u) = "%vI_" ++ show u
457 show (VirtualRegHi u) = "%vHi_" ++ show u
458 show (VirtualRegF u) = "%vF_" ++ show u
459 show (VirtualRegD u) = "%vD_" ++ show u
461 instance Outputable Reg where
462 ppr r = Outputable.text (show r)
465 -- -----------------------------------------------------------------------------
466 -- Machine-specific register stuff
468 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
469 -- point registers. The mapping of STG registers to alpha machine registers
470 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
472 #if alpha_TARGET_ARCH
476 v0, f0, ra, pv, gp, sp, zeroh :: Reg
478 f0 = realReg (fReg 0)
479 ra = FixedReg ILIT(26)
481 gp = FixedReg ILIT(29)
482 sp = FixedReg ILIT(30)
483 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
485 t9, t10, t11, t12 :: Reg
493 Intel x86 architecture:
494 - All registers except 7 (esp) are available for use.
495 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
496 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
497 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
498 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
499 fp registers, and 3-operand insns for them, and we translate this into
500 real stack-based x86 fp code after register allocation.
502 The fp registers are all Double registers; we don't have any RcFloat class
503 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
509 fake0, fake1, fake2, fake3, fake4, fake5,
510 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
526 -- On x86, we might want to have an 8-bit RegClass, which would
527 -- contain just regs 1-4 (the others don't have 8-bit versions).
528 -- However, we can get away without this at the moment because the
529 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
530 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
531 regClass (VirtualRegI u) = RcInteger
532 regClass (VirtualRegHi u) = RcInteger
533 regClass (VirtualRegD u) = RcDouble
534 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
535 (ppr (VirtualRegF u))
538 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
539 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
541 showReg :: RegNo -> String
543 = if n >= 0 && n < 14
545 else "%unknown_x86_real_reg_" ++ show n
550 AMD x86_64 architecture:
551 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
552 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
553 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
557 #if x86_64_TARGET_ARCH
559 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
560 r8, r9, r10, r11, r12, r13, r14, r15,
561 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
562 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
597 -- so we can re-use some x86 code:
607 xmm n = RealReg (16+n)
609 -- On x86, we might want to have an 8-bit RegClass, which would
610 -- contain just regs 1-4 (the others don't have 8-bit versions).
611 -- However, we can get away without this at the moment because the
612 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
613 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
614 regClass (VirtualRegI u) = RcInteger
615 regClass (VirtualRegHi u) = RcInteger
616 regClass (VirtualRegD u) = RcDouble
617 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
618 (ppr (VirtualRegF u))
621 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
623 showReg :: RegNo -> String
625 | n >= 16 = "%xmm" ++ show (n-16)
626 | n >= 8 = "%r" ++ show n
627 | otherwise = regNames !! n
632 The SPARC has 64 registers of interest; 32 integer registers and 32
633 floating point registers. The mapping of STG registers to SPARC
634 machine registers is defined in StgRegs.h. We are, of course,
635 prepared for any eventuality.
637 The whole fp-register pairing thing on sparcs is a huge nuisance. See
638 fptools/ghc/includes/MachRegs.h for a description of what's going on
642 #if sparc_TARGET_ARCH
644 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
651 nCG_FirstFloatReg :: RegNo
652 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
654 regClass (VirtualRegI u) = RcInteger
655 regClass (VirtualRegF u) = RcFloat
656 regClass (VirtualRegD u) = RcDouble
657 regClass (RealReg i) | i < 32 = RcInteger
658 | i < nCG_FirstFloatReg = RcDouble
659 | otherwise = RcFloat
661 showReg :: RegNo -> String
663 | n >= 0 && n < 8 = "%g" ++ show n
664 | n >= 8 && n < 16 = "%o" ++ show (n-8)
665 | n >= 16 && n < 24 = "%l" ++ show (n-16)
666 | n >= 24 && n < 32 = "%i" ++ show (n-24)
667 | n >= 32 && n < 64 = "%f" ++ show (n-32)
668 | otherwise = "%unknown_sparc_real_reg_" ++ show n
670 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
672 f6 = RealReg (fReg 6)
673 f8 = RealReg (fReg 8)
674 f22 = RealReg (fReg 22)
675 f26 = RealReg (fReg 26)
676 f27 = RealReg (fReg 27)
679 -- g0 is useful for codegen; is always zero, and writes to it vanish.
680 g0 = RealReg (gReg 0)
681 g1 = RealReg (gReg 1)
682 g2 = RealReg (gReg 2)
684 -- FP, SP, int and float return (from C) regs.
685 fp = RealReg (iReg 6)
686 sp = RealReg (oReg 6)
687 o0 = RealReg (oReg 0)
688 o1 = RealReg (oReg 1)
689 f0 = RealReg (fReg 0)
690 f1 = RealReg (fReg 1)
695 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
699 #if powerpc_TARGET_ARCH
703 regClass (VirtualRegI u) = RcInteger
704 regClass (VirtualRegHi u) = RcInteger
705 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
706 (ppr (VirtualRegF u))
707 regClass (VirtualRegD u) = RcDouble
708 regClass (RealReg i) | i < 32 = RcInteger
709 | otherwise = RcDouble
711 showReg :: RegNo -> String
713 | n >= 0 && n <= 31 = "%r" ++ show n
714 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
715 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
722 f1 = RealReg $ fReg 1
723 f20 = RealReg $ fReg 20
724 f21 = RealReg $ fReg 21
728 Redefine the literals used for machine-registers with non-numeric
729 names in the header files. Gag me with a spoon, eh?
732 #if alpha_TARGET_ARCH
783 #if x86_64_TARGET_ARCH
818 #if sparc_TARGET_ARCH
886 #if powerpc_TARGET_ARCH
920 #ifdef darwin_TARGET_OS
990 -- allMachRegs is the complete set of machine regs.
991 allMachRegNos :: [RegNo]
993 = IF_ARCH_alpha( [0..63],
994 IF_ARCH_i386( [0..13],
995 IF_ARCH_x86_64( [0..31],
996 IF_ARCH_sparc( ([0..31]
997 ++ [f0,f2 .. nCG_FirstFloatReg-1]
998 ++ [nCG_FirstFloatReg .. f31]),
999 IF_ARCH_powerpc([0..63],
1002 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1003 -- i.e., these are the regs for which we are prepared to allow the
1004 -- register allocator to attempt to map VRegs to.
1005 allocatableRegs :: [RegNo]
1007 = let isFree i = isFastTrue (freeReg i)
1008 in filter isFree allMachRegNos
1010 -- these are the regs which we cannot assume stay alive over a
1012 callClobberedRegs :: [Reg]
1015 #if alpha_TARGET_ARCH
1016 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1017 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1018 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1019 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1020 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1021 #endif /* alpha_TARGET_ARCH */
1022 #if i386_TARGET_ARCH
1023 -- caller-saves registers
1024 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1025 #endif /* i386_TARGET_ARCH */
1026 #if x86_64_TARGET_ARCH
1027 -- caller-saves registers
1028 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1029 -- all xmm regs are caller-saves
1030 #endif /* x86_64_TARGET_ARCH */
1031 #if sparc_TARGET_ARCH
1034 [oReg i | i <- [0..5]] ++
1035 [gReg i | i <- [1..7]] ++
1036 [fReg i | i <- [0..31]] )
1037 #endif /* sparc_TARGET_ARCH */
1038 #if powerpc_TARGET_ARCH
1039 #if darwin_TARGET_OS
1040 map RealReg (0:[2..12] ++ map fReg [0..13])
1041 #elif linux_TARGET_OS
1042 map RealReg (0:[2..13] ++ map fReg [0..13])
1044 #endif /* powerpc_TARGET_ARCH */
1047 -- argRegs is the set of regs which are read for an n-argument call to C.
1048 -- For archs which pass all args on the stack (x86), is empty.
1049 -- Sparc passes up to the first 6 args in regs.
1050 -- Dunno about Alpha.
1051 argRegs :: RegNo -> [Reg]
1053 #if i386_TARGET_ARCH
1054 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1057 #if x86_64_TARGET_ARCH
1058 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1061 #if alpha_TARGET_ARCH
1063 argRegs 1 = freeMappedRegs [16, fReg 16]
1064 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1065 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1066 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1067 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1068 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1069 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1070 #endif /* alpha_TARGET_ARCH */
1072 #if sparc_TARGET_ARCH
1074 argRegs 1 = map (RealReg . oReg) [0]
1075 argRegs 2 = map (RealReg . oReg) [0,1]
1076 argRegs 3 = map (RealReg . oReg) [0,1,2]
1077 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1078 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1079 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1080 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1081 #endif /* sparc_TARGET_ARCH */
1083 #if powerpc_TARGET_ARCH
1085 argRegs 1 = map RealReg [3]
1086 argRegs 2 = map RealReg [3,4]
1087 argRegs 3 = map RealReg [3..5]
1088 argRegs 4 = map RealReg [3..6]
1089 argRegs 5 = map RealReg [3..7]
1090 argRegs 6 = map RealReg [3..8]
1091 argRegs 7 = map RealReg [3..9]
1092 argRegs 8 = map RealReg [3..10]
1093 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1094 #endif /* powerpc_TARGET_ARCH */
1097 -- all of the arg regs ??
1098 #if alpha_TARGET_ARCH
1099 allArgRegs :: [(Reg, Reg)]
1100 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1101 #endif /* alpha_TARGET_ARCH */
1103 #if sparc_TARGET_ARCH
1105 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1106 #endif /* sparc_TARGET_ARCH */
1108 #if i386_TARGET_ARCH
1110 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1113 #if x86_64_TARGET_ARCH
1115 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1116 allFPArgRegs :: [Reg]
1117 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1120 #if powerpc_TARGET_ARCH
1122 allArgRegs = map RealReg [3..10]
1123 allFPArgRegs :: [Reg]
1124 #if darwin_TARGET_OS
1125 allFPArgRegs = map (RealReg . fReg) [1..13]
1126 #elif linux_TARGET_OS
1127 allFPArgRegs = map (RealReg . fReg) [1..8]
1129 #endif /* powerpc_TARGET_ARCH */
1133 freeReg :: RegNo -> FastBool
1135 #if alpha_TARGET_ARCH
1136 freeReg 26 = fastBool False -- return address (ra)
1137 freeReg 28 = fastBool False -- reserved for the assembler (at)
1138 freeReg 29 = fastBool False -- global pointer (gp)
1139 freeReg 30 = fastBool False -- stack pointer (sp)
1140 freeReg 31 = fastBool False -- always zero (zeroh)
1141 freeReg 63 = fastBool False -- always zero (f31)
1144 #if i386_TARGET_ARCH
1145 freeReg esp = fastBool False -- %esp is the C stack pointer
1148 #if x86_64_TARGET_ARCH
1149 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1152 #if sparc_TARGET_ARCH
1153 freeReg g0 = fastBool False -- %g0 is always 0.
1154 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1155 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1156 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1157 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1158 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1159 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1160 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1161 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1162 freeReg f1 = fastBool False
1165 #if powerpc_TARGET_ARCH
1166 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1167 freeReg 1 = fastBool False -- The Stack Pointer
1168 #if !darwin_TARGET_OS
1169 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1170 freeReg 2 = fastBool False
1175 freeReg REG_Base = fastBool False
1178 freeReg REG_R1 = fastBool False
1181 freeReg REG_R2 = fastBool False
1184 freeReg REG_R3 = fastBool False
1187 freeReg REG_R4 = fastBool False
1190 freeReg REG_R5 = fastBool False
1193 freeReg REG_R6 = fastBool False
1196 freeReg REG_R7 = fastBool False
1199 freeReg REG_R8 = fastBool False
1202 freeReg REG_F1 = fastBool False
1205 freeReg REG_F2 = fastBool False
1208 freeReg REG_F3 = fastBool False
1211 freeReg REG_F4 = fastBool False
1214 freeReg REG_D1 = fastBool False
1217 freeReg REG_D2 = fastBool False
1220 freeReg REG_Sp = fastBool False
1223 freeReg REG_Su = fastBool False
1226 freeReg REG_SpLim = fastBool False
1229 freeReg REG_Hp = fastBool False
1232 freeReg REG_HpLim = fastBool False
1234 freeReg n = fastBool True
1237 -- -----------------------------------------------------------------------------
1238 -- Information about global registers
1240 baseRegOffset :: GlobalReg -> Int
1242 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1243 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1244 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1245 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1246 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1247 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1248 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1249 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1250 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1251 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1252 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1253 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1254 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1255 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1256 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1257 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1258 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1259 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1260 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1261 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1262 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1263 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1264 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1265 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1266 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1267 baseRegOffset GCFun = oFFSET_stgGCFun
1269 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1270 baseRegOffset _ = panic "baseRegOffset:other"
1274 -- | Returns 'True' if this global register is stored in a caller-saves
1275 -- machine register.
1277 callerSaves :: GlobalReg -> Bool
1279 #ifdef CALLER_SAVES_Base
1280 callerSaves BaseReg = True
1282 #ifdef CALLER_SAVES_R1
1283 callerSaves (VanillaReg 1) = True
1285 #ifdef CALLER_SAVES_R2
1286 callerSaves (VanillaReg 2) = True
1288 #ifdef CALLER_SAVES_R3
1289 callerSaves (VanillaReg 3) = True
1291 #ifdef CALLER_SAVES_R4
1292 callerSaves (VanillaReg 4) = True
1294 #ifdef CALLER_SAVES_R5
1295 callerSaves (VanillaReg 5) = True
1297 #ifdef CALLER_SAVES_R6
1298 callerSaves (VanillaReg 6) = True
1300 #ifdef CALLER_SAVES_R7
1301 callerSaves (VanillaReg 7) = True
1303 #ifdef CALLER_SAVES_R8
1304 callerSaves (VanillaReg 8) = True
1306 #ifdef CALLER_SAVES_F1
1307 callerSaves (FloatReg 1) = True
1309 #ifdef CALLER_SAVES_F2
1310 callerSaves (FloatReg 2) = True
1312 #ifdef CALLER_SAVES_F3
1313 callerSaves (FloatReg 3) = True
1315 #ifdef CALLER_SAVES_F4
1316 callerSaves (FloatReg 4) = True
1318 #ifdef CALLER_SAVES_D1
1319 callerSaves (DoubleReg 1) = True
1321 #ifdef CALLER_SAVES_D2
1322 callerSaves (DoubleReg 2) = True
1324 #ifdef CALLER_SAVES_L1
1325 callerSaves (LongReg 1) = True
1327 #ifdef CALLER_SAVES_Sp
1328 callerSaves Sp = True
1330 #ifdef CALLER_SAVES_SpLim
1331 callerSaves SpLim = True
1333 #ifdef CALLER_SAVES_Hp
1334 callerSaves Hp = True
1336 #ifdef CALLER_SAVES_HpLim
1337 callerSaves HpLim = True
1339 #ifdef CALLER_SAVES_CurrentTSO
1340 callerSaves CurrentTSO = True
1342 #ifdef CALLER_SAVES_CurrentNursery
1343 callerSaves CurrentNursery = True
1345 callerSaves _ = False
1348 -- | Returns 'Nothing' if this global register is not stored
1349 -- in a real machine register, otherwise returns @'Just' reg@, where
1350 -- reg is the machine register it is stored in.
1352 globalRegMaybe :: GlobalReg -> Maybe Reg
1355 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1358 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1361 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1364 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1367 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1370 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1373 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1376 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1379 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1382 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1385 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1388 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1391 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1394 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1397 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1400 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1403 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1406 globalRegMaybe Sp = Just (RealReg REG_Sp)
1409 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1412 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1415 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1418 globalRegMaybe Hp = Just (RealReg REG_Hp)
1421 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1423 #ifdef REG_CurrentTSO
1424 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1426 #ifdef REG_CurrentNursery
1427 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1429 globalRegMaybe _ = Nothing