1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Size(..), intSize, floatSize, isFloatSize,
29 wordSize, cmmTypeSize, sizeToWidth,
32 Imm(..), strImmLit, litToImm,
40 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
41 RegClass(..), regClass,
47 get_GlobalReg_reg_or_addr,
49 -- * Machine-dependent register-related stuff
50 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
51 allocatableRegsInClass,
58 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
61 EABase(..), EAIndex(..),
62 eax, ebx, ecx, edx, esi, edi, ebp, esp,
63 fake0, fake1, fake2, fake3, fake4, fake5,
66 #if x86_64_TARGET_ARCH
67 EABase(..), EAIndex(..), ripRel,
68 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
69 eax, ebx, ecx, edx, esi, edi, ebp, esp,
70 r8, r9, r10, r11, r12, r13, r14, r15,
71 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
72 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
74 addrModeRegs, allFPArgRegs,
78 fpRel, gReg, iReg, lReg, oReg, fReg, largeOffsetError,
79 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
81 #if powerpc_TARGET_ARCH
90 #include "HsVersions.h"
93 # define STOLEN_X86_REGS 4
94 -- HACK: go for the max
97 #include "../includes/MachRegs.h"
101 import CgUtils ( get_GlobalReg_addr )
102 import CLabel ( CLabel, mkMainCapabilityLabel )
104 import Outputable ( Outputable(..), pprPanic, panic )
105 import qualified Outputable
113 #if powerpc_TARGET_ARCH
114 import Data.Word ( Word8, Word16, Word32 )
115 import Data.Int ( Int8, Int16, Int32 )
118 -- -----------------------------------------------------------------------------
119 -- Sizes on this architecture
121 -- A Size is usually a combination of width and class
123 -- It looks very like the old MachRep, but it's now of purely local
124 -- significance, here in the native code generator. You can change it
125 -- without global consequences.
127 -- A major use is as an opcode qualifier; thus the opcode
131 -- where the Size field encodes the ".l" part.
133 -- ToDo: it's not clear to me that we need separate signed-vs-unsigned sizes
134 -- here. I've removed them from the x86 version, we'll see what happens --SDM
136 -- ToDo: quite a few occurrences of Size could usefully be replaced by Width
138 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
139 data Size -- For these three, the "size" also gives the int/float
140 -- distinction, because the instructions for int/float
141 -- differ only in their suffices
142 = II8 | II16 | II32 | II64 | FF32 | FF64 | FF80
145 intSize, floatSize :: Width -> Size
150 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
154 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
157 wordSize = intSize wordWidth
159 sizeToWidth :: Size -> Width
161 sizeToWidth II16 = W16
162 sizeToWidth II32 = W32
163 sizeToWidth II64 = W64
164 sizeToWidth FF32 = W32
165 sizeToWidth FF64 = W64
166 sizeToWidth _ = panic "MachInstrs.sizeToWidth"
168 cmmTypeSize :: CmmType -> Size
169 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
170 | otherwise = intSize (typeWidth ty)
172 isFloatSize :: Size -> Bool
173 isFloatSize FF32 = True
174 isFloatSize FF64 = True
175 isFloatSize FF80 = True
176 isFloatSize other = False
179 #if alpha_TARGET_ARCH
183 -- | W -- word (2 bytes): UNUSED
185 | L -- longword (4 bytes)
186 | Q -- quadword (8 bytes)
187 -- | FF -- VAX F-style floating pt: UNUSED
188 -- | GF -- VAX G-style floating pt: UNUSED
189 -- | DF -- VAX D-style floating pt: UNUSED
190 -- | SF -- IEEE single-precision floating pt: UNUSED
191 | TF -- IEEE double-precision floating pt
195 #if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
197 = II8 -- byte (signed)
198 -- | II8u -- byte (unsigned)
199 | II16 -- halfword (signed, 2 bytes)
200 -- | II16u -- halfword (unsigned, 2 bytes)
201 | II32 -- word (4 bytes)
202 | II64 -- word (8 bytes)
203 | FF32 -- IEEE single-precision floating pt
204 | FF64 -- IEEE single-precision floating pt
208 intSize, floatSize :: Width -> Size
210 --intSize W16 = II16u
214 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
218 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
221 wordSize = intSize wordWidth
223 isFloatSize :: Size -> Bool
224 isFloatSize FF32 = True
225 isFloatSize FF64 = True
226 isFloatSize _ = False
228 cmmTypeSize :: CmmType -> Size
229 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
230 | otherwise = intSize (typeWidth ty)
232 sizeToWidth :: Size -> Width
247 -- -----------------------------------------------------------------------------
252 | ImmInteger Integer -- Sigh.
253 | ImmCLbl CLabel -- AbstractC Label (with baggage)
254 | ImmLit Doc -- Simple string
255 | ImmIndex CLabel Int
258 | ImmConstantSum Imm Imm
259 | ImmConstantDiff Imm Imm
260 #if sparc_TARGET_ARCH
261 | LO Imm {- Possible restrictions... -}
264 #if powerpc_TARGET_ARCH
267 | HA Imm {- high halfword adjusted -}
269 strImmLit s = ImmLit (text s)
271 litToImm :: CmmLit -> Imm
272 litToImm (CmmInt i w) = ImmInteger (narrowS w i)
273 -- narrow to the width: a CmmInt might be out of
274 -- range, but we assume that ImmInteger only contains
275 -- in-range values. A signed value should be fine here.
276 litToImm (CmmFloat f W32) = ImmFloat f
277 litToImm (CmmFloat f W64) = ImmDouble f
278 litToImm (CmmLabel l) = ImmCLbl l
279 litToImm (CmmLabelOff l off) = ImmIndex l off
280 litToImm (CmmLabelDiffOff l1 l2 off)
282 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
284 litToImm (CmmBlock id) = ImmCLbl (infoTblLbl id)
286 -- -----------------------------------------------------------------------------
290 #if alpha_TARGET_ARCH
296 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
297 = AddrBaseIndex EABase EAIndex Displacement
300 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
301 data EAIndex = EAIndexNone | EAIndex Reg Int
302 type Displacement = Imm
305 #if sparc_TARGET_ARCH
310 #if powerpc_TARGET_ARCH
315 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
316 addrModeRegs :: AddrMode -> [Reg]
317 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
319 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
320 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
325 addrOffset :: AddrMode -> Int -> Maybe AddrMode
329 #if alpha_TARGET_ARCH
330 _ -> panic "MachMisc.addrOffset not defined for Alpha"
332 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
333 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
335 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
336 AddrBaseIndex r i (ImmInteger n)
337 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
339 AddrBaseIndex r i (ImmCLbl lbl)
340 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
342 AddrBaseIndex r i (ImmIndex lbl ix)
343 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
345 _ -> Nothing -- in theory, shouldn't happen
347 #if sparc_TARGET_ARCH
348 AddrRegImm r (ImmInt n)
349 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
350 | otherwise -> Nothing
353 AddrRegImm r (ImmInteger n)
354 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
355 | otherwise -> Nothing
356 where n2 = n + toInteger off
358 AddrRegReg r (RealReg 0)
359 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
360 | otherwise -> Nothing
364 #if powerpc_TARGET_ARCH
365 AddrRegImm r (ImmInt n)
366 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
367 | otherwise -> Nothing
370 AddrRegImm r (ImmInteger n)
371 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
372 | otherwise -> Nothing
373 where n2 = n + toInteger off
379 #if alpha_TARGET_ARCH
381 fits8Bits :: Integer -> Bool
382 fits8Bits i = i >= -256 && i < 256
386 #if sparc_TARGET_ARCH
388 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
389 fits13Bits :: Integral a => a -> Bool
390 fits13Bits x = x >= -4096 && x < 4096
394 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
395 ++show i++");\nprobably because of large constant data structures;" ++
396 "\nworkaround: use -fvia-C on this module.\n")
400 #if powerpc_TARGET_ARCH
401 fits16Bits :: Integral a => a -> Bool
402 fits16Bits x = x >= -32768 && x < 32768
404 makeImmediate :: Integral a => Width -> Bool -> a -> Maybe Imm
405 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
407 narrow W32 False = fromIntegral (fromIntegral x :: Word32)
408 narrow W16 False = fromIntegral (fromIntegral x :: Word16)
409 narrow W8 False = fromIntegral (fromIntegral x :: Word8)
410 narrow W32 True = fromIntegral (fromIntegral x :: Int32)
411 narrow W16 True = fromIntegral (fromIntegral x :: Int16)
412 narrow W8 True = fromIntegral (fromIntegral x :: Int8)
414 narrowed = narrow rep signed
417 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
418 | otherwise = Nothing
420 | narrowed >= 0 && narrowed < 65536 = Just narrowed
421 | otherwise = Nothing
422 toI16 _ _ = Just narrowed
426 -- @spRel@ gives us a stack relative addressing mode for volatile
427 -- temporaries and for excess call arguments. @fpRel@, where
428 -- applicable, is the same but for the frame pointer.
430 spRel :: Int -- desired stack offset in words, positive or negative
434 #if defined(i386_TARGET_ARCH)
435 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
436 #elif defined(x86_64_TARGET_ARCH)
437 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
439 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
442 #if sparc_TARGET_ARCH
443 fpRel :: Int -> AddrMode
444 -- Duznae work for offsets greater than 13 bits; we just hope for
447 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
450 #if x86_64_TARGET_ARCH
451 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
454 -- -----------------------------------------------------------------------------
457 -- We map STG registers onto appropriate CmmExprs. Either they map
458 -- to real machine registers or stored as offsets from BaseReg. Given
459 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
460 -- register it is in, on this platform, or a CmmExpr denoting the
461 -- address in the register table holding it.
462 -- (See also get_GlobalReg_addr in CgUtils.)
464 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
465 get_GlobalReg_reg_or_addr mid
466 = case globalRegMaybe mid of
468 Nothing -> Right (get_GlobalReg_addr mid)
470 -- ---------------------------------------------------------------------------
473 -- RealRegs are machine regs which are available for allocation, in
474 -- the usual way. We know what class they are, because that's part of
475 -- the processor's architecture.
477 -- VirtualRegs are virtual registers. The register allocator will
478 -- eventually have to map them into RealRegs, or into spill slots.
479 -- VirtualRegs are allocated on the fly, usually to represent a single
480 -- value in the abstract assembly code (i.e. dynamic registers are
481 -- usually single assignment). With the new register allocator, the
482 -- single assignment restriction isn't necessary to get correct code,
483 -- although a better register allocation will result if single
484 -- assignment is used -- because the allocator maps a VirtualReg into
485 -- a single RealReg, even if the VirtualReg has multiple live ranges.
487 -- Virtual regs can be of either class, so that info is attached.
489 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
490 -- when supplied with the vreg for the lower-half of the quantity.
491 -- (NB. Not reversible).
492 getHiVRegFromLo (VirtualRegI u)
493 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
494 getHiVRegFromLo other
495 = pprPanic "getHiVRegFromLo" (ppr other)
503 instance Uniquable RegClass where
504 getUnique RcInteger = mkUnique 'L' 0
505 getUnique RcFloat = mkUnique 'L' 1
506 getUnique RcDouble = mkUnique 'L' 2
511 = RealReg {-# UNPACK #-} !RegNo
512 | VirtualRegI {-# UNPACK #-} !Unique
513 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
514 | VirtualRegF {-# UNPACK #-} !Unique
515 | VirtualRegD {-# UNPACK #-} !Unique
518 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
519 -- in the register allocator.
520 instance Uniquable Reg where
521 getUnique (RealReg i) = mkUnique 'C' i
522 getUnique (VirtualRegI u) = u
523 getUnique (VirtualRegHi u) = u
524 getUnique (VirtualRegF u) = u
525 getUnique (VirtualRegD u) = u
527 unRealReg (RealReg i) = i
528 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
530 mkVReg :: Unique -> Size -> Reg
532 | not (isFloatSize size) = VirtualRegI u
535 #if sparc_TARGET_ARCH
536 FF32 -> VirtualRegF u
537 FF64 -> VirtualRegD u
539 FF32 -> VirtualRegD u
540 FF64 -> VirtualRegD u
542 _other -> panic "mkVReg"
544 isVirtualReg :: Reg -> Bool
545 isVirtualReg (RealReg _) = False
546 isVirtualReg (VirtualRegI _) = True
547 isVirtualReg (VirtualRegHi _) = True
548 isVirtualReg (VirtualRegF _) = True
549 isVirtualReg (VirtualRegD _) = True
551 isRealReg :: Reg -> Bool
552 isRealReg = not . isVirtualReg
554 renameVirtualReg :: Unique -> Reg -> Reg
557 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
558 VirtualRegI _ -> VirtualRegI u
559 VirtualRegHi _ -> VirtualRegHi u
560 VirtualRegF _ -> VirtualRegF u
561 VirtualRegD _ -> VirtualRegD u
563 instance Show Reg where
564 show (RealReg i) = showReg i
565 show (VirtualRegI u) = "%vI_" ++ show u
566 show (VirtualRegHi u) = "%vHi_" ++ show u
567 show (VirtualRegF u) = "%vF_" ++ show u
568 show (VirtualRegD u) = "%vD_" ++ show u
570 instance Outputable RegClass where
571 ppr RcInteger = Outputable.text "I"
572 ppr RcFloat = Outputable.text "F"
573 ppr RcDouble = Outputable.text "D"
575 instance Outputable Reg where
576 ppr r = Outputable.text (show r)
581 -- trivColorable function for the graph coloring allocator
582 -- This gets hammered by scanGraph during register allocation,
583 -- so needs to be fairly efficient.
585 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
586 -- (which are disjoint) ie. x86, x86_64 and ppc
590 -- Doing a nice fold over the UniqSet makes trivColorable use
591 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
593 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
594 trivColorable classN conflicts exclusions
597 acc :: Reg -> (Int, Int) -> (Int, Int)
600 RcInteger -> (cd+1, cf)
601 RcDouble -> (cd, cf+1)
602 _ -> panic "MachRegs.trivColorable: reg class not handled"
604 tmp = foldUniqSet acc (0, 0) conflicts
605 (countInt, countFloat) = foldUniqSet acc tmp exclusions
607 squeese = worst countInt classN RcInteger
608 + worst countFloat classN RcDouble
610 in squeese < allocatableRegsInClass classN
612 -- | Worst case displacement
613 -- node N of classN has n neighbors of class C.
615 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
616 -- This is a bit boring compared to what's in RegArchX86.
618 worst :: Int -> RegClass -> RegClass -> Int
619 worst n classN classC
623 RcInteger -> min n (allocatableRegsInClass RcInteger)
628 RcDouble -> min n (allocatableRegsInClass RcDouble)
633 -- The number of allocatable regs is hard coded here so we can do a fast comparision
634 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
635 -- free regs, but they can't be more or the register conflict graph won't color.
637 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
638 -- is too slow for us here.
640 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
643 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
644 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
646 #elif x86_64_TARGET_ARCH
647 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
648 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
650 #elif powerpc_TARGET_ARCH
651 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
652 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
654 #elif sparc_TARGET_ARCH
655 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
656 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
659 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
662 {-# INLINE regClass #-}
663 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
664 trivColorable classN conflicts exclusions
665 = {-# SCC "trivColorable" #-}
669 NodeUFM _ _ left right
670 -> case isSqueesed cI cF right of
673 False -> isSqueesed cI' cF' left
674 True -> (# True, cI', cF' #)
677 -> case regClass reg of
679 -> case cI +# _ILIT(1) of
680 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
683 -> case cF +# _ILIT(1) of
684 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
687 -> (# False, cI, cF #)
689 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
690 (# False, cI', cF' #)
691 -> case isSqueesed cI' cF' exclusions of
692 (# s, _, _ #) -> not s
699 -- -----------------------------------------------------------------------------
700 -- Machine-specific register stuff
702 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
703 -- point registers. The mapping of STG registers to alpha machine registers
704 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
706 #if alpha_TARGET_ARCH
710 v0, f0, ra, pv, gp, sp, zeroh :: Reg
712 f0 = realReg (fReg 0)
713 ra = FixedReg ILIT(26)
715 gp = FixedReg ILIT(29)
716 sp = FixedReg ILIT(30)
717 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
719 t9, t10, t11, t12 :: Reg
727 Intel x86 architecture:
728 - All registers except 7 (esp) are available for use.
729 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
730 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
731 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
732 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
733 fp registers, and 3-operand insns for them, and we translate this into
734 real stack-based x86 fp code after register allocation.
736 The fp registers are all Double registers; we don't have any RcFloat class
737 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
743 fake0, fake1, fake2, fake3, fake4, fake5,
744 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
761 -- On x86, we might want to have an 8-bit RegClass, which would
762 -- contain just regs 1-4 (the others don't have 8-bit versions).
763 -- However, we can get away without this at the moment because the
764 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
765 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
766 regClass (VirtualRegI u) = RcInteger
767 regClass (VirtualRegHi u) = RcInteger
768 regClass (VirtualRegD u) = RcDouble
769 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
770 (ppr (VirtualRegF u))
773 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
774 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
776 showReg :: RegNo -> String
778 = if n >= 0 && n < 14
780 else "%unknown_x86_real_reg_" ++ show n
786 AMD x86_64 architecture:
787 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
788 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
789 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
793 #if x86_64_TARGET_ARCH
795 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
796 r8, r9, r10, r11, r12, r13, r14, r15,
797 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
798 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
833 -- so we can re-use some x86 code:
843 xmm n = RealReg (16+n)
845 -- On x86, we might want to have an 8-bit RegClass, which would
846 -- contain just regs 1-4 (the others don't have 8-bit versions).
847 -- However, we can get away without this at the moment because the
848 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
849 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
850 regClass (VirtualRegI u) = RcInteger
851 regClass (VirtualRegHi u) = RcInteger
852 regClass (VirtualRegD u) = RcDouble
853 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
854 (ppr (VirtualRegF u))
857 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
859 showReg :: RegNo -> String
861 | n >= 16 = "%xmm" ++ show (n-16)
862 | n >= 8 = "%r" ++ show n
863 | otherwise = regNames !! n
868 The SPARC has 64 registers of interest; 32 integer registers and 32
869 floating point registers. The mapping of STG registers to SPARC
870 machine registers is defined in StgRegs.h. We are, of course,
871 prepared for any eventuality.
873 The whole fp-register pairing thing on sparcs is a huge nuisance. See
874 fptools/ghc/includes/MachRegs.h for a description of what's going on
878 #if sparc_TARGET_ARCH
880 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
887 nCG_FirstFloatReg :: RegNo
888 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
890 regClass (VirtualRegI u) = RcInteger
891 regClass (VirtualRegHi u) = RcInteger
892 regClass (VirtualRegF u) = RcFloat
893 regClass (VirtualRegD u) = RcDouble
894 regClass (RealReg i) | i < 32 = RcInteger
895 | i < nCG_FirstFloatReg = RcDouble
896 | otherwise = RcFloat
898 showReg :: RegNo -> String
900 | n >= 0 && n < 8 = "%g" ++ show n
901 | n >= 8 && n < 16 = "%o" ++ show (n-8)
902 | n >= 16 && n < 24 = "%l" ++ show (n-16)
903 | n >= 24 && n < 32 = "%i" ++ show (n-24)
904 | n >= 32 && n < 64 = "%f" ++ show (n-32)
905 | otherwise = "%unknown_sparc_real_reg_" ++ show n
907 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
909 f6 = RealReg (fReg 6)
910 f8 = RealReg (fReg 8)
911 f22 = RealReg (fReg 22)
912 f26 = RealReg (fReg 26)
913 f27 = RealReg (fReg 27)
916 -- g0 is useful for codegen; is always zero, and writes to it vanish.
917 g0 = RealReg (gReg 0)
918 g1 = RealReg (gReg 1)
919 g2 = RealReg (gReg 2)
921 -- FP, SP, int and float return (from C) regs.
922 fp = RealReg (iReg 6)
923 sp = RealReg (oReg 6)
924 o0 = RealReg (oReg 0)
925 o1 = RealReg (oReg 1)
926 f0 = RealReg (fReg 0)
927 f1 = RealReg (fReg 1)
932 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
936 #if powerpc_TARGET_ARCH
940 regClass (VirtualRegI u) = RcInteger
941 regClass (VirtualRegHi u) = RcInteger
942 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
943 (ppr (VirtualRegF u))
944 regClass (VirtualRegD u) = RcDouble
945 regClass (RealReg i) | i < 32 = RcInteger
946 | otherwise = RcDouble
948 showReg :: RegNo -> String
950 | n >= 0 && n <= 31 = "%r" ++ show n
951 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
952 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
959 f1 = RealReg $ fReg 1
960 f20 = RealReg $ fReg 20
961 f21 = RealReg $ fReg 21
965 Redefine the literals used for machine-registers with non-numeric
966 names in the header files. Gag me with a spoon, eh?
969 #if alpha_TARGET_ARCH
1003 #if i386_TARGET_ARCH
1020 #if x86_64_TARGET_ARCH
1055 #if sparc_TARGET_ARCH
1123 #if powerpc_TARGET_ARCH
1157 #ifdef darwin_TARGET_OS
1227 -- allMachRegs is the complete set of machine regs.
1228 allMachRegNos :: [RegNo]
1230 = IF_ARCH_alpha( [0..63],
1231 IF_ARCH_i386( [0..13],
1232 IF_ARCH_x86_64( [0..31],
1233 IF_ARCH_sparc( ([0..31]
1234 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1235 ++ [nCG_FirstFloatReg .. f31]),
1236 IF_ARCH_powerpc([0..63],
1239 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1240 -- i.e., these are the regs for which we are prepared to allow the
1241 -- register allocator to attempt to map VRegs to.
1242 allocatableRegs :: [RegNo]
1244 = let isFree i = isFastTrue (freeReg i)
1245 in filter isFree allMachRegNos
1248 -- | The number of regs in each class.
1249 -- We go via top level CAFs to ensure that we're not recomputing
1250 -- the length of these lists each time the fn is called.
1251 allocatableRegsInClass :: RegClass -> Int
1252 allocatableRegsInClass cls
1254 RcInteger -> allocatableRegsInteger
1255 RcDouble -> allocatableRegsDouble
1257 allocatableRegsInteger
1258 = length $ filter (\r -> regClass r == RcInteger)
1259 $ map RealReg allocatableRegs
1261 allocatableRegsDouble
1262 = length $ filter (\r -> regClass r == RcDouble)
1263 $ map RealReg allocatableRegs
1266 -- these are the regs which we cannot assume stay alive over a
1268 callClobberedRegs :: [Reg]
1271 #if alpha_TARGET_ARCH
1272 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1273 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1274 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1275 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1276 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1277 #endif /* alpha_TARGET_ARCH */
1278 #if i386_TARGET_ARCH
1279 -- caller-saves registers
1280 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1281 #endif /* i386_TARGET_ARCH */
1282 #if x86_64_TARGET_ARCH
1283 -- caller-saves registers
1284 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1285 -- all xmm regs are caller-saves
1286 #endif /* x86_64_TARGET_ARCH */
1287 #if sparc_TARGET_ARCH
1290 [oReg i | i <- [0..5]] ++
1291 [gReg i | i <- [1..7]] ++
1292 [fReg i | i <- [0..31]] )
1293 #endif /* sparc_TARGET_ARCH */
1294 #if powerpc_TARGET_ARCH
1295 #if darwin_TARGET_OS
1296 map RealReg (0:[2..12] ++ map fReg [0..13])
1297 #elif linux_TARGET_OS
1298 map RealReg (0:[2..13] ++ map fReg [0..13])
1300 #endif /* powerpc_TARGET_ARCH */
1303 -- argRegs is the set of regs which are read for an n-argument call to C.
1304 -- For archs which pass all args on the stack (x86), is empty.
1305 -- Sparc passes up to the first 6 args in regs.
1306 -- Dunno about Alpha.
1307 argRegs :: RegNo -> [Reg]
1309 #if i386_TARGET_ARCH
1310 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1313 #if x86_64_TARGET_ARCH
1314 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1317 #if alpha_TARGET_ARCH
1319 argRegs 1 = freeMappedRegs [16, fReg 16]
1320 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1321 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1322 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1323 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1324 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1325 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1326 #endif /* alpha_TARGET_ARCH */
1328 #if sparc_TARGET_ARCH
1330 argRegs 1 = map (RealReg . oReg) [0]
1331 argRegs 2 = map (RealReg . oReg) [0,1]
1332 argRegs 3 = map (RealReg . oReg) [0,1,2]
1333 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1334 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1335 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1336 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1337 #endif /* sparc_TARGET_ARCH */
1339 #if powerpc_TARGET_ARCH
1341 argRegs 1 = map RealReg [3]
1342 argRegs 2 = map RealReg [3,4]
1343 argRegs 3 = map RealReg [3..5]
1344 argRegs 4 = map RealReg [3..6]
1345 argRegs 5 = map RealReg [3..7]
1346 argRegs 6 = map RealReg [3..8]
1347 argRegs 7 = map RealReg [3..9]
1348 argRegs 8 = map RealReg [3..10]
1349 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1350 #endif /* powerpc_TARGET_ARCH */
1353 -- all of the arg regs ??
1354 #if alpha_TARGET_ARCH
1355 allArgRegs :: [(Reg, Reg)]
1356 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1357 #endif /* alpha_TARGET_ARCH */
1359 #if sparc_TARGET_ARCH
1361 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1362 #endif /* sparc_TARGET_ARCH */
1364 #if i386_TARGET_ARCH
1366 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1369 #if x86_64_TARGET_ARCH
1371 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1372 allFPArgRegs :: [Reg]
1373 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1376 #if powerpc_TARGET_ARCH
1378 allArgRegs = map RealReg [3..10]
1379 allFPArgRegs :: [Reg]
1380 #if darwin_TARGET_OS
1381 allFPArgRegs = map (RealReg . fReg) [1..13]
1382 #elif linux_TARGET_OS
1383 allFPArgRegs = map (RealReg . fReg) [1..8]
1385 #endif /* powerpc_TARGET_ARCH */
1389 freeReg :: RegNo -> FastBool
1391 #if alpha_TARGET_ARCH
1392 freeReg 26 = fastBool False -- return address (ra)
1393 freeReg 28 = fastBool False -- reserved for the assembler (at)
1394 freeReg 29 = fastBool False -- global pointer (gp)
1395 freeReg 30 = fastBool False -- stack pointer (sp)
1396 freeReg 31 = fastBool False -- always zero (zeroh)
1397 freeReg 63 = fastBool False -- always zero (f31)
1400 #if i386_TARGET_ARCH
1401 freeReg esp = fastBool False -- %esp is the C stack pointer
1404 #if x86_64_TARGET_ARCH
1405 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1408 #if sparc_TARGET_ARCH
1409 freeReg g0 = fastBool False -- %g0 is always 0.
1411 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1412 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1413 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1414 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1415 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1416 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1417 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1418 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1419 freeReg f1 = fastBool False
1421 -- TODO: Not sure about these BL 2009/01/10
1422 -- Used for NCG spill tmps? what is this?
1425 freeReg g1 = fastBool False -- %g1 is used for NCG spill tmp
1426 freeReg g2 = fastBool False
1427 freeReg f6 = fastBool False
1428 freeReg f8 = fastBool False
1429 freeReg f26 = fastBool False
1430 freeReg f27 = fastBool False
1435 #if powerpc_TARGET_ARCH
1436 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1437 freeReg 1 = fastBool False -- The Stack Pointer
1438 #if !darwin_TARGET_OS
1439 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1440 freeReg 2 = fastBool False
1445 freeReg REG_Base = fastBool False
1448 freeReg REG_R1 = fastBool False
1451 freeReg REG_R2 = fastBool False
1454 freeReg REG_R3 = fastBool False
1457 freeReg REG_R4 = fastBool False
1460 freeReg REG_R5 = fastBool False
1463 freeReg REG_R6 = fastBool False
1466 freeReg REG_R7 = fastBool False
1469 freeReg REG_R8 = fastBool False
1472 freeReg REG_F1 = fastBool False
1475 freeReg REG_F2 = fastBool False
1478 freeReg REG_F3 = fastBool False
1481 freeReg REG_F4 = fastBool False
1484 freeReg REG_D1 = fastBool False
1487 freeReg REG_D2 = fastBool False
1490 freeReg REG_Sp = fastBool False
1493 freeReg REG_Su = fastBool False
1496 freeReg REG_SpLim = fastBool False
1499 freeReg REG_Hp = fastBool False
1502 freeReg REG_HpLim = fastBool False
1504 freeReg n = fastBool True
1507 -- | Returns 'Nothing' if this global register is not stored
1508 -- in a real machine register, otherwise returns @'Just' reg@, where
1509 -- reg is the machine register it is stored in.
1511 globalRegMaybe :: GlobalReg -> Maybe Reg
1514 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1517 globalRegMaybe (VanillaReg 1 _) = Just (RealReg REG_R1)
1520 globalRegMaybe (VanillaReg 2 _) = Just (RealReg REG_R2)
1523 globalRegMaybe (VanillaReg 3 _) = Just (RealReg REG_R3)
1526 globalRegMaybe (VanillaReg 4 _) = Just (RealReg REG_R4)
1529 globalRegMaybe (VanillaReg 5 _) = Just (RealReg REG_R5)
1532 globalRegMaybe (VanillaReg 6 _) = Just (RealReg REG_R6)
1535 globalRegMaybe (VanillaReg 7 _) = Just (RealReg REG_R7)
1538 globalRegMaybe (VanillaReg 8 _) = Just (RealReg REG_R8)
1541 globalRegMaybe (VanillaReg 9 _) = Just (RealReg REG_R9)
1544 globalRegMaybe (VanillaReg 10 _) = Just (RealReg REG_R10)
1547 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1550 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1553 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1556 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1559 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1562 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1565 globalRegMaybe Sp = Just (RealReg REG_Sp)
1568 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1571 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1574 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1577 globalRegMaybe Hp = Just (RealReg REG_Hp)
1580 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1582 #ifdef REG_CurrentTSO
1583 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1585 #ifdef REG_CurrentNursery
1586 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1588 globalRegMaybe _ = Nothing