1 -----------------------------------------------------------------------------
3 -- Machine-dependent assembly language
5 -- (c) The University of Glasgow 1993-2004
7 -----------------------------------------------------------------------------
9 #include "HsVersions.h"
10 #include "nativeGen/NCG.h"
44 condNegate :: Cond -> Cond
45 condNegate ALWAYS = panic "condNegate: ALWAYS"
58 -- -----------------------------------------------------------------------------
59 -- Machine's assembly language
61 -- We have a few common "instructions" (nearly all the pseudo-ops) but
62 -- mostly all of 'Instr' is machine-specific.
64 -- Register or immediate
73 -- some static data spat out during code
74 -- generation. Will be extracted before
76 | LDATA Section [CmmStatic]
78 -- start a new basic block. Useful during
79 -- codegen, removed later. Preceding
80 -- instruction should be a jump, as per the
81 -- invariants for a BasicBlock (see Cmm).
84 -- specify current stack offset for
85 -- benefit of subsequent passes
88 -- | spill this reg to a stack slot
91 -- | reload this reg from a stack slot
95 | LD Size Reg AddrMode -- Load size, dst, src
96 | LA Size Reg AddrMode -- Load arithmetic size, dst, src
97 | ST Size Reg AddrMode -- Store size, src, dst
98 | STU Size Reg AddrMode -- Store with Update size, src, dst
99 | LIS Reg Imm -- Load Immediate Shifted dst, src
100 | LI Reg Imm -- Load Immediate dst, src
101 | MR Reg Reg -- Move Register dst, src -- also for fmr
103 | CMP Size Reg RI --- size, src1, src2
104 | CMPL Size Reg RI --- size, src1, src2
107 | BCCFAR Cond BlockId
108 | JMP CLabel -- same as branch,
109 -- but with CLabel instead of block ID
111 | BCTR [BlockId] -- with list of local destinations
112 | BL CLabel [Reg] -- with list of argument regs
115 | ADD Reg Reg RI -- dst, src1, src2
116 | ADDC Reg Reg Reg -- (carrying) dst, src1, src2
117 | ADDE Reg Reg Reg -- (extend) dst, src1, src2
118 | ADDIS Reg Reg Imm -- Add Immediate Shifted dst, src1, src2
119 | SUBF Reg Reg Reg -- dst, src1, src2 ; dst = src2 - src1
124 | MULLW_MayOflo Reg Reg Reg
125 -- dst = 1 if src1 * src2 overflows
126 -- pseudo-instruction; pretty-printed as:
127 -- mullwo. dst, src1, src2
129 -- rlwinm dst, dst, 2, 31,31
131 | AND Reg Reg RI -- dst, src1, src2
132 | OR Reg Reg RI -- dst, src1, src2
133 | XOR Reg Reg RI -- dst, src1, src2
134 | XORIS Reg Reg Imm -- XOR Immediate Shifted dst, src1, src2
141 | SLW Reg Reg RI -- shift left word
142 | SRW Reg Reg RI -- shift right word
143 | SRAW Reg Reg RI -- shift right arithmetic word
145 -- Rotate Left Word Immediate then AND with Mask
146 | RLWINM Reg Reg Int Int Int
148 | FADD Size Reg Reg Reg
149 | FSUB Size Reg Reg Reg
150 | FMUL Size Reg Reg Reg
151 | FDIV Size Reg Reg Reg
152 | FNEG Reg Reg -- negate is the same for single and double prec.
156 | FCTIWZ Reg Reg -- convert to integer word
157 | FRSP Reg Reg -- reduce to single precision
158 -- (but destination is a FP register)
160 | CRNOR Int Int Int -- condition register nor
161 | MFCR Reg -- move from condition register
163 | MFLR Reg -- move from link register
164 | FETCHPC Reg -- pseudo-instruction:
165 -- bcl to next insn, mflr reg
167 | LWSYNC -- memory barrier