1 -----------------------------------------------------------------------------
3 -- Machine-dependent assembly language
5 -- (c) The University of Glasgow 1993-2004
7 -----------------------------------------------------------------------------
9 #include "HsVersions.h"
10 #include "nativeGen/NCG.h"
43 condNegate :: Cond -> Cond
44 condNegate ALWAYS = panic "condNegate: ALWAYS"
57 -- -----------------------------------------------------------------------------
58 -- Machine's assembly language
60 -- We have a few common "instructions" (nearly all the pseudo-ops) but
61 -- mostly all of 'Instr' is machine-specific.
63 -- Register or immediate
72 -- some static data spat out during code
73 -- generation. Will be extracted before
75 | LDATA Section [CmmStatic]
77 -- start a new basic block. Useful during
78 -- codegen, removed later. Preceding
79 -- instruction should be a jump, as per the
80 -- invariants for a BasicBlock (see Cmm).
83 -- specify current stack offset for
84 -- benefit of subsequent passes
87 -- | spill this reg to a stack slot
90 -- | reload this reg from a stack slot
94 | LD Size Reg AddrMode -- Load size, dst, src
95 | LA Size Reg AddrMode -- Load arithmetic size, dst, src
96 | ST Size Reg AddrMode -- Store size, src, dst
97 | STU Size Reg AddrMode -- Store with Update size, src, dst
98 | LIS Reg Imm -- Load Immediate Shifted dst, src
99 | LI Reg Imm -- Load Immediate dst, src
100 | MR Reg Reg -- Move Register dst, src -- also for fmr
102 | CMP Size Reg RI --- size, src1, src2
103 | CMPL Size Reg RI --- size, src1, src2
106 | BCCFAR Cond BlockId
107 | JMP CLabel -- same as branch,
108 -- but with CLabel instead of block ID
110 | BCTR [BlockId] -- with list of local destinations
111 | BL CLabel [Reg] -- with list of argument regs
114 | ADD Reg Reg RI -- dst, src1, src2
115 | ADDC Reg Reg Reg -- (carrying) dst, src1, src2
116 | ADDE Reg Reg Reg -- (extend) dst, src1, src2
117 | ADDIS Reg Reg Imm -- Add Immediate Shifted dst, src1, src2
118 | SUBF Reg Reg Reg -- dst, src1, src2 ; dst = src2 - src1
123 | MULLW_MayOflo Reg Reg Reg
124 -- dst = 1 if src1 * src2 overflows
125 -- pseudo-instruction; pretty-printed as:
126 -- mullwo. dst, src1, src2
128 -- rlwinm dst, dst, 2, 31,31
130 | AND Reg Reg RI -- dst, src1, src2
131 | OR Reg Reg RI -- dst, src1, src2
132 | XOR Reg Reg RI -- dst, src1, src2
133 | XORIS Reg Reg Imm -- XOR Immediate Shifted dst, src1, src2
140 | SLW Reg Reg RI -- shift left word
141 | SRW Reg Reg RI -- shift right word
142 | SRAW Reg Reg RI -- shift right arithmetic word
144 -- Rotate Left Word Immediate then AND with Mask
145 | RLWINM Reg Reg Int Int Int
147 | FADD Size Reg Reg Reg
148 | FSUB Size Reg Reg Reg
149 | FMUL Size Reg Reg Reg
150 | FDIV Size Reg Reg Reg
151 | FNEG Reg Reg -- negate is the same for single and double prec.
155 | FCTIWZ Reg Reg -- convert to integer word
156 | FRSP Reg Reg -- reduce to single precision
157 -- (but destination is a FP register)
159 | CRNOR Int Int Int -- condition register nor
160 | MFCR Reg -- move from condition register
162 | MFLR Reg -- move from link register
163 | FETCHPC Reg -- pseudo-instruction:
164 -- bcl to next insn, mflr reg
166 | LWSYNC -- memory barrier