1 -----------------------------------------------------------------------------
3 -- Pretty-printing assembly language
5 -- (c) The University of Glasgow 1993-2005
7 -----------------------------------------------------------------------------
9 -- We start with the @pprXXX@s with some cross-platform commonality
10 -- (e.g., 'pprReg'); we conclude with the no-commonality monster,
13 #include "nativeGen/NCG.h"
16 pprNatCmmTop, pprBasicBlock, pprSectionHeader, pprData,
17 pprInstr, pprSize, pprUserReg
21 #include "HsVersions.h"
24 import MachOp ( MachRep(..), wordRep, isFloatingRep )
25 import MachRegs -- may differ per-platform
28 import CLabel ( CLabel, pprCLabel, externallyVisibleCLabel,
29 labelDynamic, mkAsmTempLabel, entryLblToInfoLbl )
30 #if HAVE_SUBSECTIONS_VIA_SYMBOLS
31 import CLabel ( mkDeadStripPreventer )
34 import Panic ( panic )
35 import Unique ( pprUnique )
38 import qualified Outputable
39 import Outputable ( Outputable )
42 import Data.Word ( Word8 )
43 import Control.Monad.ST
44 import Data.Char ( chr, ord )
45 import Data.Maybe ( isJust )
47 #if powerpc_TARGET_ARCH || darwin_TARGET_OS
48 import Data.Word(Word32)
52 -- -----------------------------------------------------------------------------
53 -- Printing this stuff out
55 asmSDoc d = Outputable.withPprStyleDoc (
56 Outputable.mkCodeStyle Outputable.AsmStyle) d
57 pprCLabel_asm l = asmSDoc (pprCLabel l)
59 pprNatCmmTop :: NatCmmTop -> Doc
60 pprNatCmmTop (CmmData section dats) =
61 pprSectionHeader section $$ vcat (map pprData dats)
63 -- special case for split markers:
64 pprNatCmmTop (CmmProc [] lbl _ []) = pprLabel lbl
66 pprNatCmmTop (CmmProc info lbl params blocks) =
67 pprSectionHeader Text $$
70 #if HAVE_SUBSECTIONS_VIA_SYMBOLS
71 pprCLabel_asm (mkDeadStripPreventer $ entryLblToInfoLbl lbl)
74 vcat (map pprData info) $$
75 pprLabel (entryLblToInfoLbl lbl)
79 (BasicBlock _ instrs : rest) ->
80 (if null info then pprLabel lbl else empty) $$
81 -- the first block doesn't get a label:
82 vcat (map pprInstr instrs) $$
83 vcat (map pprBasicBlock rest)
85 #if HAVE_SUBSECTIONS_VIA_SYMBOLS
86 -- If we are using the .subsections_via_symbols directive
87 -- (available on recent versions of Darwin),
88 -- we have to make sure that there is some kind of reference
89 -- from the entry code to a label on the _top_ of of the info table,
90 -- so that the linker will not think it is unreferenced and dead-strip
91 -- it. That's why the label is called a DeadStripPreventer (_dsp).
94 <+> pprCLabel_asm (entryLblToInfoLbl lbl)
96 <+> pprCLabel_asm (mkDeadStripPreventer $ entryLblToInfoLbl lbl)
101 pprBasicBlock :: NatBasicBlock -> Doc
102 pprBasicBlock (BasicBlock (BlockId id) instrs) =
103 pprLabel (mkAsmTempLabel id) $$
104 vcat (map pprInstr instrs)
106 -- -----------------------------------------------------------------------------
107 -- pprReg: print a 'Reg'
109 -- For x86, the way we print a register name depends
110 -- on which bit of it we care about. Yurgh.
112 pprUserReg :: Reg -> Doc
113 pprUserReg = pprReg IF_ARCH_i386(I32,) IF_ARCH_x86_64(I64,)
115 pprReg :: IF_ARCH_i386(MachRep ->,) IF_ARCH_x86_64(MachRep ->,) Reg -> Doc
117 pprReg IF_ARCH_i386(s,) IF_ARCH_x86_64(s,) r
119 RealReg i -> ppr_reg_no IF_ARCH_i386(s,) IF_ARCH_x86_64(s,) i
120 VirtualRegI u -> text "%vI_" <> asmSDoc (pprUnique u)
121 VirtualRegHi u -> text "%vHi_" <> asmSDoc (pprUnique u)
122 VirtualRegF u -> text "%vF_" <> asmSDoc (pprUnique u)
123 VirtualRegD u -> text "%vD_" <> asmSDoc (pprUnique u)
125 #if alpha_TARGET_ARCH
126 ppr_reg_no :: Int -> Doc
129 0 -> SLIT("$0"); 1 -> SLIT("$1");
130 2 -> SLIT("$2"); 3 -> SLIT("$3");
131 4 -> SLIT("$4"); 5 -> SLIT("$5");
132 6 -> SLIT("$6"); 7 -> SLIT("$7");
133 8 -> SLIT("$8"); 9 -> SLIT("$9");
134 10 -> SLIT("$10"); 11 -> SLIT("$11");
135 12 -> SLIT("$12"); 13 -> SLIT("$13");
136 14 -> SLIT("$14"); 15 -> SLIT("$15");
137 16 -> SLIT("$16"); 17 -> SLIT("$17");
138 18 -> SLIT("$18"); 19 -> SLIT("$19");
139 20 -> SLIT("$20"); 21 -> SLIT("$21");
140 22 -> SLIT("$22"); 23 -> SLIT("$23");
141 24 -> SLIT("$24"); 25 -> SLIT("$25");
142 26 -> SLIT("$26"); 27 -> SLIT("$27");
143 28 -> SLIT("$28"); 29 -> SLIT("$29");
144 30 -> SLIT("$30"); 31 -> SLIT("$31");
145 32 -> SLIT("$f0"); 33 -> SLIT("$f1");
146 34 -> SLIT("$f2"); 35 -> SLIT("$f3");
147 36 -> SLIT("$f4"); 37 -> SLIT("$f5");
148 38 -> SLIT("$f6"); 39 -> SLIT("$f7");
149 40 -> SLIT("$f8"); 41 -> SLIT("$f9");
150 42 -> SLIT("$f10"); 43 -> SLIT("$f11");
151 44 -> SLIT("$f12"); 45 -> SLIT("$f13");
152 46 -> SLIT("$f14"); 47 -> SLIT("$f15");
153 48 -> SLIT("$f16"); 49 -> SLIT("$f17");
154 50 -> SLIT("$f18"); 51 -> SLIT("$f19");
155 52 -> SLIT("$f20"); 53 -> SLIT("$f21");
156 54 -> SLIT("$f22"); 55 -> SLIT("$f23");
157 56 -> SLIT("$f24"); 57 -> SLIT("$f25");
158 58 -> SLIT("$f26"); 59 -> SLIT("$f27");
159 60 -> SLIT("$f28"); 61 -> SLIT("$f29");
160 62 -> SLIT("$f30"); 63 -> SLIT("$f31");
161 _ -> SLIT("very naughty alpha register")
165 ppr_reg_no :: MachRep -> Int -> Doc
166 ppr_reg_no I8 = ppr_reg_byte
167 ppr_reg_no I16 = ppr_reg_word
168 ppr_reg_no _ = ppr_reg_long
170 ppr_reg_byte i = ptext
172 0 -> SLIT("%al"); 1 -> SLIT("%bl");
173 2 -> SLIT("%cl"); 3 -> SLIT("%dl");
174 _ -> SLIT("very naughty I386 byte register")
177 ppr_reg_word i = ptext
179 0 -> SLIT("%ax"); 1 -> SLIT("%bx");
180 2 -> SLIT("%cx"); 3 -> SLIT("%dx");
181 4 -> SLIT("%si"); 5 -> SLIT("%di");
182 6 -> SLIT("%bp"); 7 -> SLIT("%sp");
183 _ -> SLIT("very naughty I386 word register")
186 ppr_reg_long i = ptext
188 0 -> SLIT("%eax"); 1 -> SLIT("%ebx");
189 2 -> SLIT("%ecx"); 3 -> SLIT("%edx");
190 4 -> SLIT("%esi"); 5 -> SLIT("%edi");
191 6 -> SLIT("%ebp"); 7 -> SLIT("%esp");
192 8 -> SLIT("%fake0"); 9 -> SLIT("%fake1");
193 10 -> SLIT("%fake2"); 11 -> SLIT("%fake3");
194 12 -> SLIT("%fake4"); 13 -> SLIT("%fake5");
195 _ -> SLIT("very naughty I386 register")
199 #if x86_64_TARGET_ARCH
200 ppr_reg_no :: MachRep -> Int -> Doc
201 ppr_reg_no I8 = ppr_reg_byte
202 ppr_reg_no I16 = ppr_reg_word
203 ppr_reg_no I32 = ppr_reg_long
204 ppr_reg_no _ = ppr_reg_quad
206 ppr_reg_byte i = ptext
208 0 -> SLIT("%al"); 1 -> SLIT("%bl");
209 2 -> SLIT("%cl"); 3 -> SLIT("%dl");
210 4 -> SLIT("%sil"); 5 -> SLIT("%dil"); -- new 8-bit regs!
211 6 -> SLIT("%bpl"); 7 -> SLIT("%spl");
212 8 -> SLIT("%r8b"); 9 -> SLIT("%r9b");
213 10 -> SLIT("%r10b"); 11 -> SLIT("%r11b");
214 12 -> SLIT("%r12b"); 13 -> SLIT("%r13b");
215 14 -> SLIT("%r14b"); 15 -> SLIT("%r15b");
216 _ -> SLIT("very naughty x86_64 byte register")
219 ppr_reg_word i = ptext
221 0 -> SLIT("%ax"); 1 -> SLIT("%bx");
222 2 -> SLIT("%cx"); 3 -> SLIT("%dx");
223 4 -> SLIT("%si"); 5 -> SLIT("%di");
224 6 -> SLIT("%bp"); 7 -> SLIT("%sp");
225 8 -> SLIT("%r8w"); 9 -> SLIT("%r9w");
226 10 -> SLIT("%r10w"); 11 -> SLIT("%r11w");
227 12 -> SLIT("%r12w"); 13 -> SLIT("%r13w");
228 14 -> SLIT("%r14w"); 15 -> SLIT("%r15w");
229 _ -> SLIT("very naughty x86_64 word register")
232 ppr_reg_long i = ptext
234 0 -> SLIT("%eax"); 1 -> SLIT("%ebx");
235 2 -> SLIT("%ecx"); 3 -> SLIT("%edx");
236 4 -> SLIT("%esi"); 5 -> SLIT("%edi");
237 6 -> SLIT("%ebp"); 7 -> SLIT("%esp");
238 8 -> SLIT("%r8d"); 9 -> SLIT("%r9d");
239 10 -> SLIT("%r10d"); 11 -> SLIT("%r11d");
240 12 -> SLIT("%r12d"); 13 -> SLIT("%r13d");
241 14 -> SLIT("%r14d"); 15 -> SLIT("%r15d");
242 _ -> SLIT("very naughty x86_64 register")
245 ppr_reg_quad i = ptext
247 0 -> SLIT("%rax"); 1 -> SLIT("%rbx");
248 2 -> SLIT("%rcx"); 3 -> SLIT("%rdx");
249 4 -> SLIT("%rsi"); 5 -> SLIT("%rdi");
250 6 -> SLIT("%rbp"); 7 -> SLIT("%rsp");
251 8 -> SLIT("%r8"); 9 -> SLIT("%r9");
252 10 -> SLIT("%r10"); 11 -> SLIT("%r11");
253 12 -> SLIT("%r12"); 13 -> SLIT("%r13");
254 14 -> SLIT("%r14"); 15 -> SLIT("%r15");
255 16 -> SLIT("%xmm0"); 17 -> SLIT("%xmm1");
256 18 -> SLIT("%xmm2"); 19 -> SLIT("%xmm3");
257 20 -> SLIT("%xmm4"); 21 -> SLIT("%xmm5");
258 22 -> SLIT("%xmm6"); 23 -> SLIT("%xmm7");
259 24 -> SLIT("%xmm8"); 25 -> SLIT("%xmm9");
260 26 -> SLIT("%xmm10"); 27 -> SLIT("%xmm11");
261 28 -> SLIT("%xmm12"); 29 -> SLIT("%xmm13");
262 30 -> SLIT("%xmm14"); 31 -> SLIT("%xmm15");
263 _ -> SLIT("very naughty x86_64 register")
267 #if sparc_TARGET_ARCH
268 ppr_reg_no :: Int -> Doc
271 0 -> SLIT("%g0"); 1 -> SLIT("%g1");
272 2 -> SLIT("%g2"); 3 -> SLIT("%g3");
273 4 -> SLIT("%g4"); 5 -> SLIT("%g5");
274 6 -> SLIT("%g6"); 7 -> SLIT("%g7");
275 8 -> SLIT("%o0"); 9 -> SLIT("%o1");
276 10 -> SLIT("%o2"); 11 -> SLIT("%o3");
277 12 -> SLIT("%o4"); 13 -> SLIT("%o5");
278 14 -> SLIT("%o6"); 15 -> SLIT("%o7");
279 16 -> SLIT("%l0"); 17 -> SLIT("%l1");
280 18 -> SLIT("%l2"); 19 -> SLIT("%l3");
281 20 -> SLIT("%l4"); 21 -> SLIT("%l5");
282 22 -> SLIT("%l6"); 23 -> SLIT("%l7");
283 24 -> SLIT("%i0"); 25 -> SLIT("%i1");
284 26 -> SLIT("%i2"); 27 -> SLIT("%i3");
285 28 -> SLIT("%i4"); 29 -> SLIT("%i5");
286 30 -> SLIT("%i6"); 31 -> SLIT("%i7");
287 32 -> SLIT("%f0"); 33 -> SLIT("%f1");
288 34 -> SLIT("%f2"); 35 -> SLIT("%f3");
289 36 -> SLIT("%f4"); 37 -> SLIT("%f5");
290 38 -> SLIT("%f6"); 39 -> SLIT("%f7");
291 40 -> SLIT("%f8"); 41 -> SLIT("%f9");
292 42 -> SLIT("%f10"); 43 -> SLIT("%f11");
293 44 -> SLIT("%f12"); 45 -> SLIT("%f13");
294 46 -> SLIT("%f14"); 47 -> SLIT("%f15");
295 48 -> SLIT("%f16"); 49 -> SLIT("%f17");
296 50 -> SLIT("%f18"); 51 -> SLIT("%f19");
297 52 -> SLIT("%f20"); 53 -> SLIT("%f21");
298 54 -> SLIT("%f22"); 55 -> SLIT("%f23");
299 56 -> SLIT("%f24"); 57 -> SLIT("%f25");
300 58 -> SLIT("%f26"); 59 -> SLIT("%f27");
301 60 -> SLIT("%f28"); 61 -> SLIT("%f29");
302 62 -> SLIT("%f30"); 63 -> SLIT("%f31");
303 _ -> SLIT("very naughty sparc register")
306 #if powerpc_TARGET_ARCH
308 ppr_reg_no :: Int -> Doc
311 0 -> SLIT("r0"); 1 -> SLIT("r1");
312 2 -> SLIT("r2"); 3 -> SLIT("r3");
313 4 -> SLIT("r4"); 5 -> SLIT("r5");
314 6 -> SLIT("r6"); 7 -> SLIT("r7");
315 8 -> SLIT("r8"); 9 -> SLIT("r9");
316 10 -> SLIT("r10"); 11 -> SLIT("r11");
317 12 -> SLIT("r12"); 13 -> SLIT("r13");
318 14 -> SLIT("r14"); 15 -> SLIT("r15");
319 16 -> SLIT("r16"); 17 -> SLIT("r17");
320 18 -> SLIT("r18"); 19 -> SLIT("r19");
321 20 -> SLIT("r20"); 21 -> SLIT("r21");
322 22 -> SLIT("r22"); 23 -> SLIT("r23");
323 24 -> SLIT("r24"); 25 -> SLIT("r25");
324 26 -> SLIT("r26"); 27 -> SLIT("r27");
325 28 -> SLIT("r28"); 29 -> SLIT("r29");
326 30 -> SLIT("r30"); 31 -> SLIT("r31");
327 32 -> SLIT("f0"); 33 -> SLIT("f1");
328 34 -> SLIT("f2"); 35 -> SLIT("f3");
329 36 -> SLIT("f4"); 37 -> SLIT("f5");
330 38 -> SLIT("f6"); 39 -> SLIT("f7");
331 40 -> SLIT("f8"); 41 -> SLIT("f9");
332 42 -> SLIT("f10"); 43 -> SLIT("f11");
333 44 -> SLIT("f12"); 45 -> SLIT("f13");
334 46 -> SLIT("f14"); 47 -> SLIT("f15");
335 48 -> SLIT("f16"); 49 -> SLIT("f17");
336 50 -> SLIT("f18"); 51 -> SLIT("f19");
337 52 -> SLIT("f20"); 53 -> SLIT("f21");
338 54 -> SLIT("f22"); 55 -> SLIT("f23");
339 56 -> SLIT("f24"); 57 -> SLIT("f25");
340 58 -> SLIT("f26"); 59 -> SLIT("f27");
341 60 -> SLIT("f28"); 61 -> SLIT("f29");
342 62 -> SLIT("f30"); 63 -> SLIT("f31");
343 _ -> SLIT("very naughty powerpc register")
346 ppr_reg_no :: Int -> Doc
347 ppr_reg_no i | i <= 31 = int i -- GPRs
348 | i <= 63 = int (i-32) -- FPRs
349 | otherwise = ptext SLIT("very naughty powerpc register")
354 -- -----------------------------------------------------------------------------
355 -- pprSize: print a 'Size'
357 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH || sparc_TARGET_ARCH
358 pprSize :: MachRep -> Doc
360 pprSize :: Size -> Doc
363 pprSize x = ptext (case x of
364 #if alpha_TARGET_ARCH
367 -- W -> SLIT("w") UNUSED
368 -- Wu -> SLIT("wu") UNUSED
371 -- FF -> SLIT("f") UNUSED
372 -- DF -> SLIT("d") UNUSED
373 -- GF -> SLIT("g") UNUSED
374 -- SF -> SLIT("s") UNUSED
377 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
388 #if x86_64_TARGET_ARCH
389 F32 -> SLIT("ss") -- "scalar single-precision float" (SSE2)
390 F64 -> SLIT("sd") -- "scalar double-precision float" (SSE2)
392 #if sparc_TARGET_ARCH
399 pprStSize :: MachRep -> Doc
400 pprStSize x = ptext (case x of
407 #if powerpc_TARGET_ARCH
416 -- -----------------------------------------------------------------------------
417 -- pprCond: print a 'Cond'
419 pprCond :: Cond -> Doc
421 pprCond c = ptext (case c of {
422 #if alpha_TARGET_ARCH
432 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
433 GEU -> SLIT("ae"); LU -> SLIT("b");
434 EQQ -> SLIT("e"); GTT -> SLIT("g");
435 GE -> SLIT("ge"); GU -> SLIT("a");
436 LTT -> SLIT("l"); LE -> SLIT("le");
437 LEU -> SLIT("be"); NE -> SLIT("ne");
438 NEG -> SLIT("s"); POS -> SLIT("ns");
439 CARRY -> SLIT("c"); OFLO -> SLIT("o");
440 PARITY -> SLIT("p"); NOTPARITY -> SLIT("np");
441 ALWAYS -> SLIT("mp") -- hack
443 #if sparc_TARGET_ARCH
444 ALWAYS -> SLIT(""); NEVER -> SLIT("n");
445 GEU -> SLIT("geu"); LU -> SLIT("lu");
446 EQQ -> SLIT("e"); GTT -> SLIT("g");
447 GE -> SLIT("ge"); GU -> SLIT("gu");
448 LTT -> SLIT("l"); LE -> SLIT("le");
449 LEU -> SLIT("leu"); NE -> SLIT("ne");
450 NEG -> SLIT("neg"); POS -> SLIT("pos");
451 VC -> SLIT("vc"); VS -> SLIT("vs")
453 #if powerpc_TARGET_ARCH
455 EQQ -> SLIT("eq"); NE -> SLIT("ne");
456 LTT -> SLIT("lt"); GE -> SLIT("ge");
457 GTT -> SLIT("gt"); LE -> SLIT("le");
458 LU -> SLIT("lt"); GEU -> SLIT("ge");
459 GU -> SLIT("gt"); LEU -> SLIT("le");
464 -- -----------------------------------------------------------------------------
465 -- pprImm: print an 'Imm'
469 pprImm (ImmInt i) = int i
470 pprImm (ImmInteger i) = integer i
471 pprImm (ImmCLbl l) = pprCLabel_asm l
472 pprImm (ImmIndex l i) = pprCLabel_asm l <> char '+' <> int i
473 pprImm (ImmLit s) = s
475 pprImm (ImmFloat _) = ptext SLIT("naughty float immediate")
476 pprImm (ImmDouble _) = ptext SLIT("naughty double immediate")
478 pprImm (ImmConstantSum a b) = pprImm a <> char '+' <> pprImm b
479 #if sparc_TARGET_ARCH
480 -- ToDo: This should really be fixed in the PIC support, but only
482 pprImm (ImmConstantDiff a b) = pprImm a
484 pprImm (ImmConstantDiff a b) = pprImm a <> char '-'
485 <> lparen <> pprImm b <> rparen
488 #if sparc_TARGET_ARCH
490 = hcat [ pp_lo, pprImm i, rparen ]
495 = hcat [ pp_hi, pprImm i, rparen ]
499 #if powerpc_TARGET_ARCH
502 = hcat [ pp_lo, pprImm i, rparen ]
507 = hcat [ pp_hi, pprImm i, rparen ]
512 = hcat [ pp_ha, pprImm i, rparen ]
518 = pprImm i <> text "@l"
521 = pprImm i <> text "@h"
524 = pprImm i <> text "@ha"
529 -- -----------------------------------------------------------------------------
530 -- @pprAddr: print an 'AddrMode'
532 pprAddr :: AddrMode -> Doc
534 #if alpha_TARGET_ARCH
535 pprAddr (AddrReg r) = parens (pprReg r)
536 pprAddr (AddrImm i) = pprImm i
537 pprAddr (AddrRegImm r1 i)
538 = (<>) (pprImm i) (parens (pprReg r1))
543 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
544 pprAddr (ImmAddr imm off)
545 = let pp_imm = pprImm imm
549 else if (off < 0) then
552 pp_imm <> char '+' <> int off
554 pprAddr (AddrBaseIndex base index displacement)
556 pp_disp = ppr_disp displacement
557 pp_off p = pp_disp <> char '(' <> p <> char ')'
558 pp_reg r = pprReg wordRep r
561 (EABaseNone, EAIndexNone) -> pp_disp
562 (EABaseReg b, EAIndexNone) -> pp_off (pp_reg b)
563 (EABaseRip, EAIndexNone) -> pp_off (ptext SLIT("%rip"))
564 (EABaseNone, EAIndex r i) -> pp_off (comma <> pp_reg r <> comma <> int i)
565 (EABaseReg b, EAIndex r i) -> pp_off (pp_reg b <> comma <> pp_reg r
568 ppr_disp (ImmInt 0) = empty
569 ppr_disp imm = pprImm imm
574 #if sparc_TARGET_ARCH
575 pprAddr (AddrRegReg r1 (RealReg 0)) = pprReg r1
577 pprAddr (AddrRegReg r1 r2)
578 = hcat [ pprReg r1, char '+', pprReg r2 ]
580 pprAddr (AddrRegImm r1 (ImmInt i))
582 | not (fits13Bits i) = largeOffsetError i
583 | otherwise = hcat [ pprReg r1, pp_sign, int i ]
585 pp_sign = if i > 0 then char '+' else empty
587 pprAddr (AddrRegImm r1 (ImmInteger i))
589 | not (fits13Bits i) = largeOffsetError i
590 | otherwise = hcat [ pprReg r1, pp_sign, integer i ]
592 pp_sign = if i > 0 then char '+' else empty
594 pprAddr (AddrRegImm r1 imm)
595 = hcat [ pprReg r1, char '+', pprImm imm ]
600 #if powerpc_TARGET_ARCH
601 pprAddr (AddrRegReg r1 r2)
602 = pprReg r1 <+> ptext SLIT(", ") <+> pprReg r2
604 pprAddr (AddrRegImm r1 (ImmInt i)) = hcat [ int i, char '(', pprReg r1, char ')' ]
605 pprAddr (AddrRegImm r1 (ImmInteger i)) = hcat [ integer i, char '(', pprReg r1, char ')' ]
606 pprAddr (AddrRegImm r1 imm) = hcat [ pprImm imm, char '(', pprReg r1, char ')' ]
610 -- -----------------------------------------------------------------------------
611 -- pprData: print a 'CmmStatic'
613 pprSectionHeader Text
615 IF_ARCH_alpha(SLIT("\t.text\n\t.align 3") {-word boundary-}
616 ,IF_ARCH_sparc(SLIT(".text\n\t.align 4") {-word boundary-}
617 ,IF_ARCH_i386(IF_OS_darwin(SLIT(".text\n\t.align 2"),
618 SLIT(".text\n\t.align 4,0x90"))
619 {-needs per-OS variation!-}
620 ,IF_ARCH_x86_64(IF_OS_darwin(SLIT(".text\n.align 3"),
621 SLIT(".text\n\t.align 8"))
622 ,IF_ARCH_powerpc(SLIT(".text\n.align 2")
624 pprSectionHeader Data
626 IF_ARCH_alpha(SLIT("\t.data\n\t.align 3")
627 ,IF_ARCH_sparc(SLIT(".data\n\t.align 8") {-<8 will break double constants -}
628 ,IF_ARCH_i386(IF_OS_darwin(SLIT(".data\n\t.align 2"),
629 SLIT(".data\n\t.align 4"))
630 ,IF_ARCH_x86_64(IF_OS_darwin(SLIT(".data\n.align 3"),
631 SLIT(".data\n\t.align 8"))
632 ,IF_ARCH_powerpc(SLIT(".data\n.align 2")
634 pprSectionHeader ReadOnlyData
636 IF_ARCH_alpha(SLIT("\t.data\n\t.align 3")
637 ,IF_ARCH_sparc(SLIT(".data\n\t.align 8") {-<8 will break double constants -}
638 ,IF_ARCH_i386(IF_OS_darwin(SLIT(".const\n.align 2"),
639 SLIT(".section .rodata\n\t.align 4"))
640 ,IF_ARCH_x86_64(IF_OS_darwin(SLIT(".const\n.align 3"),
641 SLIT(".section .rodata\n\t.align 8"))
642 ,IF_ARCH_powerpc(IF_OS_darwin(SLIT(".const\n.align 2"),
643 SLIT(".section .rodata\n\t.align 2"))
645 pprSectionHeader RelocatableReadOnlyData
647 IF_ARCH_alpha(SLIT("\t.data\n\t.align 3")
648 ,IF_ARCH_sparc(SLIT(".data\n\t.align 8") {-<8 will break double constants -}
649 ,IF_ARCH_i386(IF_OS_darwin(SLIT(".const_data\n.align 2"),
650 SLIT(".section .data\n\t.align 4"))
651 ,IF_ARCH_x86_64(IF_OS_darwin(SLIT(".const_data\n.align 3"),
652 SLIT(".section .data\n\t.align 8"))
653 ,IF_ARCH_powerpc(IF_OS_darwin(SLIT(".const_data\n.align 2"),
654 SLIT(".data\n\t.align 2"))
656 pprSectionHeader UninitialisedData
658 IF_ARCH_alpha(SLIT("\t.bss\n\t.align 3")
659 ,IF_ARCH_sparc(SLIT(".bss\n\t.align 8") {-<8 will break double constants -}
660 ,IF_ARCH_i386(IF_OS_darwin(SLIT(".data\n\t.align 2"),
661 SLIT(".section .bss\n\t.align 4"))
662 ,IF_ARCH_x86_64(IF_OS_darwin(SLIT(".data\n\t.align 3"),
663 SLIT(".section .bss\n\t.align 8"))
664 ,IF_ARCH_powerpc(IF_OS_darwin(SLIT(".const_data\n.align 2"),
665 SLIT(".section .bss\n\t.align 2"))
667 pprSectionHeader ReadOnlyData16
669 IF_ARCH_alpha(SLIT("\t.data\n\t.align 4")
670 ,IF_ARCH_sparc(SLIT(".data\n\t.align 16")
671 ,IF_ARCH_i386(IF_OS_darwin(SLIT(".const\n.align 4"),
672 SLIT(".section .rodata\n\t.align 16"))
673 ,IF_ARCH_x86_64(IF_OS_darwin(SLIT(".const\n.align 4"),
674 SLIT(".section .rodata.cst16\n\t.align 16"))
675 ,IF_ARCH_powerpc(IF_OS_darwin(SLIT(".const\n.align 4"),
676 SLIT(".section .rodata\n\t.align 4"))
679 pprSectionHeader (OtherSection sec)
680 = panic "PprMach.pprSectionHeader: unknown section"
682 pprData :: CmmStatic -> Doc
683 pprData (CmmAlign bytes) = pprAlign bytes
684 pprData (CmmDataLabel lbl) = pprLabel lbl
685 pprData (CmmString str) = pprASCII str
686 pprData (CmmUninitialised bytes) = ptext SLIT(".space ") <> int bytes
687 pprData (CmmStaticLit lit) = pprDataItem lit
689 pprGloblDecl :: CLabel -> Doc
691 | not (externallyVisibleCLabel lbl) = empty
692 | otherwise = ptext IF_ARCH_sparc(SLIT(".global "),
696 pprTypeAndSizeDecl :: CLabel -> Doc
697 pprTypeAndSizeDecl lbl
699 | not (externallyVisibleCLabel lbl) = empty
700 | otherwise = ptext SLIT(".type ") <>
701 pprCLabel_asm lbl <> ptext SLIT(", @object")
706 pprLabel :: CLabel -> Doc
707 pprLabel lbl = pprGloblDecl lbl $$ pprTypeAndSizeDecl lbl $$ (pprCLabel_asm lbl <> char ':')
711 = vcat (map do1 str) $$ do1 0
714 do1 w = ptext SLIT("\t.byte\t") <> int (fromIntegral w)
717 IF_ARCH_alpha(ptextSLIT(".align ") <> int pow2,
718 IF_ARCH_i386(ptext SLIT(".align ") <> int IF_OS_darwin(pow2,bytes),
719 IF_ARCH_x86_64(ptext SLIT(".align ") <> int IF_OS_darwin(pow2,bytes),
720 IF_ARCH_sparc(ptext SLIT(".align ") <> int bytes,
721 IF_ARCH_powerpc(ptext SLIT(".align ") <> int pow2,)))))
725 log2 :: Int -> Int -- cache the common ones
730 log2 n = 1 + log2 (n `quot` 2)
733 pprDataItem :: CmmLit -> Doc
735 = vcat (ppr_item (cmmLitRep lit) lit)
739 -- These seem to be common:
740 ppr_item I8 x = [ptext SLIT("\t.byte\t") <> pprImm imm]
741 ppr_item I32 x = [ptext SLIT("\t.long\t") <> pprImm imm]
742 ppr_item F32 (CmmFloat r _)
743 = let bs = floatToBytes (fromRational r)
744 in map (\b -> ptext SLIT("\t.byte\t") <> pprImm (ImmInt b)) bs
745 ppr_item F64 (CmmFloat r _)
746 = let bs = doubleToBytes (fromRational r)
747 in map (\b -> ptext SLIT("\t.byte\t") <> pprImm (ImmInt b)) bs
749 #if sparc_TARGET_ARCH
750 -- copy n paste of x86 version
751 ppr_item I16 x = [ptext SLIT("\t.short\t") <> pprImm imm]
752 ppr_item I64 x = [ptext SLIT("\t.quad\t") <> pprImm imm]
754 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
755 ppr_item I16 x = [ptext SLIT("\t.word\t") <> pprImm imm]
757 #if i386_TARGET_ARCH && darwin_TARGET_OS
758 ppr_item I64 (CmmInt x _) =
759 [ptext SLIT("\t.long\t")
760 <> int (fromIntegral (fromIntegral x :: Word32)),
761 ptext SLIT("\t.long\t")
763 (fromIntegral (x `shiftR` 32) :: Word32))]
765 #if i386_TARGET_ARCH || (darwin_TARGET_OS && x86_64_TARGET_ARCH)
766 ppr_item I64 x = [ptext SLIT("\t.quad\t") <> pprImm imm]
768 #if x86_64_TARGET_ARCH && !darwin_TARGET_OS
769 -- x86_64: binutils can't handle the R_X86_64_PC64 relocation
770 -- type, which means we can't do pc-relative 64-bit addresses.
771 -- Fortunately we're assuming the small memory model, in which
772 -- all such offsets will fit into 32 bits, so we have to stick
773 -- to 32-bit offset fields and modify the RTS appropriately
775 -- See Note [x86-64-relative] in includes/InfoTables.h
778 | isRelativeReloc x =
779 [ptext SLIT("\t.long\t") <> pprImm imm,
780 ptext SLIT("\t.long\t0")]
782 [ptext SLIT("\t.quad\t") <> pprImm imm]
784 isRelativeReloc (CmmLabelDiffOff _ _ _) = True
785 isRelativeReloc _ = False
787 #if powerpc_TARGET_ARCH
788 ppr_item I16 x = [ptext SLIT("\t.short\t") <> pprImm imm]
789 ppr_item I64 (CmmInt x _) =
790 [ptext SLIT("\t.long\t")
792 (fromIntegral (x `shiftR` 32) :: Word32)),
793 ptext SLIT("\t.long\t")
794 <> int (fromIntegral (fromIntegral x :: Word32))]
797 -- fall through to rest of (machine-specific) pprInstr...
799 -- -----------------------------------------------------------------------------
800 -- pprInstr: print an 'Instr'
802 instance Outputable Instr where
803 ppr instr = Outputable.docToSDoc $ pprInstr instr
805 pprInstr :: Instr -> Doc
807 --pprInstr (COMMENT s) = empty -- nuke 'em
809 = IF_ARCH_alpha( ((<>) (ptext SLIT("\t# ")) (ftext s))
810 ,IF_ARCH_sparc( ((<>) (ptext SLIT("! ")) (ftext s))
811 ,IF_ARCH_i386( ((<>) (ptext SLIT("# ")) (ftext s))
812 ,IF_ARCH_x86_64( ((<>) (ptext SLIT("# ")) (ftext s))
813 ,IF_ARCH_powerpc( IF_OS_linux(
814 ((<>) (ptext SLIT("# ")) (ftext s)),
815 ((<>) (ptext SLIT("; ")) (ftext s)))
819 = pprInstr (COMMENT (mkFastString ("\tdelta = " ++ show d)))
821 pprInstr (NEWBLOCK _)
822 = panic "PprMach.pprInstr: NEWBLOCK"
825 = panic "PprMach.pprInstr: LDATA"
827 -- -----------------------------------------------------------------------------
828 -- pprInstr for an Alpha
830 #if alpha_TARGET_ARCH
832 pprInstr (SPILL reg slot)
834 ptext SLIT("\tSPILL"),
838 ptext SLIT("SLOT") <> parens (int slot)]
840 pprInstr (RELOAD slot reg)
842 ptext SLIT("\tRELOAD"),
844 ptext SLIT("SLOT") <> parens (int slot),
848 pprInstr (LD size reg addr)
858 pprInstr (LDA reg addr)
860 ptext SLIT("\tlda\t"),
866 pprInstr (LDAH reg addr)
868 ptext SLIT("\tldah\t"),
874 pprInstr (LDGP reg addr)
876 ptext SLIT("\tldgp\t"),
882 pprInstr (LDI size reg imm)
892 pprInstr (ST size reg addr)
904 ptext SLIT("\tclr\t"),
908 pprInstr (ABS size ri reg)
918 pprInstr (NEG size ov ri reg)
922 if ov then ptext SLIT("v\t") else char '\t',
928 pprInstr (ADD size ov reg1 ri reg2)
932 if ov then ptext SLIT("v\t") else char '\t',
940 pprInstr (SADD size scale reg1 ri reg2)
942 ptext (case scale of {{-UNUSED:L -> SLIT("\ts4");-} Q -> SLIT("\ts8")}),
953 pprInstr (SUB size ov reg1 ri reg2)
957 if ov then ptext SLIT("v\t") else char '\t',
965 pprInstr (SSUB size scale reg1 ri reg2)
967 ptext (case scale of {{-UNUSED:L -> SLIT("\ts4");-} Q -> SLIT("\ts8")}),
978 pprInstr (MUL size ov reg1 ri reg2)
982 if ov then ptext SLIT("v\t") else char '\t',
990 pprInstr (DIV size uns reg1 ri reg2)
994 if uns then ptext SLIT("u\t") else char '\t',
1002 pprInstr (REM size uns reg1 ri reg2)
1004 ptext SLIT("\trem"),
1006 if uns then ptext SLIT("u\t") else char '\t',
1014 pprInstr (NOT ri reg)
1016 ptext SLIT("\tnot"),
1023 pprInstr (AND reg1 ri reg2) = pprRegRIReg SLIT("and") reg1 ri reg2
1024 pprInstr (ANDNOT reg1 ri reg2) = pprRegRIReg SLIT("andnot") reg1 ri reg2
1025 pprInstr (OR reg1 ri reg2) = pprRegRIReg SLIT("or") reg1 ri reg2
1026 pprInstr (ORNOT reg1 ri reg2) = pprRegRIReg SLIT("ornot") reg1 ri reg2
1027 pprInstr (XOR reg1 ri reg2) = pprRegRIReg SLIT("xor") reg1 ri reg2
1028 pprInstr (XORNOT reg1 ri reg2) = pprRegRIReg SLIT("xornot") reg1 ri reg2
1030 pprInstr (SLL reg1 ri reg2) = pprRegRIReg SLIT("sll") reg1 ri reg2
1031 pprInstr (SRL reg1 ri reg2) = pprRegRIReg SLIT("srl") reg1 ri reg2
1032 pprInstr (SRA reg1 ri reg2) = pprRegRIReg SLIT("sra") reg1 ri reg2
1034 pprInstr (ZAP reg1 ri reg2) = pprRegRIReg SLIT("zap") reg1 ri reg2
1035 pprInstr (ZAPNOT reg1 ri reg2) = pprRegRIReg SLIT("zapnot") reg1 ri reg2
1037 pprInstr (NOP) = ptext SLIT("\tnop")
1039 pprInstr (CMP cond reg1 ri reg2)
1041 ptext SLIT("\tcmp"),
1053 ptext SLIT("\tfclr\t"),
1057 pprInstr (FABS reg1 reg2)
1059 ptext SLIT("\tfabs\t"),
1065 pprInstr (FNEG size reg1 reg2)
1067 ptext SLIT("\tneg"),
1075 pprInstr (FADD size reg1 reg2 reg3) = pprSizeRegRegReg SLIT("add") size reg1 reg2 reg3
1076 pprInstr (FDIV size reg1 reg2 reg3) = pprSizeRegRegReg SLIT("div") size reg1 reg2 reg3
1077 pprInstr (FMUL size reg1 reg2 reg3) = pprSizeRegRegReg SLIT("mul") size reg1 reg2 reg3
1078 pprInstr (FSUB size reg1 reg2 reg3) = pprSizeRegRegReg SLIT("sub") size reg1 reg2 reg3
1080 pprInstr (CVTxy size1 size2 reg1 reg2)
1082 ptext SLIT("\tcvt"),
1084 case size2 of {Q -> ptext SLIT("qc"); _ -> pprSize size2},
1091 pprInstr (FCMP size cond reg1 reg2 reg3)
1093 ptext SLIT("\tcmp"),
1104 pprInstr (FMOV reg1 reg2)
1106 ptext SLIT("\tfmov\t"),
1112 pprInstr (BI ALWAYS reg lab) = pprInstr (BR lab)
1114 pprInstr (BI NEVER reg lab) = empty
1116 pprInstr (BI cond reg lab)
1126 pprInstr (BF cond reg lab)
1137 = (<>) (ptext SLIT("\tbr\t")) (pprImm lab)
1139 pprInstr (JMP reg addr hint)
1141 ptext SLIT("\tjmp\t"),
1149 pprInstr (BSR imm n)
1150 = (<>) (ptext SLIT("\tbsr\t")) (pprImm imm)
1152 pprInstr (JSR reg addr n)
1154 ptext SLIT("\tjsr\t"),
1160 pprInstr (FUNBEGIN clab)
1162 if (externallyVisibleCLabel clab) then
1163 hcat [ptext SLIT("\t.globl\t"), pp_lab, char '\n']
1166 ptext SLIT("\t.ent "),
1175 pp_lab = pprCLabel_asm clab
1177 -- NEVER use commas within those string literals, cpp will ruin your day
1178 pp_ldgp = hcat [ ptext SLIT(":\n\tldgp $29"), char ',', ptext SLIT("0($27)\n") ]
1179 pp_frame = hcat [ ptext SLIT("..ng:\n\t.frame $30"), char ',',
1180 ptext SLIT("4240"), char ',',
1181 ptext SLIT("$26"), char ',',
1182 ptext SLIT("0\n\t.prologue 1") ]
1184 pprInstr (FUNEND clab)
1185 = (<>) (ptext SLIT("\t.align 4\n\t.end ")) (pprCLabel_asm clab)
1188 Continue with Alpha-only printing bits and bobs:
1192 pprRI (RIReg r) = pprReg r
1193 pprRI (RIImm r) = pprImm r
1195 pprRegRIReg :: LitString -> Reg -> RI -> Reg -> Doc
1196 pprRegRIReg name reg1 ri reg2
1208 pprSizeRegRegReg :: LitString -> Size -> Reg -> Reg -> Reg -> Doc
1209 pprSizeRegRegReg name size reg1 reg2 reg3
1222 #endif /* alpha_TARGET_ARCH */
1225 -- -----------------------------------------------------------------------------
1226 -- pprInstr for an x86
1228 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
1230 {- -- BUGS: changed for coloring allocator
1231 pprInstr v@(MOV size s@(OpReg src) d@(OpReg dst)) -- hack -- write a pass for this and patch linear allocator with it
1234 #if 0 /* #ifdef DEBUG */
1235 (<>) (ptext SLIT("# warning: ")) (pprSizeOpOp SLIT("mov") size s d)
1241 pprInstr (SPILL reg slot)
1243 ptext SLIT("\tSPILL"),
1247 ptext SLIT("SLOT") <> parens (int slot)]
1249 pprInstr (RELOAD slot reg)
1251 ptext SLIT("\tRELOAD"),
1253 ptext SLIT("SLOT") <> parens (int slot),
1257 pprInstr (MOV size src dst)
1258 = pprSizeOpOp SLIT("mov") size src dst
1260 pprInstr (MOVZxL I32 src dst) = pprSizeOpOp SLIT("mov") I32 src dst
1261 -- 32-to-64 bit zero extension on x86_64 is accomplished by a simple
1262 -- movl. But we represent it as a MOVZxL instruction, because
1263 -- the reg alloc would tend to throw away a plain reg-to-reg
1264 -- move, and we still want it to do that.
1266 pprInstr (MOVZxL sizes src dst) = pprSizeOpOpCoerce SLIT("movz") sizes I32 src dst
1267 -- zero-extension only needs to extend to 32 bits: on x86_64,
1268 -- the remaining zero-extension to 64 bits is automatic, and the 32-bit
1269 -- instruction is shorter.
1271 pprInstr (MOVSxL sizes src dst) = pprSizeOpOpCoerce SLIT("movs") sizes wordRep src dst
1273 -- here we do some patching, since the physical registers are only set late
1274 -- in the code generation.
1275 pprInstr (LEA size (OpAddr (AddrBaseIndex src1@(EABaseReg reg1) (EAIndex reg2 1) (ImmInt 0))) dst@(OpReg reg3))
1277 = pprSizeOpOp SLIT("add") size (OpReg reg2) dst
1278 pprInstr (LEA size (OpAddr (AddrBaseIndex src1@(EABaseReg reg1) (EAIndex reg2 1) (ImmInt 0))) dst@(OpReg reg3))
1280 = pprSizeOpOp SLIT("add") size (OpReg reg1) dst
1281 pprInstr (LEA size (OpAddr (AddrBaseIndex src1@(EABaseReg reg1) EAIndexNone displ)) dst@(OpReg reg3))
1283 = pprInstr (ADD size (OpImm displ) dst)
1284 pprInstr (LEA size src dst) = pprSizeOpOp SLIT("lea") size src dst
1286 pprInstr (ADD size (OpImm (ImmInt (-1))) dst)
1287 = pprSizeOp SLIT("dec") size dst
1288 pprInstr (ADD size (OpImm (ImmInt 1)) dst)
1289 = pprSizeOp SLIT("inc") size dst
1290 pprInstr (ADD size src dst)
1291 = pprSizeOpOp SLIT("add") size src dst
1292 pprInstr (ADC size src dst)
1293 = pprSizeOpOp SLIT("adc") size src dst
1294 pprInstr (SUB size src dst) = pprSizeOpOp SLIT("sub") size src dst
1295 pprInstr (IMUL size op1 op2) = pprSizeOpOp SLIT("imul") size op1 op2
1297 {- A hack. The Intel documentation says that "The two and three
1298 operand forms [of IMUL] may also be used with unsigned operands
1299 because the lower half of the product is the same regardless if
1300 (sic) the operands are signed or unsigned. The CF and OF flags,
1301 however, cannot be used to determine if the upper half of the
1302 result is non-zero." So there.
1304 pprInstr (AND size src dst) = pprSizeOpOp SLIT("and") size src dst
1305 pprInstr (OR size src dst) = pprSizeOpOp SLIT("or") size src dst
1307 pprInstr (XOR F32 src dst) = pprOpOp SLIT("xorps") F32 src dst
1308 pprInstr (XOR F64 src dst) = pprOpOp SLIT("xorpd") F64 src dst
1309 pprInstr (XOR size src dst) = pprSizeOpOp SLIT("xor") size src dst
1311 pprInstr (NOT size op) = pprSizeOp SLIT("not") size op
1312 pprInstr (NEGI size op) = pprSizeOp SLIT("neg") size op
1314 pprInstr (SHL size src dst) = pprShift SLIT("shl") size src dst
1315 pprInstr (SAR size src dst) = pprShift SLIT("sar") size src dst
1316 pprInstr (SHR size src dst) = pprShift SLIT("shr") size src dst
1318 pprInstr (BT size imm src) = pprSizeImmOp SLIT("bt") size imm src
1320 pprInstr (CMP size src dst)
1321 | isFloatingRep size = pprSizeOpOp SLIT("ucomi") size src dst -- SSE2
1322 | otherwise = pprSizeOpOp SLIT("cmp") size src dst
1324 pprInstr (TEST size src dst) = pprSizeOpOp SLIT("test") size src dst
1325 pprInstr (PUSH size op) = pprSizeOp SLIT("push") size op
1326 pprInstr (POP size op) = pprSizeOp SLIT("pop") size op
1328 -- both unused (SDM):
1329 -- pprInstr PUSHA = ptext SLIT("\tpushal")
1330 -- pprInstr POPA = ptext SLIT("\tpopal")
1332 pprInstr NOP = ptext SLIT("\tnop")
1333 pprInstr (CLTD I32) = ptext SLIT("\tcltd")
1334 pprInstr (CLTD I64) = ptext SLIT("\tcqto")
1336 pprInstr (SETCC cond op) = pprCondInstr SLIT("set") cond (pprOperand I8 op)
1338 pprInstr (JXX cond (BlockId id))
1339 = pprCondInstr SLIT("j") cond (pprCLabel_asm lab)
1340 where lab = mkAsmTempLabel id
1342 pprInstr (JXX_GBL cond imm) = pprCondInstr SLIT("j") cond (pprImm imm)
1344 pprInstr (JMP (OpImm imm)) = (<>) (ptext SLIT("\tjmp ")) (pprImm imm)
1345 pprInstr (JMP op) = (<>) (ptext SLIT("\tjmp *")) (pprOperand wordRep op)
1346 pprInstr (JMP_TBL op ids) = pprInstr (JMP op)
1347 pprInstr (CALL (Left imm) _) = (<>) (ptext SLIT("\tcall ")) (pprImm imm)
1348 pprInstr (CALL (Right reg) _) = (<>) (ptext SLIT("\tcall *")) (pprReg wordRep reg)
1350 pprInstr (IDIV sz op) = pprSizeOp SLIT("idiv") sz op
1351 pprInstr (DIV sz op) = pprSizeOp SLIT("div") sz op
1352 pprInstr (IMUL2 sz op) = pprSizeOp SLIT("imul") sz op
1354 #if x86_64_TARGET_ARCH
1355 pprInstr (MUL size op1 op2) = pprSizeOpOp SLIT("mul") size op1 op2
1357 pprInstr (FDIV size op1 op2) = pprSizeOpOp SLIT("div") size op1 op2
1359 pprInstr (CVTSS2SD from to) = pprRegReg SLIT("cvtss2sd") from to
1360 pprInstr (CVTSD2SS from to) = pprRegReg SLIT("cvtsd2ss") from to
1361 pprInstr (CVTTSS2SIQ from to) = pprOpReg SLIT("cvttss2siq") from to
1362 pprInstr (CVTTSD2SIQ from to) = pprOpReg SLIT("cvttsd2siq") from to
1363 pprInstr (CVTSI2SS from to) = pprOpReg SLIT("cvtsi2ssq") from to
1364 pprInstr (CVTSI2SD from to) = pprOpReg SLIT("cvtsi2sdq") from to
1367 -- FETCHGOT for PIC on ELF platforms
1368 pprInstr (FETCHGOT reg)
1369 = vcat [ ptext SLIT("\tcall 1f"),
1370 hcat [ ptext SLIT("1:\tpopl\t"), pprReg I32 reg ],
1371 hcat [ ptext SLIT("\taddl\t$_GLOBAL_OFFSET_TABLE_+(.-1b), "),
1375 -- FETCHPC for PIC on Darwin/x86
1376 -- get the instruction pointer into a register
1377 -- (Terminology note: the IP is called Program Counter on PPC,
1378 -- and it's a good thing to use the same name on both platforms)
1379 pprInstr (FETCHPC reg)
1380 = vcat [ ptext SLIT("\tcall 1f"),
1381 hcat [ ptext SLIT("1:\tpopl\t"), pprReg I32 reg ]
1388 -- -----------------------------------------------------------------------------
1389 -- i386 floating-point
1391 #if i386_TARGET_ARCH
1392 -- Simulating a flat register set on the x86 FP stack is tricky.
1393 -- you have to free %st(7) before pushing anything on the FP reg stack
1394 -- so as to preclude the possibility of a FP stack overflow exception.
1395 pprInstr g@(GMOV src dst)
1399 = pprG g (hcat [gtab, gpush src 0, gsemi, gpop dst 1])
1401 -- GLD sz addr dst ==> FFREE %st(7) ; FLDsz addr ; FSTP (dst+1)
1402 pprInstr g@(GLD sz addr dst)
1403 = pprG g (hcat [gtab, text "ffree %st(7) ; fld", pprSize sz, gsp,
1404 pprAddr addr, gsemi, gpop dst 1])
1406 -- GST sz src addr ==> FFREE %st(7) ; FLD dst ; FSTPsz addr
1407 pprInstr g@(GST sz src addr)
1408 = pprG g (hcat [gtab, gpush src 0, gsemi,
1409 text "fstp", pprSize sz, gsp, pprAddr addr])
1411 pprInstr g@(GLDZ dst)
1412 = pprG g (hcat [gtab, text "ffree %st(7) ; fldz ; ", gpop dst 1])
1413 pprInstr g@(GLD1 dst)
1414 = pprG g (hcat [gtab, text "ffree %st(7) ; fld1 ; ", gpop dst 1])
1416 pprInstr g@(GFTOI src dst)
1417 = pprInstr (GDTOI src dst)
1418 pprInstr g@(GDTOI src dst)
1419 = pprG g (hcat [gtab, text "subl $4, %esp ; ",
1420 gpush src 0, gsemi, text "fistpl 0(%esp) ; popl ",
1423 pprInstr g@(GITOF src dst)
1424 = pprInstr (GITOD src dst)
1425 pprInstr g@(GITOD src dst)
1426 = pprG g (hcat [gtab, text "pushl ", pprReg I32 src,
1427 text " ; ffree %st(7); fildl (%esp) ; ",
1428 gpop dst 1, text " ; addl $4,%esp"])
1430 {- Gruesome swamp follows. If you're unfortunate enough to have ventured
1431 this far into the jungle AND you give a Rat's Ass (tm) what's going
1432 on, here's the deal. Generate code to do a floating point comparison
1433 of src1 and src2, of kind cond, and set the Zero flag if true.
1435 The complications are to do with handling NaNs correctly. We want the
1436 property that if either argument is NaN, then the result of the
1437 comparison is False ... except if we're comparing for inequality,
1438 in which case the answer is True.
1440 Here's how the general (non-inequality) case works. As an
1441 example, consider generating the an equality test:
1443 pushl %eax -- we need to mess with this
1444 <get src1 to top of FPU stack>
1445 fcomp <src2 location in FPU stack> and pop pushed src1
1446 -- Result of comparison is in FPU Status Register bits
1448 fstsw %ax -- Move FPU Status Reg to %ax
1449 sahf -- move C3 C2 C0 from %ax to integer flag reg
1450 -- now the serious magic begins
1451 setpo %ah -- %ah = if comparable(neither arg was NaN) then 1 else 0
1452 sete %al -- %al = if arg1 == arg2 then 1 else 0
1453 andb %ah,%al -- %al &= %ah
1454 -- so %al == 1 iff (comparable && same); else it holds 0
1455 decb %al -- %al == 0, ZeroFlag=1 iff (comparable && same);
1456 else %al == 0xFF, ZeroFlag=0
1457 -- the zero flag is now set as we desire.
1460 The special case of inequality differs thusly:
1462 setpe %ah -- %ah = if incomparable(either arg was NaN) then 1 else 0
1463 setne %al -- %al = if arg1 /= arg2 then 1 else 0
1464 orb %ah,%al -- %al = if (incomparable || different) then 1 else 0
1465 decb %al -- if (incomparable || different) then (%al == 0, ZF=1)
1466 else (%al == 0xFF, ZF=0)
1468 pprInstr g@(GCMP cond src1 src2)
1469 | case cond of { NE -> True; other -> False }
1471 hcat [gtab, text "pushl %eax ; ",gpush src1 0],
1472 hcat [gtab, text "fcomp ", greg src2 1,
1473 text "; fstsw %ax ; sahf ; setpe %ah"],
1474 hcat [gtab, text "setne %al ; ",
1475 text "orb %ah,%al ; decb %al ; popl %eax"]
1479 hcat [gtab, text "pushl %eax ; ",gpush src1 0],
1480 hcat [gtab, text "fcomp ", greg src2 1,
1481 text "; fstsw %ax ; sahf ; setpo %ah"],
1482 hcat [gtab, text "set", pprCond (fix_FP_cond cond), text " %al ; ",
1483 text "andb %ah,%al ; decb %al ; popl %eax"]
1486 {- On the 486, the flags set by FP compare are the unsigned ones!
1487 (This looks like a HACK to me. WDP 96/03)
1489 fix_FP_cond :: Cond -> Cond
1490 fix_FP_cond GE = GEU
1491 fix_FP_cond GTT = GU
1492 fix_FP_cond LTT = LU
1493 fix_FP_cond LE = LEU
1494 fix_FP_cond EQQ = EQQ
1496 -- there should be no others
1499 pprInstr g@(GABS sz src dst)
1500 = pprG g (hcat [gtab, gpush src 0, text " ; fabs ; ", gpop dst 1])
1501 pprInstr g@(GNEG sz src dst)
1502 = pprG g (hcat [gtab, gpush src 0, text " ; fchs ; ", gpop dst 1])
1504 pprInstr g@(GSQRT sz src dst)
1505 = pprG g (hcat [gtab, gpush src 0, text " ; fsqrt"] $$
1506 hcat [gtab, gcoerceto sz, gpop dst 1])
1507 pprInstr g@(GSIN sz src dst)
1508 = pprG g (hcat [gtab, gpush src 0, text " ; fsin"] $$
1509 hcat [gtab, gcoerceto sz, gpop dst 1])
1510 pprInstr g@(GCOS sz src dst)
1511 = pprG g (hcat [gtab, gpush src 0, text " ; fcos"] $$
1512 hcat [gtab, gcoerceto sz, gpop dst 1])
1513 pprInstr g@(GTAN sz src dst)
1514 = pprG g (hcat [gtab, text "ffree %st(6) ; ",
1515 gpush src 0, text " ; fptan ; ",
1516 text " fstp %st(0)"] $$
1517 hcat [gtab, gcoerceto sz, gpop dst 1])
1519 -- In the translations for GADD, GMUL, GSUB and GDIV,
1520 -- the first two cases are mere optimisations. The otherwise clause
1521 -- generates correct code under all circumstances.
1523 pprInstr g@(GADD sz src1 src2 dst)
1525 = pprG g (text "\t#GADD-xxxcase1" $$
1526 hcat [gtab, gpush src2 0,
1527 text " ; faddp %st(0),", greg src1 1])
1529 = pprG g (text "\t#GADD-xxxcase2" $$
1530 hcat [gtab, gpush src1 0,
1531 text " ; faddp %st(0),", greg src2 1])
1533 = pprG g (hcat [gtab, gpush src1 0,
1534 text " ; fadd ", greg src2 1, text ",%st(0)",
1538 pprInstr g@(GMUL sz src1 src2 dst)
1540 = pprG g (text "\t#GMUL-xxxcase1" $$
1541 hcat [gtab, gpush src2 0,
1542 text " ; fmulp %st(0),", greg src1 1])
1544 = pprG g (text "\t#GMUL-xxxcase2" $$
1545 hcat [gtab, gpush src1 0,
1546 text " ; fmulp %st(0),", greg src2 1])
1548 = pprG g (hcat [gtab, gpush src1 0,
1549 text " ; fmul ", greg src2 1, text ",%st(0)",
1553 pprInstr g@(GSUB sz src1 src2 dst)
1555 = pprG g (text "\t#GSUB-xxxcase1" $$
1556 hcat [gtab, gpush src2 0,
1557 text " ; fsubrp %st(0),", greg src1 1])
1559 = pprG g (text "\t#GSUB-xxxcase2" $$
1560 hcat [gtab, gpush src1 0,
1561 text " ; fsubp %st(0),", greg src2 1])
1563 = pprG g (hcat [gtab, gpush src1 0,
1564 text " ; fsub ", greg src2 1, text ",%st(0)",
1568 pprInstr g@(GDIV sz src1 src2 dst)
1570 = pprG g (text "\t#GDIV-xxxcase1" $$
1571 hcat [gtab, gpush src2 0,
1572 text " ; fdivrp %st(0),", greg src1 1])
1574 = pprG g (text "\t#GDIV-xxxcase2" $$
1575 hcat [gtab, gpush src1 0,
1576 text " ; fdivp %st(0),", greg src2 1])
1578 = pprG g (hcat [gtab, gpush src1 0,
1579 text " ; fdiv ", greg src2 1, text ",%st(0)",
1584 = vcat [ ptext SLIT("\tffree %st(0) ;ffree %st(1) ;ffree %st(2) ;ffree %st(3)"),
1585 ptext SLIT("\tffree %st(4) ;ffree %st(5) ;ffree %st(6) ;ffree %st(7)")
1588 --------------------------
1590 -- coerce %st(0) to the specified size
1591 gcoerceto F64 = empty
1592 gcoerceto F32 = empty --text "subl $4,%esp ; fstps (%esp) ; flds (%esp) ; addl $4,%esp ; "
1595 = hcat [text "ffree %st(7) ; fld ", greg reg offset]
1597 = hcat [text "fstp ", greg reg offset]
1599 greg reg offset = text "%st(" <> int (gregno reg - 8+offset) <> char ')'
1604 gregno (RealReg i) = i
1605 gregno other = --pprPanic "gregno" (ppr other)
1606 999 -- bogus; only needed for debug printing
1608 pprG :: Instr -> Doc -> Doc
1610 = (char '#' <> pprGInstr fake) $$ actual
1612 pprGInstr (GMOV src dst) = pprSizeRegReg SLIT("gmov") F64 src dst
1613 pprGInstr (GLD sz src dst) = pprSizeAddrReg SLIT("gld") sz src dst
1614 pprGInstr (GST sz src dst) = pprSizeRegAddr SLIT("gst") sz src dst
1616 pprGInstr (GLDZ dst) = pprSizeReg SLIT("gldz") F64 dst
1617 pprGInstr (GLD1 dst) = pprSizeReg SLIT("gld1") F64 dst
1619 pprGInstr (GFTOI src dst) = pprSizeSizeRegReg SLIT("gftoi") F32 I32 src dst
1620 pprGInstr (GDTOI src dst) = pprSizeSizeRegReg SLIT("gdtoi") F64 I32 src dst
1622 pprGInstr (GITOF src dst) = pprSizeSizeRegReg SLIT("gitof") I32 F32 src dst
1623 pprGInstr (GITOD src dst) = pprSizeSizeRegReg SLIT("gitod") I32 F64 src dst
1625 pprGInstr (GCMP co src dst) = pprCondRegReg SLIT("gcmp_") F64 co src dst
1626 pprGInstr (GABS sz src dst) = pprSizeRegReg SLIT("gabs") sz src dst
1627 pprGInstr (GNEG sz src dst) = pprSizeRegReg SLIT("gneg") sz src dst
1628 pprGInstr (GSQRT sz src dst) = pprSizeRegReg SLIT("gsqrt") sz src dst
1629 pprGInstr (GSIN sz src dst) = pprSizeRegReg SLIT("gsin") sz src dst
1630 pprGInstr (GCOS sz src dst) = pprSizeRegReg SLIT("gcos") sz src dst
1631 pprGInstr (GTAN sz src dst) = pprSizeRegReg SLIT("gtan") sz src dst
1633 pprGInstr (GADD sz src1 src2 dst) = pprSizeRegRegReg SLIT("gadd") sz src1 src2 dst
1634 pprGInstr (GSUB sz src1 src2 dst) = pprSizeRegRegReg SLIT("gsub") sz src1 src2 dst
1635 pprGInstr (GMUL sz src1 src2 dst) = pprSizeRegRegReg SLIT("gmul") sz src1 src2 dst
1636 pprGInstr (GDIV sz src1 src2 dst) = pprSizeRegRegReg SLIT("gdiv") sz src1 src2 dst
1639 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
1641 -- Continue with I386-only printing bits and bobs:
1643 pprDollImm :: Imm -> Doc
1645 pprDollImm i = ptext SLIT("$") <> pprImm i
1647 pprOperand :: MachRep -> Operand -> Doc
1648 pprOperand s (OpReg r) = pprReg s r
1649 pprOperand s (OpImm i) = pprDollImm i
1650 pprOperand s (OpAddr ea) = pprAddr ea
1652 pprMnemonic_ :: LitString -> Doc
1654 char '\t' <> ptext name <> space
1656 pprMnemonic :: LitString -> MachRep -> Doc
1657 pprMnemonic name size =
1658 char '\t' <> ptext name <> pprSize size <> space
1660 pprSizeImmOp :: LitString -> MachRep -> Imm -> Operand -> Doc
1661 pprSizeImmOp name size imm op1
1663 pprMnemonic name size,
1670 pprSizeOp :: LitString -> MachRep -> Operand -> Doc
1671 pprSizeOp name size op1
1673 pprMnemonic name size,
1677 pprSizeOpOp :: LitString -> MachRep -> Operand -> Operand -> Doc
1678 pprSizeOpOp name size op1 op2
1680 pprMnemonic name size,
1681 pprOperand size op1,
1686 pprOpOp :: LitString -> MachRep -> Operand -> Operand -> Doc
1687 pprOpOp name size op1 op2
1690 pprOperand size op1,
1695 pprSizeReg :: LitString -> MachRep -> Reg -> Doc
1696 pprSizeReg name size reg1
1698 pprMnemonic name size,
1702 pprSizeRegReg :: LitString -> MachRep -> Reg -> Reg -> Doc
1703 pprSizeRegReg name size reg1 reg2
1705 pprMnemonic name size,
1711 pprRegReg :: LitString -> Reg -> Reg -> Doc
1712 pprRegReg name reg1 reg2
1715 pprReg wordRep reg1,
1720 pprOpReg :: LitString -> Operand -> Reg -> Doc
1721 pprOpReg name op1 reg2
1724 pprOperand wordRep op1,
1729 pprCondRegReg :: LitString -> MachRep -> Cond -> Reg -> Reg -> Doc
1730 pprCondRegReg name size cond reg1 reg2
1741 pprSizeSizeRegReg :: LitString -> MachRep -> MachRep -> Reg -> Reg -> Doc
1742 pprSizeSizeRegReg name size1 size2 reg1 reg2
1755 pprSizeRegRegReg :: LitString -> MachRep -> Reg -> Reg -> Reg -> Doc
1756 pprSizeRegRegReg name size reg1 reg2 reg3
1758 pprMnemonic name size,
1766 pprSizeAddrReg :: LitString -> MachRep -> AddrMode -> Reg -> Doc
1767 pprSizeAddrReg name size op dst
1769 pprMnemonic name size,
1775 pprSizeRegAddr :: LitString -> MachRep -> Reg -> AddrMode -> Doc
1776 pprSizeRegAddr name size src op
1778 pprMnemonic name size,
1784 pprShift :: LitString -> MachRep -> Operand -> Operand -> Doc
1785 pprShift name size src dest
1787 pprMnemonic name size,
1788 pprOperand I8 src, -- src is 8-bit sized
1790 pprOperand size dest
1793 pprSizeOpOpCoerce :: LitString -> MachRep -> MachRep -> Operand -> Operand -> Doc
1794 pprSizeOpOpCoerce name size1 size2 op1 op2
1795 = hcat [ char '\t', ptext name, pprSize size1, pprSize size2, space,
1796 pprOperand size1 op1,
1798 pprOperand size2 op2
1801 pprCondInstr :: LitString -> Cond -> Doc -> Doc
1802 pprCondInstr name cond arg
1803 = hcat [ char '\t', ptext name, pprCond cond, space, arg]
1805 #endif /* i386_TARGET_ARCH */
1808 -- ------------------------------------------------------------------------------- pprInstr for a SPARC
1810 #if sparc_TARGET_ARCH
1812 -- a clumsy hack for now, to handle possible double alignment problems
1814 -- even clumsier, to allow for RegReg regs that show when doing indexed
1815 -- reads (bytearrays).
1818 pprInstr (SPILL reg slot)
1820 ptext SLIT("\tSPILL"),
1824 ptext SLIT("SLOT") <> parens (int slot)]
1826 pprInstr (RELOAD slot reg)
1828 ptext SLIT("\tRELOAD"),
1830 ptext SLIT("SLOT") <> parens (int slot),
1834 -- Translate to the following:
1837 -- ld [g1+4],%f(n+1)
1838 -- sub g1,g2,g1 -- to restore g1
1840 pprInstr (LD F64 (AddrRegReg g1 g2) reg)
1842 hcat [ptext SLIT("\tadd\t"), pprReg g1,comma,pprReg g2,comma,pprReg g1],
1843 hcat [pp_ld_lbracket, pprReg g1, pp_rbracket_comma, pprReg reg],
1844 hcat [pp_ld_lbracket, pprReg g1, ptext SLIT("+4]"), comma, pprReg (fPair reg)],
1845 hcat [ptext SLIT("\tsub\t"), pprReg g1,comma,pprReg g2,comma,pprReg g1]
1850 -- ld [addr+4],%f(n+1)
1851 pprInstr (LD F64 addr reg) | isJust off_addr
1853 hcat [pp_ld_lbracket, pprAddr addr, pp_rbracket_comma, pprReg reg],
1854 hcat [pp_ld_lbracket, pprAddr addr2, pp_rbracket_comma,pprReg (fPair reg)]
1857 off_addr = addrOffset addr 4
1858 addr2 = case off_addr of Just x -> x
1861 pprInstr (LD size addr reg)
1872 -- The same clumsy hack as above
1874 -- Translate to the following:
1877 -- st %f(n+1),[g1+4]
1878 -- sub g1,g2,g1 -- to restore g1
1879 pprInstr (ST F64 reg (AddrRegReg g1 g2))
1881 hcat [ptext SLIT("\tadd\t"), pprReg g1,comma,pprReg g2,comma,pprReg g1],
1882 hcat [ptext SLIT("\tst\t"), pprReg reg, pp_comma_lbracket,
1884 hcat [ptext SLIT("\tst\t"), pprReg (fPair reg), pp_comma_lbracket,
1885 pprReg g1, ptext SLIT("+4]")],
1886 hcat [ptext SLIT("\tsub\t"), pprReg g1,comma,pprReg g2,comma,pprReg g1]
1891 -- st %f(n+1),[addr+4]
1892 pprInstr (ST F64 reg addr) | isJust off_addr
1894 hcat [ptext SLIT("\tst\t"), pprReg reg, pp_comma_lbracket,
1895 pprAddr addr, rbrack],
1896 hcat [ptext SLIT("\tst\t"), pprReg (fPair reg), pp_comma_lbracket,
1897 pprAddr addr2, rbrack]
1900 off_addr = addrOffset addr 4
1901 addr2 = case off_addr of Just x -> x
1903 -- no distinction is made between signed and unsigned bytes on stores for the
1904 -- Sparc opcodes (at least I cannot see any, and gas is nagging me --SOF),
1905 -- so we call a special-purpose pprSize for ST..
1907 pprInstr (ST size reg addr)
1918 pprInstr (ADD x cc reg1 ri reg2)
1919 | not x && not cc && riZero ri
1920 = hcat [ ptext SLIT("\tmov\t"), pprReg reg1, comma, pprReg reg2 ]
1922 = pprRegRIReg (if x then SLIT("addx") else SLIT("add")) cc reg1 ri reg2
1924 pprInstr (SUB x cc reg1 ri reg2)
1925 | not x && cc && reg2 == g0
1926 = hcat [ ptext SLIT("\tcmp\t"), pprReg reg1, comma, pprRI ri ]
1927 | not x && not cc && riZero ri
1928 = hcat [ ptext SLIT("\tmov\t"), pprReg reg1, comma, pprReg reg2 ]
1930 = pprRegRIReg (if x then SLIT("subx") else SLIT("sub")) cc reg1 ri reg2
1932 pprInstr (AND b reg1 ri reg2) = pprRegRIReg SLIT("and") b reg1 ri reg2
1933 pprInstr (ANDN b reg1 ri reg2) = pprRegRIReg SLIT("andn") b reg1 ri reg2
1935 pprInstr (OR b reg1 ri reg2)
1936 | not b && reg1 == g0
1937 = let doit = hcat [ ptext SLIT("\tmov\t"), pprRI ri, comma, pprReg reg2 ]
1939 RIReg rrr | rrr == reg2 -> empty
1942 = pprRegRIReg SLIT("or") b reg1 ri reg2
1944 pprInstr (ORN b reg1 ri reg2) = pprRegRIReg SLIT("orn") b reg1 ri reg2
1946 pprInstr (XOR b reg1 ri reg2) = pprRegRIReg SLIT("xor") b reg1 ri reg2
1947 pprInstr (XNOR b reg1 ri reg2) = pprRegRIReg SLIT("xnor") b reg1 ri reg2
1949 pprInstr (SLL reg1 ri reg2) = pprRegRIReg SLIT("sll") False reg1 ri reg2
1950 pprInstr (SRL reg1 ri reg2) = pprRegRIReg SLIT("srl") False reg1 ri reg2
1951 pprInstr (SRA reg1 ri reg2) = pprRegRIReg SLIT("sra") False reg1 ri reg2
1953 pprInstr (RDY rd) = ptext SLIT("\trd\t%y,") <> pprReg rd
1954 pprInstr (SMUL b reg1 ri reg2) = pprRegRIReg SLIT("smul") b reg1 ri reg2
1955 pprInstr (UMUL b reg1 ri reg2) = pprRegRIReg SLIT("umul") b reg1 ri reg2
1957 pprInstr (SETHI imm reg)
1959 ptext SLIT("\tsethi\t"),
1965 pprInstr NOP = ptext SLIT("\tnop")
1967 pprInstr (FABS F32 reg1 reg2) = pprSizeRegReg SLIT("fabs") F32 reg1 reg2
1968 pprInstr (FABS F64 reg1 reg2)
1969 = (<>) (pprSizeRegReg SLIT("fabs") F32 reg1 reg2)
1970 (if (reg1 == reg2) then empty
1971 else (<>) (char '\n')
1972 (pprSizeRegReg SLIT("fmov") F32 (fPair reg1) (fPair reg2)))
1974 pprInstr (FADD size reg1 reg2 reg3)
1975 = pprSizeRegRegReg SLIT("fadd") size reg1 reg2 reg3
1976 pprInstr (FCMP e size reg1 reg2)
1977 = pprSizeRegReg (if e then SLIT("fcmpe") else SLIT("fcmp")) size reg1 reg2
1978 pprInstr (FDIV size reg1 reg2 reg3)
1979 = pprSizeRegRegReg SLIT("fdiv") size reg1 reg2 reg3
1981 pprInstr (FMOV F32 reg1 reg2) = pprSizeRegReg SLIT("fmov") F32 reg1 reg2
1982 pprInstr (FMOV F64 reg1 reg2)
1983 = (<>) (pprSizeRegReg SLIT("fmov") F32 reg1 reg2)
1984 (if (reg1 == reg2) then empty
1985 else (<>) (char '\n')
1986 (pprSizeRegReg SLIT("fmov") F32 (fPair reg1) (fPair reg2)))
1988 pprInstr (FMUL size reg1 reg2 reg3)
1989 = pprSizeRegRegReg SLIT("fmul") size reg1 reg2 reg3
1991 pprInstr (FNEG F32 reg1 reg2) = pprSizeRegReg SLIT("fneg") F32 reg1 reg2
1992 pprInstr (FNEG F64 reg1 reg2)
1993 = (<>) (pprSizeRegReg SLIT("fneg") F32 reg1 reg2)
1994 (if (reg1 == reg2) then empty
1995 else (<>) (char '\n')
1996 (pprSizeRegReg SLIT("fmov") F32 (fPair reg1) (fPair reg2)))
1998 pprInstr (FSQRT size reg1 reg2) = pprSizeRegReg SLIT("fsqrt") size reg1 reg2
1999 pprInstr (FSUB size reg1 reg2 reg3) = pprSizeRegRegReg SLIT("fsub") size reg1 reg2 reg3
2000 pprInstr (FxTOy size1 size2 reg1 reg2)
2007 F64 -> SLIT("dto")),
2012 F64 -> SLIT("d\t")),
2013 pprReg reg1, comma, pprReg reg2
2017 pprInstr (BI cond b lab)
2019 ptext SLIT("\tb"), pprCond cond,
2020 if b then pp_comma_a else empty,
2025 pprInstr (BF cond b lab)
2027 ptext SLIT("\tfb"), pprCond cond,
2028 if b then pp_comma_a else empty,
2033 pprInstr (JMP addr) = (<>) (ptext SLIT("\tjmp\t")) (pprAddr addr)
2035 pprInstr (CALL (Left imm) n _)
2036 = hcat [ ptext SLIT("\tcall\t"), pprImm imm, comma, int n ]
2037 pprInstr (CALL (Right reg) n _)
2038 = hcat [ ptext SLIT("\tcall\t"), pprReg reg, comma, int n ]
2041 pprRI (RIReg r) = pprReg r
2042 pprRI (RIImm r) = pprImm r
2044 pprSizeRegReg :: LitString -> MachRep -> Reg -> Reg -> Doc
2045 pprSizeRegReg name size reg1 reg2
2050 F32 -> ptext SLIT("s\t")
2051 F64 -> ptext SLIT("d\t")),
2057 pprSizeRegRegReg :: LitString -> MachRep -> Reg -> Reg -> Reg -> Doc
2058 pprSizeRegRegReg name size reg1 reg2 reg3
2063 F32 -> ptext SLIT("s\t")
2064 F64 -> ptext SLIT("d\t")),
2072 pprRegRIReg :: LitString -> Bool -> Reg -> RI -> Reg -> Doc
2073 pprRegRIReg name b reg1 ri reg2
2077 if b then ptext SLIT("cc\t") else char '\t',
2085 pprRIReg :: LitString -> Bool -> RI -> Reg -> Doc
2086 pprRIReg name b ri reg1
2090 if b then ptext SLIT("cc\t") else char '\t',
2096 pp_ld_lbracket = ptext SLIT("\tld\t[")
2097 pp_rbracket_comma = text "],"
2098 pp_comma_lbracket = text ",["
2099 pp_comma_a = text ",a"
2101 #endif /* sparc_TARGET_ARCH */
2104 -- -----------------------------------------------------------------------------
2105 -- pprInstr for PowerPC
2107 #if powerpc_TARGET_ARCH
2109 pprInstr (SPILL reg slot)
2111 ptext SLIT("\tSPILL"),
2115 ptext SLIT("SLOT") <> parens (int slot)]
2117 pprInstr (RELOAD slot reg)
2119 ptext SLIT("\tRELOAD"),
2121 ptext SLIT("SLOT") <> parens (int slot),
2125 pprInstr (LD sz reg addr) = hcat [
2134 case addr of AddrRegImm _ _ -> empty
2135 AddrRegReg _ _ -> char 'x',
2141 pprInstr (LA sz reg addr) = hcat [
2150 case addr of AddrRegImm _ _ -> empty
2151 AddrRegReg _ _ -> char 'x',
2157 pprInstr (ST sz reg addr) = hcat [
2161 case addr of AddrRegImm _ _ -> empty
2162 AddrRegReg _ _ -> char 'x',
2168 pprInstr (STU sz reg addr) = hcat [
2173 case addr of AddrRegImm _ _ -> empty
2174 AddrRegReg _ _ -> char 'x',
2179 pprInstr (LIS reg imm) = hcat [
2187 pprInstr (LI reg imm) = hcat [
2195 pprInstr (MR reg1 reg2)
2196 | reg1 == reg2 = empty
2197 | otherwise = hcat [
2199 case regClass reg1 of
2200 RcInteger -> ptext SLIT("mr")
2201 _ -> ptext SLIT("fmr"),
2207 pprInstr (CMP sz reg ri) = hcat [
2223 pprInstr (CMPL sz reg ri) = hcat [
2239 pprInstr (BCC cond (BlockId id)) = hcat [
2246 where lbl = mkAsmTempLabel id
2248 pprInstr (BCCFAR cond (BlockId id)) = vcat [
2251 pprCond (condNegate cond),
2255 ptext SLIT("\tb\t"),
2259 where lbl = mkAsmTempLabel id
2261 pprInstr (JMP lbl) = hcat [ -- an alias for b that takes a CLabel
2268 pprInstr (MTCTR reg) = hcat [
2270 ptext SLIT("mtctr"),
2274 pprInstr (BCTR _) = hcat [
2278 pprInstr (BL lbl _) = hcat [
2279 ptext SLIT("\tbl\t"),
2282 pprInstr (BCTRL _) = hcat [
2286 pprInstr (ADD reg1 reg2 ri) = pprLogic SLIT("add") reg1 reg2 ri
2287 pprInstr (ADDIS reg1 reg2 imm) = hcat [
2289 ptext SLIT("addis"),
2298 pprInstr (ADDC reg1 reg2 reg3) = pprLogic SLIT("addc") reg1 reg2 (RIReg reg3)
2299 pprInstr (ADDE reg1 reg2 reg3) = pprLogic SLIT("adde") reg1 reg2 (RIReg reg3)
2300 pprInstr (SUBF reg1 reg2 reg3) = pprLogic SLIT("subf") reg1 reg2 (RIReg reg3)
2301 pprInstr (MULLW reg1 reg2 ri@(RIReg _)) = pprLogic SLIT("mullw") reg1 reg2 ri
2302 pprInstr (MULLW reg1 reg2 ri@(RIImm _)) = pprLogic SLIT("mull") reg1 reg2 ri
2303 pprInstr (DIVW reg1 reg2 reg3) = pprLogic SLIT("divw") reg1 reg2 (RIReg reg3)
2304 pprInstr (DIVWU reg1 reg2 reg3) = pprLogic SLIT("divwu") reg1 reg2 (RIReg reg3)
2306 pprInstr (MULLW_MayOflo reg1 reg2 reg3) = vcat [
2307 hcat [ ptext SLIT("\tmullwo\t"), pprReg reg1, ptext SLIT(", "),
2308 pprReg reg2, ptext SLIT(", "),
2310 hcat [ ptext SLIT("\tmfxer\t"), pprReg reg1 ],
2311 hcat [ ptext SLIT("\trlwinm\t"), pprReg reg1, ptext SLIT(", "),
2312 pprReg reg1, ptext SLIT(", "),
2313 ptext SLIT("2, 31, 31") ]
2316 -- for some reason, "andi" doesn't exist.
2317 -- we'll use "andi." instead.
2318 pprInstr (AND reg1 reg2 (RIImm imm)) = hcat [
2320 ptext SLIT("andi."),
2328 pprInstr (AND reg1 reg2 ri) = pprLogic SLIT("and") reg1 reg2 ri
2330 pprInstr (OR reg1 reg2 ri) = pprLogic SLIT("or") reg1 reg2 ri
2331 pprInstr (XOR reg1 reg2 ri) = pprLogic SLIT("xor") reg1 reg2 ri
2333 pprInstr (XORIS reg1 reg2 imm) = hcat [
2335 ptext SLIT("xoris"),
2344 pprInstr (EXTS sz reg1 reg2) = hcat [
2354 pprInstr (NEG reg1 reg2) = pprUnary SLIT("neg") reg1 reg2
2355 pprInstr (NOT reg1 reg2) = pprUnary SLIT("not") reg1 reg2
2357 pprInstr (SLW reg1 reg2 ri) = pprLogic SLIT("slw") reg1 reg2 (limitShiftRI ri)
2358 pprInstr (SRW reg1 reg2 ri) = pprLogic SLIT("srw") reg1 reg2 (limitShiftRI ri)
2359 pprInstr (SRAW reg1 reg2 ri) = pprLogic SLIT("sraw") reg1 reg2 (limitShiftRI ri)
2360 pprInstr (RLWINM reg1 reg2 sh mb me) = hcat [
2361 ptext SLIT("\trlwinm\t"),
2373 pprInstr (FADD sz reg1 reg2 reg3) = pprBinaryF SLIT("fadd") sz reg1 reg2 reg3
2374 pprInstr (FSUB sz reg1 reg2 reg3) = pprBinaryF SLIT("fsub") sz reg1 reg2 reg3
2375 pprInstr (FMUL sz reg1 reg2 reg3) = pprBinaryF SLIT("fmul") sz reg1 reg2 reg3
2376 pprInstr (FDIV sz reg1 reg2 reg3) = pprBinaryF SLIT("fdiv") sz reg1 reg2 reg3
2377 pprInstr (FNEG reg1 reg2) = pprUnary SLIT("fneg") reg1 reg2
2379 pprInstr (FCMP reg1 reg2) = hcat [
2381 ptext SLIT("fcmpu\tcr0, "),
2382 -- Note: we're using fcmpu, not fcmpo
2383 -- The difference is with fcmpo, compare with NaN is an invalid operation.
2384 -- We don't handle invalid fp ops, so we don't care
2390 pprInstr (FCTIWZ reg1 reg2) = pprUnary SLIT("fctiwz") reg1 reg2
2391 pprInstr (FRSP reg1 reg2) = pprUnary SLIT("frsp") reg1 reg2
2393 pprInstr (CRNOR dst src1 src2) = hcat [
2394 ptext SLIT("\tcrnor\t"),
2402 pprInstr (MFCR reg) = hcat [
2409 pprInstr (MFLR reg) = hcat [
2416 pprInstr (FETCHPC reg) = vcat [
2417 ptext SLIT("\tbcl\t20,31,1f"),
2418 hcat [ ptext SLIT("1:\tmflr\t"), pprReg reg ]
2421 pprInstr LWSYNC = ptext SLIT("\tlwsync")
2423 pprInstr _ = panic "pprInstr (ppc)"
2425 pprLogic op reg1 reg2 ri = hcat [
2430 RIImm _ -> char 'i',
2439 pprUnary op reg1 reg2 = hcat [
2448 pprBinaryF op sz reg1 reg2 reg3 = hcat [
2461 pprRI (RIReg r) = pprReg r
2462 pprRI (RIImm r) = pprImm r
2464 pprFSize F64 = empty
2465 pprFSize F32 = char 's'
2467 -- limit immediate argument for shift instruction to range 0..32
2468 -- (yes, the maximum is really 32, not 31)
2469 limitShiftRI :: RI -> RI
2470 limitShiftRI (RIImm (ImmInt i)) | i > 32 || i < 0 = RIImm (ImmInt 32)
2473 #endif /* powerpc_TARGET_ARCH */
2476 -- -----------------------------------------------------------------------------
2477 -- Converting floating-point literals to integrals for printing
2479 castFloatToWord8Array :: STUArray s Int Float -> ST s (STUArray s Int Word8)
2480 castFloatToWord8Array = castSTUArray
2482 castDoubleToWord8Array :: STUArray s Int Double -> ST s (STUArray s Int Word8)
2483 castDoubleToWord8Array = castSTUArray
2485 -- floatToBytes and doubleToBytes convert to the host's byte
2486 -- order. Providing that we're not cross-compiling for a
2487 -- target with the opposite endianness, this should work ok
2490 -- ToDo: this stuff is very similar to the shenanigans in PprAbs,
2491 -- could they be merged?
2493 floatToBytes :: Float -> [Int]
2496 arr <- newArray_ ((0::Int),3)
2498 arr <- castFloatToWord8Array arr
2499 i0 <- readArray arr 0
2500 i1 <- readArray arr 1
2501 i2 <- readArray arr 2
2502 i3 <- readArray arr 3
2503 return (map fromIntegral [i0,i1,i2,i3])
2506 doubleToBytes :: Double -> [Int]
2509 arr <- newArray_ ((0::Int),7)
2511 arr <- castDoubleToWord8Array arr
2512 i0 <- readArray arr 0
2513 i1 <- readArray arr 1
2514 i2 <- readArray arr 2
2515 i3 <- readArray arr 3
2516 i4 <- readArray arr 4
2517 i5 <- readArray arr 5
2518 i6 <- readArray arr 6
2519 i7 <- readArray arr 7
2520 return (map fromIntegral [i0,i1,i2,i3,i4,i5,i6,i7])