1 {-# OPTIONS -fno-warn-missing-signatures #-}
2 -- | Graph coloring register allocator.
4 -- TODO: The colors in graphviz graphs for x86_64 and ppc could be nicer.
7 module RegAlloc.Graph.Main (
13 import qualified GraphColor as Color
14 import RegAlloc.Liveness
15 import RegAlloc.Graph.Spill
16 import RegAlloc.Graph.SpillClean
17 import RegAlloc.Graph.SpillCost
18 import RegAlloc.Graph.Stats
19 import RegAlloc.Graph.TrivColorable
37 -- | The maximum number of build\/spill cycles we'll allow.
38 -- We should only need 3 or 4 cycles tops.
39 -- If we run for any longer than this we're probably in an infinite loop,
40 -- It's probably better just to bail out and report a bug at this stage.
45 -- | The top level of the graph coloring register allocator.
47 :: (Outputable instr, Instruction instr)
49 -> UniqFM (UniqSet RealReg) -- ^ the registers we can use for allocation
50 -> UniqSet Int -- ^ the set of available spill slots.
51 -> [LiveCmmTop instr] -- ^ code annotated with liveness information.
52 -> UniqSM ( [NatCmmTop instr], [RegAllocStats instr] )
53 -- ^ code with registers allocated and stats for each stage of
56 regAlloc dflags regsFree slotsFree code
58 -- TODO: the regClass function is currently hard coded to the default target
59 -- architecture. Would prefer to determine this from dflags.
60 -- There are other uses of targetRegClass later in this module.
61 let triv = trivColorable
62 targetVirtualRegSqueeze
65 (code_final, debug_codeGraphs, _)
66 <- regAlloc_spin dflags 0
68 regsFree slotsFree [] code
71 , reverse debug_codeGraphs )
76 (triv :: Color.Triv VirtualReg RegClass RealReg)
77 (regsFree :: UniqFM (UniqSet RealReg))
82 -- if any of these dump flags are turned on we want to hang on to
83 -- intermediate structures in the allocator - otherwise tell the
84 -- allocator to ditch them early so we don't end up creating space leaks.
86 [ dopt Opt_D_dump_asm_regalloc_stages dflags
87 , dopt Opt_D_dump_asm_stats dflags
88 , dopt Opt_D_dump_asm_conflicts dflags ]
90 -- check that we're not running off down the garden path.
91 when (spinCount > maxSpinCount)
92 $ pprPanic "regAlloc_spin: max build/spill cycle count exceeded."
93 ( text "It looks like the register allocator is stuck in an infinite loop."
94 $$ text "max cycles = " <> int maxSpinCount
95 $$ text "regsFree = " <> (hcat $ punctuate space $ map ppr
96 $ uniqSetToList $ unionManyUniqSets $ eltsUFM regsFree)
97 $$ text "slotsFree = " <> ppr (sizeUniqSet slotsFree))
99 -- build a conflict graph from the code.
100 (graph :: Color.Graph VirtualReg RegClass RealReg)
101 <- {-# SCC "BuildGraph" #-} buildGraph code
104 -- We really do want the graph to be fully evaluated _before_ we start coloring.
105 -- If we don't do this now then when the call to Color.colorGraph forces bits of it,
106 -- the heap will be filled with half evaluated pieces of graph and zillions of apply thunks.
108 seqGraph graph `seq` return ()
111 -- build a map of the cost of spilling each instruction
112 -- this will only actually be computed if we have to spill something.
113 let spillCosts = foldl' plusSpillCostInfo zeroSpillCostInfo
114 $ map slurpSpillCostInfo code
116 -- the function to choose regs to leave uncolored
117 let spill = chooseSpill spillCosts
119 -- record startup state
122 then Just $ RegAllocStatsStart
125 , raSpillCosts = spillCosts }
128 -- try and color the graph
129 let (graph_colored, rsSpill, rmCoalesce)
130 = {-# SCC "ColorGraph" #-}
132 (dopt Opt_RegsIterative dflags)
134 regsFree triv spill graph
136 -- rewrite regs in the code that have been coalesced
138 | RegVirtual vr <- reg
139 = case lookupUFM rmCoalesce vr of
140 Just vr' -> patchF (RegVirtual vr')
147 = map (patchEraseLive patchF) code
150 -- see if we've found a coloring
151 if isEmptyUniqSet rsSpill
153 -- if -fasm-lint is turned on then validate the graph
154 let graph_colored_lint =
155 if dopt Opt_DoAsmLinting dflags
156 then Color.validateGraph (text "")
157 True -- require all nodes to be colored
161 -- patch the registers using the info in the graph
162 let code_patched = map (patchRegsFromGraph graph_colored_lint) code_coalesced
164 -- clean out unneeded SPILL/RELOADs
165 let code_spillclean = map cleanSpills code_patched
167 -- strip off liveness information,
168 -- and rewrite SPILL/RELOAD pseudos into real instructions along the way
169 let code_final = map stripLive code_spillclean
171 -- record what happened in this stage for debugging
176 , raGraphColored = graph_colored_lint
177 , raCoalesced = rmCoalesce
178 , raCodeCoalesced = code_coalesced
179 , raPatched = code_patched
180 , raSpillClean = code_spillclean
181 , raFinal = code_final
182 , raSRMs = foldl' addSRM (0, 0, 0) $ map countSRMs code_spillclean }
186 if dump then [stat] ++ maybeToList stat1 ++ debug_codeGraphs
189 -- space leak avoidance
190 seqList statList `seq` return ()
194 , graph_colored_lint)
196 -- we couldn't find a coloring, time to spill something
198 -- if -fasm-lint is turned on then validate the graph
199 let graph_colored_lint =
200 if dopt Opt_DoAsmLinting dflags
201 then Color.validateGraph (text "")
202 False -- don't require nodes to be colored
206 -- spill the uncolored regs
207 (code_spilled, slotsFree', spillStats)
208 <- regSpill code_coalesced slotsFree rsSpill
210 -- recalculate liveness
211 -- NOTE: we have to reverse the SCCs here to get them back into the reverse-dependency
212 -- order required by computeLiveness. If they're not in the correct order
213 -- that function will panic.
214 code_relive <- mapM (regLiveness . reverseBlocksInTops) code_spilled
216 -- record what happened in this stage for debugging
220 , raGraph = graph_colored_lint
221 , raCoalesced = rmCoalesce
222 , raSpillStats = spillStats
223 , raSpillCosts = spillCosts
224 , raSpilled = code_spilled }
228 then [stat] ++ maybeToList stat1 ++ debug_codeGraphs
231 -- space leak avoidance
232 seqList statList `seq` return ()
234 regAlloc_spin dflags (spinCount + 1) triv regsFree slotsFree'
239 -- | Build a graph from the liveness and coalesce information in this code.
242 => [LiveCmmTop instr]
243 -> UniqSM (Color.Graph VirtualReg RegClass RealReg)
247 -- Slurp out the conflicts and reg->reg moves from this code
248 let (conflictList, moveList) =
249 unzip $ map slurpConflicts code
251 -- Slurp out the spill/reload coalesces
252 let moveList2 = map slurpReloadCoalesce code
254 -- Add the reg-reg conflicts to the graph
255 let conflictBag = unionManyBags conflictList
256 let graph_conflict = foldrBag graphAddConflictSet Color.initGraph conflictBag
258 -- Add the coalescences edges to the graph.
259 let moveBag = unionBags (unionManyBags moveList2) (unionManyBags moveList)
260 let graph_coalesce = foldrBag graphAddCoalesce graph_conflict moveBag
262 return graph_coalesce
265 -- | Add some conflict edges to the graph.
266 -- Conflicts between virtual and real regs are recorded as exclusions.
269 -> Color.Graph VirtualReg RegClass RealReg
270 -> Color.Graph VirtualReg RegClass RealReg
272 graphAddConflictSet set graph
273 = let virtuals = mkUniqSet
274 [ vr | RegVirtual vr <- uniqSetToList set ]
276 graph1 = Color.addConflicts virtuals classOfVirtualReg graph
278 graph2 = foldr (\(r1, r2) -> Color.addExclusion r1 classOfVirtualReg r2)
281 | RegVirtual vr <- uniqSetToList set
282 , RegReal rr <- uniqSetToList set]
287 -- | Add some coalesence edges to the graph
288 -- Coalesences between virtual and real regs are recorded as preferences.
291 -> Color.Graph VirtualReg RegClass RealReg
292 -> Color.Graph VirtualReg RegClass RealReg
294 graphAddCoalesce (r1, r2) graph
296 , RegVirtual vr <- r2
297 = Color.addPreference (vr, classOfVirtualReg vr) rr graph
300 , RegVirtual vr <- r1
301 = Color.addPreference (vr, classOfVirtualReg vr) rr graph
303 | RegVirtual vr1 <- r1
304 , RegVirtual vr2 <- r2
306 (vr1, classOfVirtualReg vr1)
307 (vr2, classOfVirtualReg vr2)
310 -- We can't coalesce two real regs, but there could well be existing
311 -- hreg,hreg moves in the input code. We'll just ignore these
312 -- for coalescing purposes.
318 = panic "graphAddCoalesce: bogus"
321 -- | Patch registers in code using the reg -> reg mapping in this graph.
323 :: (Outputable instr, Instruction instr)
324 => Color.Graph VirtualReg RegClass RealReg
325 -> LiveCmmTop instr -> LiveCmmTop instr
327 patchRegsFromGraph graph code
329 -- a function to lookup the hardreg for a virtual reg from the graph.
331 -- leave real regs alone.
335 -- this virtual has a regular node in the graph.
336 | RegVirtual vr <- reg
337 , Just node <- Color.lookupNode graph vr
338 = case Color.nodeColor node of
339 Just color -> RegReal color
340 Nothing -> RegVirtual vr
342 -- no node in the graph for this virtual, bad news.
344 = pprPanic "patchRegsFromGraph: register mapping failed."
345 ( text "There is no node in the graph for register " <> ppr reg
350 targetVirtualRegSqueeze
351 targetRealRegSqueeze)
354 in patchEraseLive patchF code
358 -- for when laziness just isn't what you wanted...
360 seqGraph :: Color.Graph VirtualReg RegClass RealReg -> ()
361 seqGraph graph = seqNodes (eltsUFM (Color.graphMap graph))
363 seqNodes :: [Color.Node VirtualReg RegClass RealReg] -> ()
367 (n : ns) -> seqNode n `seq` seqNodes ns
369 seqNode :: Color.Node VirtualReg RegClass RealReg -> ()
371 = seqVirtualReg (Color.nodeId node)
372 `seq` seqRegClass (Color.nodeClass node)
373 `seq` seqMaybeRealReg (Color.nodeColor node)
374 `seq` (seqVirtualRegList (uniqSetToList (Color.nodeConflicts node)))
375 `seq` (seqRealRegList (uniqSetToList (Color.nodeExclusions node)))
376 `seq` (seqRealRegList (Color.nodePreference node))
377 `seq` (seqVirtualRegList (uniqSetToList (Color.nodeCoalesce node)))
379 seqVirtualReg :: VirtualReg -> ()
380 seqVirtualReg reg = reg `seq` ()
382 seqRealReg :: RealReg -> ()
383 seqRealReg reg = reg `seq` ()
385 seqRegClass :: RegClass -> ()
386 seqRegClass c = c `seq` ()
388 seqMaybeRealReg :: Maybe RealReg -> ()
392 Just r -> seqRealReg r
394 seqVirtualRegList :: [VirtualReg] -> ()
398 (r : rs) -> seqVirtualReg r `seq` seqVirtualRegList rs
400 seqRealRegList :: [RealReg] -> ()
404 (r : rs) -> seqRealReg r `seq` seqRealRegList rs
410 (r : rs) -> r `seq` seqList rs