2 -- The above warning supression flag is a temporary kludge.
3 -- While working on this module you are encouraged to remove it and fix
4 -- any warnings in the module. See
5 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
8 -----------------------------------------------------------------------------
10 -- Machine-specific parts of the register allocator
12 -- (c) The University of Glasgow 1996-2004
14 -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
27 JumpDest, canShortcut, shortcutJump, shortcutStatic,
36 #include "HsVersions.h"
41 import MachOp ( MachRep(..), wordRep )
45 import Constants ( rESERVED_C_STACK_BYTES )
48 -- -----------------------------------------------------------------------------
51 -- @regUsage@ returns the sets of src and destination registers used
52 -- by a particular instruction. Machine registers that are
53 -- pre-allocated to stgRegs are filtered out, because they are
54 -- uninteresting from a register allocation standpoint. (We wouldn't
55 -- want them to end up on the free list!) As far as we are concerned,
56 -- the fixed registers simply don't exist (for allocation purposes,
59 -- regUsage doesn't need to do any trickery for jumps and such. Just
60 -- state precisely the regs read and written by that insn. The
61 -- consequences of control flow transfers, as far as register
62 -- allocation goes, are taken care of by the register allocator.
64 data RegUsage = RU [Reg] [Reg]
69 regUsage :: Instr -> RegUsage
71 interesting (VirtualRegI _) = True
72 interesting (VirtualRegHi _) = True
73 interesting (VirtualRegF _) = True
74 interesting (VirtualRegD _) = True
75 interesting (RealReg i) = isFastTrue (freeReg i)
79 regUsage instr = case instr of
80 SPILL reg slot -> usage ([reg], [])
81 RELOAD slot reg -> usage ([], [reg])
82 LD B reg addr -> usage (regAddr addr, [reg, t9])
83 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
84 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
85 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
86 LD sz reg addr -> usage (regAddr addr, [reg])
87 LDA reg addr -> usage (regAddr addr, [reg])
88 LDAH reg addr -> usage (regAddr addr, [reg])
89 LDGP reg addr -> usage (regAddr addr, [reg])
90 LDI sz reg imm -> usage ([], [reg])
91 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
92 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
93 ST sz reg addr -> usage (reg : regAddr addr, [])
94 CLR reg -> usage ([], [reg])
95 ABS sz ri reg -> usage (regRI ri, [reg])
96 NEG sz ov ri reg -> usage (regRI ri, [reg])
97 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
103 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
104 NOT ri reg -> usage (regRI ri, [reg])
105 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
106 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
107 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
108 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
109 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
110 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
111 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
112 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
113 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
114 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
115 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
116 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
117 FCLR reg -> usage ([], [reg])
118 FABS r1 r2 -> usage ([r1], [r2])
119 FNEG sz r1 r2 -> usage ([r1], [r2])
120 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
121 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
122 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
123 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
124 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
125 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
126 FMOV r1 r2 -> usage ([r1], [r2])
129 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
130 BI cond reg lbl -> usage ([reg], [])
131 BF cond reg lbl -> usage ([reg], [])
132 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
134 BSR _ n -> RU (argRegSet n) callClobberedRegSet
135 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
140 usage (src, dst) = RU (mkRegSet (filter interesting src))
141 (mkRegSet (filter interesting dst))
143 interesting (FixedReg _) = False
146 regAddr (AddrReg r1) = [r1]
147 regAddr (AddrRegImm r1 _) = [r1]
148 regAddr (AddrImm _) = []
150 regRI (RIReg r) = [r]
153 #endif /* alpha_TARGET_ARCH */
154 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
155 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
157 regUsage instr = case instr of
158 MOV sz src dst -> usageRW src dst
159 MOVZxL sz src dst -> usageRW src dst
160 MOVSxL sz src dst -> usageRW src dst
161 LEA sz src dst -> usageRW src dst
162 ADD sz src dst -> usageRM src dst
163 ADC sz src dst -> usageRM src dst
164 SUB sz src dst -> usageRM src dst
165 IMUL sz src dst -> usageRM src dst
166 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
167 MUL sz src dst -> usageRM src dst
168 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
169 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
170 AND sz src dst -> usageRM src dst
171 OR sz src dst -> usageRM src dst
172 XOR sz (OpReg src) (OpReg dst)
173 | src == dst -> mkRU [] [dst]
174 XOR sz src dst -> usageRM src dst
175 NOT sz op -> usageM op
176 NEGI sz op -> usageM op
177 SHL sz imm dst -> usageRM imm dst
178 SAR sz imm dst -> usageRM imm dst
179 SHR sz imm dst -> usageRM imm dst
180 BT sz imm src -> mkRUR (use_R src)
182 PUSH sz op -> mkRUR (use_R op)
183 POP sz op -> mkRU [] (def_W op)
184 TEST sz src dst -> mkRUR (use_R src ++ use_R dst)
185 CMP sz src dst -> mkRUR (use_R src ++ use_R dst)
186 SETCC cond op -> mkRU [] (def_W op)
187 JXX cond lbl -> mkRU [] []
188 JXX_GBL cond lbl -> mkRU [] []
189 JMP op -> mkRUR (use_R op)
190 JMP_TBL op ids -> mkRUR (use_R op)
191 CALL (Left imm) params -> mkRU params callClobberedRegs
192 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
193 CLTD sz -> mkRU [eax] [edx]
197 GMOV src dst -> mkRU [src] [dst]
198 GLD sz src dst -> mkRU (use_EA src) [dst]
199 GST sz src dst -> mkRUR (src : use_EA dst)
201 GLDZ dst -> mkRU [] [dst]
202 GLD1 dst -> mkRU [] [dst]
204 GFTOI src dst -> mkRU [src] [dst]
205 GDTOI src dst -> mkRU [src] [dst]
207 GITOF src dst -> mkRU [src] [dst]
208 GITOD src dst -> mkRU [src] [dst]
210 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
211 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
212 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
213 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
215 GCMP sz src1 src2 -> mkRUR [src1,src2]
216 GABS sz src dst -> mkRU [src] [dst]
217 GNEG sz src dst -> mkRU [src] [dst]
218 GSQRT sz src dst -> mkRU [src] [dst]
219 GSIN sz _ _ src dst -> mkRU [src] [dst]
220 GCOS sz _ _ src dst -> mkRU [src] [dst]
221 GTAN sz _ _ src dst -> mkRU [src] [dst]
224 #if x86_64_TARGET_ARCH
225 CVTSS2SD src dst -> mkRU [src] [dst]
226 CVTSD2SS src dst -> mkRU [src] [dst]
227 CVTTSS2SIQ src dst -> mkRU (use_R src) [dst]
228 CVTTSD2SIQ src dst -> mkRU (use_R src) [dst]
229 CVTSI2SS src dst -> mkRU (use_R src) [dst]
230 CVTSI2SD src dst -> mkRU (use_R src) [dst]
231 FDIV sz src dst -> usageRM src dst
234 FETCHGOT reg -> mkRU [] [reg]
235 FETCHPC reg -> mkRU [] [reg]
239 SPILL reg slot -> mkRU [reg] []
240 RELOAD slot reg -> mkRU [] [reg]
242 _other -> panic "regUsage: unrecognised instr"
245 -- 2 operand form; first operand Read; second Written
246 usageRW :: Operand -> Operand -> RegUsage
247 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
248 usageRW op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
250 -- 2 operand form; first operand Read; second Modified
251 usageRM :: Operand -> Operand -> RegUsage
252 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
253 usageRM op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
255 -- 1 operand form; operand Modified
256 usageM :: Operand -> RegUsage
257 usageM (OpReg reg) = mkRU [reg] [reg]
258 usageM (OpAddr ea) = mkRUR (use_EA ea)
260 -- Registers defd when an operand is written.
261 def_W (OpReg reg) = [reg]
262 def_W (OpAddr ea) = []
264 -- Registers used when an operand is read.
265 use_R (OpReg reg) = [reg]
266 use_R (OpImm imm) = []
267 use_R (OpAddr ea) = use_EA ea
269 -- Registers used to compute an effective address.
270 use_EA (ImmAddr _ _) = []
271 use_EA (AddrBaseIndex base index _) =
272 use_base base $! use_index index
273 where use_base (EABaseReg r) x = r : x
275 use_index EAIndexNone = []
276 use_index (EAIndex i _) = [i]
278 mkRUR src = src' `seq` RU src' []
279 where src' = filter interesting src
281 mkRU src dst = src' `seq` dst' `seq` RU src' dst'
282 where src' = filter interesting src
283 dst' = filter interesting dst
285 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
286 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
287 #if sparc_TARGET_ARCH
289 regUsage instr = case instr of
290 SPILL reg slot -> usage ([reg], [])
291 RELOAD slot reg -> usage ([], [reg])
293 LD sz addr reg -> usage (regAddr addr, [reg])
294 ST sz reg addr -> usage (reg : regAddr addr, [])
295 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
296 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
297 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
298 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
299 RDY rd -> usage ([], [rd])
300 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
301 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
302 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
303 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
304 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
305 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
306 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
307 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
308 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
309 SETHI imm reg -> usage ([], [reg])
310 FABS s r1 r2 -> usage ([r1], [r2])
311 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
312 FCMP e s r1 r2 -> usage ([r1, r2], [])
313 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
314 FMOV s r1 r2 -> usage ([r1], [r2])
315 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
316 FNEG s r1 r2 -> usage ([r1], [r2])
317 FSQRT s r1 r2 -> usage ([r1], [r2])
318 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
319 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
321 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
322 JMP addr -> usage (regAddr addr, [])
324 CALL (Left imm) n True -> noUsage
325 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
326 CALL (Right reg) n True -> usage ([reg], [])
327 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
331 usage (src, dst) = RU (filter interesting src)
332 (filter interesting dst)
334 regAddr (AddrRegReg r1 r2) = [r1, r2]
335 regAddr (AddrRegImm r1 _) = [r1]
337 regRI (RIReg r) = [r]
340 #endif /* sparc_TARGET_ARCH */
341 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
342 #if powerpc_TARGET_ARCH
344 regUsage instr = case instr of
345 SPILL reg slot -> usage ([reg], [])
346 RELOAD slot reg -> usage ([], [reg])
348 LD sz reg addr -> usage (regAddr addr, [reg])
349 LA sz reg addr -> usage (regAddr addr, [reg])
350 ST sz reg addr -> usage (reg : regAddr addr, [])
351 STU sz reg addr -> usage (reg : regAddr addr, [])
352 LIS reg imm -> usage ([], [reg])
353 LI reg imm -> usage ([], [reg])
354 MR reg1 reg2 -> usage ([reg2], [reg1])
355 CMP sz reg ri -> usage (reg : regRI ri,[])
356 CMPL sz reg ri -> usage (reg : regRI ri,[])
357 BCC cond lbl -> noUsage
358 BCCFAR cond lbl -> noUsage
359 MTCTR reg -> usage ([reg],[])
360 BCTR targets -> noUsage
361 BL imm params -> usage (params, callClobberedRegs)
362 BCTRL params -> usage (params, callClobberedRegs)
363 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
364 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
365 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
366 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
367 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
368 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
369 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
370 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
371 MULLW_MayOflo reg1 reg2 reg3
372 -> usage ([reg2,reg3], [reg1])
373 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
374 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
375 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
376 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
377 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
378 NEG reg1 reg2 -> usage ([reg2], [reg1])
379 NOT reg1 reg2 -> usage ([reg2], [reg1])
380 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
381 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
382 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
383 RLWINM reg1 reg2 sh mb me
384 -> usage ([reg2], [reg1])
385 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
386 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
387 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
388 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
389 FNEG r1 r2 -> usage ([r2], [r1])
390 FCMP r1 r2 -> usage ([r1,r2], [])
391 FCTIWZ r1 r2 -> usage ([r2], [r1])
392 FRSP r1 r2 -> usage ([r2], [r1])
393 MFCR reg -> usage ([], [reg])
394 MFLR reg -> usage ([], [reg])
395 FETCHPC reg -> usage ([], [reg])
398 usage (src, dst) = RU (filter interesting src)
399 (filter interesting dst)
400 regAddr (AddrRegReg r1 r2) = [r1, r2]
401 regAddr (AddrRegImm r1 _) = [r1]
403 regRI (RIReg r) = [r]
405 #endif /* powerpc_TARGET_ARCH */
408 -- -----------------------------------------------------------------------------
409 -- Determine the possible destinations from the current instruction.
411 -- (we always assume that the next instruction is also a valid destination;
412 -- if this isn't the case then the jump should be at the end of the basic
415 jumpDests :: Instr -> [BlockId] -> [BlockId]
418 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
420 JMP_TBL _ ids -> ids ++ acc
421 #elif powerpc_TARGET_ARCH
423 BCCFAR _ id -> id : acc
424 BCTR targets -> targets ++ acc
428 patchJump :: Instr -> BlockId -> BlockId -> Instr
430 patchJump insn old new
432 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
433 JXX cc id | id == old -> JXX cc new
434 JMP_TBL op ids -> error "Cannot patch JMP_TBL"
435 #elif powerpc_TARGET_ARCH
436 BCC cc id | id == old -> BCC cc new
437 BCCFAR cc id | id == old -> BCCFAR cc new
438 BCTR targets -> error "Cannot patch BCTR"
442 data JumpDest = DestBlockId BlockId | DestImm Imm
444 canShortcut :: Instr -> Maybe JumpDest
445 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
446 canShortcut (JXX ALWAYS id) = Just (DestBlockId id)
447 canShortcut (JMP (OpImm imm)) = Just (DestImm imm)
449 canShortcut _ = Nothing
451 shortcutJump :: (BlockId -> Maybe JumpDest) -> Instr -> Instr
452 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
453 shortcutJump fn insn@(JXX cc id) =
456 Just (DestBlockId id') -> shortcutJump fn (JXX cc id')
457 Just (DestImm imm) -> shortcutJump fn (JXX_GBL cc imm)
459 shortcutJump fn other = other
461 -- Here because it knows about JumpDest
462 shortcutStatic :: (BlockId -> Maybe JumpDest) -> CmmStatic -> CmmStatic
463 shortcutStatic fn (CmmStaticLit (CmmLabel lab))
464 | Just uq <- maybeAsmTemp lab
465 = CmmStaticLit (CmmLabel (shortBlockId fn (BlockId uq)))
466 shortcutStatic fn (CmmStaticLit (CmmLabelDiffOff lbl1 lbl2 off))
467 | Just uq <- maybeAsmTemp lbl1
468 = CmmStaticLit (CmmLabelDiffOff (shortBlockId fn (BlockId uq)) lbl2 off)
469 -- slightly dodgy, we're ignoring the second label, but this
470 -- works with the way we use CmmLabelDiffOff for jump tables now.
471 shortcutStatic fn other_static
474 shortBlockId fn blockid@(BlockId uq) =
476 Nothing -> mkAsmTempLabel uq
477 Just (DestBlockId blockid') -> shortBlockId fn blockid'
478 Just (DestImm (ImmCLbl lbl)) -> lbl
479 _other -> panic "shortBlockId"
481 -- -----------------------------------------------------------------------------
482 -- 'patchRegs' function
484 -- 'patchRegs' takes an instruction and applies the given mapping to
485 -- all the register references.
487 patchRegs :: Instr -> (Reg -> Reg) -> Instr
489 #if alpha_TARGET_ARCH
491 patchRegs instr env = case instr of
492 SPILL reg slot -> SPILL (env reg) slot
493 RELOAD slot reg -> RELOAD slot (env reg)
494 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
495 LDA reg addr -> LDA (env reg) (fixAddr addr)
496 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
497 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
498 LDI sz reg imm -> LDI sz (env reg) imm
499 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
500 CLR reg -> CLR (env reg)
501 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
502 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
503 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
504 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
505 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
506 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
507 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
508 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
509 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
510 NOT ar reg -> NOT (fixRI ar) (env reg)
511 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
512 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
513 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
514 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
515 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
516 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
517 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
518 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
519 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
520 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
521 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
522 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
523 FCLR reg -> FCLR (env reg)
524 FABS r1 r2 -> FABS (env r1) (env r2)
525 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
526 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
527 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
528 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
529 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
530 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
531 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
532 FMOV r1 r2 -> FMOV (env r1) (env r2)
533 BI cond reg lbl -> BI cond (env reg) lbl
534 BF cond reg lbl -> BF cond (env reg) lbl
535 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
536 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
539 fixAddr (AddrReg r1) = AddrReg (env r1)
540 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
541 fixAddr other = other
543 fixRI (RIReg r) = RIReg (env r)
546 #endif /* alpha_TARGET_ARCH */
547 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
548 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
550 patchRegs instr env = case instr of
551 MOV sz src dst -> patch2 (MOV sz) src dst
552 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
553 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
554 LEA sz src dst -> patch2 (LEA sz) src dst
555 ADD sz src dst -> patch2 (ADD sz) src dst
556 ADC sz src dst -> patch2 (ADC sz) src dst
557 SUB sz src dst -> patch2 (SUB sz) src dst
558 IMUL sz src dst -> patch2 (IMUL sz) src dst
559 IMUL2 sz src -> patch1 (IMUL2 sz) src
560 MUL sz src dst -> patch2 (MUL sz) src dst
561 IDIV sz op -> patch1 (IDIV sz) op
562 DIV sz op -> patch1 (DIV sz) op
563 AND sz src dst -> patch2 (AND sz) src dst
564 OR sz src dst -> patch2 (OR sz) src dst
565 XOR sz src dst -> patch2 (XOR sz) src dst
566 NOT sz op -> patch1 (NOT sz) op
567 NEGI sz op -> patch1 (NEGI sz) op
568 SHL sz imm dst -> patch1 (SHL sz imm) dst
569 SAR sz imm dst -> patch1 (SAR sz imm) dst
570 SHR sz imm dst -> patch1 (SHR sz imm) dst
571 BT sz imm src -> patch1 (BT sz imm) src
572 TEST sz src dst -> patch2 (TEST sz) src dst
573 CMP sz src dst -> patch2 (CMP sz) src dst
574 PUSH sz op -> patch1 (PUSH sz) op
575 POP sz op -> patch1 (POP sz) op
576 SETCC cond op -> patch1 (SETCC cond) op
577 JMP op -> patch1 JMP op
578 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
581 GMOV src dst -> GMOV (env src) (env dst)
582 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
583 GST sz src dst -> GST sz (env src) (lookupAddr dst)
585 GLDZ dst -> GLDZ (env dst)
586 GLD1 dst -> GLD1 (env dst)
588 GFTOI src dst -> GFTOI (env src) (env dst)
589 GDTOI src dst -> GDTOI (env src) (env dst)
591 GITOF src dst -> GITOF (env src) (env dst)
592 GITOD src dst -> GITOD (env src) (env dst)
594 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
595 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
596 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
597 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
599 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
600 GABS sz src dst -> GABS sz (env src) (env dst)
601 GNEG sz src dst -> GNEG sz (env src) (env dst)
602 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
603 GSIN sz l1 l2 src dst -> GSIN sz l1 l2 (env src) (env dst)
604 GCOS sz l1 l2 src dst -> GCOS sz l1 l2 (env src) (env dst)
605 GTAN sz l1 l2 src dst -> GTAN sz l1 l2 (env src) (env dst)
608 #if x86_64_TARGET_ARCH
609 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
610 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
611 CVTTSS2SIQ src dst -> CVTTSS2SIQ (patchOp src) (env dst)
612 CVTTSD2SIQ src dst -> CVTTSD2SIQ (patchOp src) (env dst)
613 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
614 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
615 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
618 CALL (Left imm) _ -> instr
619 CALL (Right reg) p -> CALL (Right (env reg)) p
621 FETCHGOT reg -> FETCHGOT (env reg)
622 FETCHPC reg -> FETCHPC (env reg)
627 SPILL reg slot -> SPILL (env reg) slot
628 RELOAD slot reg -> RELOAD slot (env reg)
634 _other -> panic "patchRegs: unrecognised instr"
637 patch1 insn op = insn $! patchOp op
638 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
640 patchOp (OpReg reg) = OpReg $! env reg
641 patchOp (OpImm imm) = OpImm imm
642 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
644 lookupAddr (ImmAddr imm off) = ImmAddr imm off
645 lookupAddr (AddrBaseIndex base index disp)
646 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
648 lookupBase EABaseNone = EABaseNone
649 lookupBase EABaseRip = EABaseRip
650 lookupBase (EABaseReg r) = EABaseReg (env r)
652 lookupIndex EAIndexNone = EAIndexNone
653 lookupIndex (EAIndex r i) = EAIndex (env r) i
655 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
656 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
657 #if sparc_TARGET_ARCH
659 patchRegs instr env = case instr of
660 SPILL reg slot -> SPILL (env reg) slot
661 RELOAD slot reg -> RELOAD slot (env reg)
662 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
663 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
664 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
665 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
666 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
667 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
668 RDY rd -> RDY (env rd)
669 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
670 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
671 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
672 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
673 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
674 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
675 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
676 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
677 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
678 SETHI imm reg -> SETHI imm (env reg)
679 FABS s r1 r2 -> FABS s (env r1) (env r2)
680 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
681 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
682 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
683 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
684 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
685 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
686 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
687 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
688 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
689 JMP addr -> JMP (fixAddr addr)
690 CALL (Left i) n t -> CALL (Left i) n t
691 CALL (Right r) n t -> CALL (Right (env r)) n t
694 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
695 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
697 fixRI (RIReg r) = RIReg (env r)
700 #endif /* sparc_TARGET_ARCH */
701 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
702 #if powerpc_TARGET_ARCH
704 patchRegs instr env = case instr of
705 SPILL reg slot -> SPILL (env reg) slot
706 RELOAD slot reg -> RELOAD slot (env reg)
708 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
709 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
710 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
711 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
712 LIS reg imm -> LIS (env reg) imm
713 LI reg imm -> LI (env reg) imm
714 MR reg1 reg2 -> MR (env reg1) (env reg2)
715 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
716 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
717 BCC cond lbl -> BCC cond lbl
718 BCCFAR cond lbl -> BCCFAR cond lbl
719 MTCTR reg -> MTCTR (env reg)
720 BCTR targets -> BCTR targets
721 BL imm argRegs -> BL imm argRegs -- argument regs
722 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
723 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
724 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
725 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
726 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
727 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
728 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
729 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
730 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
731 MULLW_MayOflo reg1 reg2 reg3
732 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
733 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
734 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
735 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
736 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
737 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
738 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
739 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
740 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
741 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
742 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
743 RLWINM reg1 reg2 sh mb me
744 -> RLWINM (env reg1) (env reg2) sh mb me
745 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
746 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
747 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
748 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
749 FNEG r1 r2 -> FNEG (env r1) (env r2)
750 FCMP r1 r2 -> FCMP (env r1) (env r2)
751 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
752 FRSP r1 r2 -> FRSP (env r1) (env r2)
753 MFCR reg -> MFCR (env reg)
754 MFLR reg -> MFLR (env reg)
755 FETCHPC reg -> FETCHPC (env reg)
758 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
759 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
761 fixRI (RIReg r) = RIReg (env r)
763 #endif /* powerpc_TARGET_ARCH */
765 -- -----------------------------------------------------------------------------
766 -- Detecting reg->reg moves
768 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
769 -- by assigning the src and dest temporaries to the same real register.
771 isRegRegMove :: Instr -> Maybe (Reg,Reg)
772 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
774 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
775 #elif powerpc_TARGET_ARCH
776 isRegRegMove (MR dst src) = Just (src,dst)
778 #error ToDo: isRegRegMove
780 isRegRegMove _ = Nothing
782 -- -----------------------------------------------------------------------------
783 -- Generating spill instructions
786 :: Reg -- register to spill
787 -> Int -- current stack delta
788 -> Int -- spill slot to use
790 mkSpillInstr reg delta slot
791 = let off = spillSlotToOffset slot
793 #ifdef alpha_TARGET_ARCH
794 {-Alpha: spill below the stack pointer (?)-}
795 ST sz dyn (spRel (- (off `div` 8)))
797 #ifdef i386_TARGET_ARCH
798 let off_w = (off-delta) `div` 4
799 in case regClass reg of
800 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
801 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
803 #ifdef x86_64_TARGET_ARCH
804 let off_w = (off-delta) `div` 8
805 in case regClass reg of
806 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
807 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
808 -- ToDo: will it work to always spill as a double?
809 -- does that cause a stall if the data was a float?
811 #ifdef sparc_TARGET_ARCH
812 {-SPARC: spill below frame pointer leaving 2 words/spill-}
813 let{off_w = 1 + (off `div` 4);
814 sz = case regClass reg of {
818 in ST sz reg (fpRel (negate off_w))
820 #ifdef powerpc_TARGET_ARCH
821 let sz = case regClass reg of
824 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
829 :: Reg -- register to load
830 -> Int -- current stack delta
831 -> Int -- spill slot to use
833 mkLoadInstr reg delta slot
834 = let off = spillSlotToOffset slot
836 #if alpha_TARGET_ARCH
837 LD sz dyn (spRel (- (off `div` 8)))
840 let off_w = (off-delta) `div` 4
841 in case regClass reg of {
842 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
843 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
845 #if x86_64_TARGET_ARCH
846 let off_w = (off-delta) `div` 8
847 in case regClass reg of
848 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
849 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
851 #if sparc_TARGET_ARCH
852 let{off_w = 1 + (off `div` 4);
853 sz = case regClass reg of {
857 in LD sz (fpRel (- off_w)) reg
859 #if powerpc_TARGET_ARCH
860 let sz = case regClass reg of
863 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
870 mkRegRegMoveInstr src dst
871 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
872 = case regClass src of
873 RcInteger -> MOV wordRep (OpReg src) (OpReg dst)
875 RcDouble -> GMOV src dst
877 RcDouble -> MOV F64 (OpReg src) (OpReg dst)
879 #elif powerpc_TARGET_ARCH
882 #error ToDo: mkRegRegMoveInstr
888 #if alpha_TARGET_ARCH
889 mkBranchInstr id = [BR id]
892 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
893 mkBranchInstr id = [JXX ALWAYS id]
896 #if sparc_TARGET_ARCH
897 mkBranchInstr (BlockId id) = [BI ALWAYS False (ImmCLbl (mkAsmTempLabel id)), NOP]
900 #if powerpc_TARGET_ARCH
901 mkBranchInstr id = [BCC ALWAYS id]
906 spillSlotSize = IF_ARCH_i386(12, 8)
909 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
911 -- convert a spill slot number to a *byte* offset, with no sign:
912 -- decide on a per arch basis whether you are spilling above or below
913 -- the C stack pointer.
914 spillSlotToOffset :: Int -> Int
915 spillSlotToOffset slot
916 | slot >= 0 && slot < maxSpillSlots
917 = 64 + spillSlotSize * slot
919 = pprPanic "spillSlotToOffset:"
920 ( text "invalid spill location: " <> int slot
921 $$ text "maxSpillSlots: " <> int maxSpillSlots)