2 -- The above warning supression flag is a temporary kludge.
3 -- While working on this module you are encouraged to remove it and fix
4 -- any warnings in the module. See
5 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
8 -----------------------------------------------------------------------------
10 -- Machine-specific parts of the register allocator
12 -- (c) The University of Glasgow 1996-2004
14 -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
27 JumpDest, canShortcut, shortcutJump, shortcutStatic,
36 #include "HsVersions.h"
44 import Constants ( rESERVED_C_STACK_BYTES )
47 -- -----------------------------------------------------------------------------
50 -- @regUsage@ returns the sets of src and destination registers used
51 -- by a particular instruction. Machine registers that are
52 -- pre-allocated to stgRegs are filtered out, because they are
53 -- uninteresting from a register allocation standpoint. (We wouldn't
54 -- want them to end up on the free list!) As far as we are concerned,
55 -- the fixed registers simply don't exist (for allocation purposes,
58 -- regUsage doesn't need to do any trickery for jumps and such. Just
59 -- state precisely the regs read and written by that insn. The
60 -- consequences of control flow transfers, as far as register
61 -- allocation goes, are taken care of by the register allocator.
63 data RegUsage = RU [Reg] [Reg]
68 regUsage :: Instr -> RegUsage
70 interesting (VirtualRegI _) = True
71 interesting (VirtualRegHi _) = True
72 interesting (VirtualRegF _) = True
73 interesting (VirtualRegD _) = True
74 interesting (RealReg i) = isFastTrue (freeReg i)
78 regUsage instr = case instr of
79 SPILL reg slot -> usage ([reg], [])
80 RELOAD slot reg -> usage ([], [reg])
81 LD B reg addr -> usage (regAddr addr, [reg, t9])
82 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
83 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
84 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
85 LD sz reg addr -> usage (regAddr addr, [reg])
86 LDA reg addr -> usage (regAddr addr, [reg])
87 LDAH reg addr -> usage (regAddr addr, [reg])
88 LDGP reg addr -> usage (regAddr addr, [reg])
89 LDI sz reg imm -> usage ([], [reg])
90 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
91 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
92 ST sz reg addr -> usage (reg : regAddr addr, [])
93 CLR reg -> usage ([], [reg])
94 ABS sz ri reg -> usage (regRI ri, [reg])
95 NEG sz ov ri reg -> usage (regRI ri, [reg])
96 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
102 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
103 NOT ri reg -> usage (regRI ri, [reg])
104 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
105 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
106 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
107 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
108 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
109 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
110 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
111 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
112 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
113 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
114 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
115 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
116 FCLR reg -> usage ([], [reg])
117 FABS r1 r2 -> usage ([r1], [r2])
118 FNEG sz r1 r2 -> usage ([r1], [r2])
119 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
120 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
121 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
122 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
123 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
124 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
125 FMOV r1 r2 -> usage ([r1], [r2])
128 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
129 BI cond reg lbl -> usage ([reg], [])
130 BF cond reg lbl -> usage ([reg], [])
131 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
133 BSR _ n -> RU (argRegSet n) callClobberedRegSet
134 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
139 usage (src, dst) = RU (mkRegSet (filter interesting src))
140 (mkRegSet (filter interesting dst))
142 interesting (FixedReg _) = False
145 regAddr (AddrReg r1) = [r1]
146 regAddr (AddrRegImm r1 _) = [r1]
147 regAddr (AddrImm _) = []
149 regRI (RIReg r) = [r]
152 #endif /* alpha_TARGET_ARCH */
153 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
154 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
156 regUsage instr = case instr of
157 MOV sz src dst -> usageRW src dst
158 MOVZxL sz src dst -> usageRW src dst
159 MOVSxL sz src dst -> usageRW src dst
160 LEA sz src dst -> usageRW src dst
161 ADD sz src dst -> usageRM src dst
162 ADC sz src dst -> usageRM src dst
163 SUB sz src dst -> usageRM src dst
164 IMUL sz src dst -> usageRM src dst
165 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
166 MUL sz src dst -> usageRM src dst
167 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
168 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
169 AND sz src dst -> usageRM src dst
170 OR sz src dst -> usageRM src dst
171 XOR sz (OpReg src) (OpReg dst)
172 | src == dst -> mkRU [] [dst]
173 XOR sz src dst -> usageRM src dst
174 NOT sz op -> usageM op
175 NEGI sz op -> usageM op
176 SHL sz imm dst -> usageRM imm dst
177 SAR sz imm dst -> usageRM imm dst
178 SHR sz imm dst -> usageRM imm dst
179 BT sz imm src -> mkRUR (use_R src)
181 PUSH sz op -> mkRUR (use_R op)
182 POP sz op -> mkRU [] (def_W op)
183 TEST sz src dst -> mkRUR (use_R src ++ use_R dst)
184 CMP sz src dst -> mkRUR (use_R src ++ use_R dst)
185 SETCC cond op -> mkRU [] (def_W op)
186 JXX cond lbl -> mkRU [] []
187 JXX_GBL cond lbl -> mkRU [] []
188 JMP op -> mkRUR (use_R op)
189 JMP_TBL op ids -> mkRUR (use_R op)
190 CALL (Left imm) params -> mkRU params callClobberedRegs
191 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
192 CLTD sz -> mkRU [eax] [edx]
196 GMOV src dst -> mkRU [src] [dst]
197 GLD sz src dst -> mkRU (use_EA src) [dst]
198 GST sz src dst -> mkRUR (src : use_EA dst)
200 GLDZ dst -> mkRU [] [dst]
201 GLD1 dst -> mkRU [] [dst]
203 GFTOI src dst -> mkRU [src] [dst]
204 GDTOI src dst -> mkRU [src] [dst]
206 GITOF src dst -> mkRU [src] [dst]
207 GITOD src dst -> mkRU [src] [dst]
209 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
210 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
211 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
212 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
214 GCMP sz src1 src2 -> mkRUR [src1,src2]
215 GABS sz src dst -> mkRU [src] [dst]
216 GNEG sz src dst -> mkRU [src] [dst]
217 GSQRT sz src dst -> mkRU [src] [dst]
218 GSIN sz _ _ src dst -> mkRU [src] [dst]
219 GCOS sz _ _ src dst -> mkRU [src] [dst]
220 GTAN sz _ _ src dst -> mkRU [src] [dst]
223 #if x86_64_TARGET_ARCH
224 CVTSS2SD src dst -> mkRU [src] [dst]
225 CVTSD2SS src dst -> mkRU [src] [dst]
226 CVTTSS2SIQ src dst -> mkRU (use_R src) [dst]
227 CVTTSD2SIQ src dst -> mkRU (use_R src) [dst]
228 CVTSI2SS src dst -> mkRU (use_R src) [dst]
229 CVTSI2SD src dst -> mkRU (use_R src) [dst]
230 FDIV sz src dst -> usageRM src dst
233 FETCHGOT reg -> mkRU [] [reg]
234 FETCHPC reg -> mkRU [] [reg]
238 SPILL reg slot -> mkRU [reg] []
239 RELOAD slot reg -> mkRU [] [reg]
241 _other -> panic "regUsage: unrecognised instr"
244 -- 2 operand form; first operand Read; second Written
245 usageRW :: Operand -> Operand -> RegUsage
246 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
247 usageRW op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
249 -- 2 operand form; first operand Read; second Modified
250 usageRM :: Operand -> Operand -> RegUsage
251 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
252 usageRM op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
254 -- 1 operand form; operand Modified
255 usageM :: Operand -> RegUsage
256 usageM (OpReg reg) = mkRU [reg] [reg]
257 usageM (OpAddr ea) = mkRUR (use_EA ea)
259 -- Registers defd when an operand is written.
260 def_W (OpReg reg) = [reg]
261 def_W (OpAddr ea) = []
263 -- Registers used when an operand is read.
264 use_R (OpReg reg) = [reg]
265 use_R (OpImm imm) = []
266 use_R (OpAddr ea) = use_EA ea
268 -- Registers used to compute an effective address.
269 use_EA (ImmAddr _ _) = []
270 use_EA (AddrBaseIndex base index _) =
271 use_base base $! use_index index
272 where use_base (EABaseReg r) x = r : x
274 use_index EAIndexNone = []
275 use_index (EAIndex i _) = [i]
277 mkRUR src = src' `seq` RU src' []
278 where src' = filter interesting src
280 mkRU src dst = src' `seq` dst' `seq` RU src' dst'
281 where src' = filter interesting src
282 dst' = filter interesting dst
284 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
285 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
286 #if sparc_TARGET_ARCH
288 regUsage instr = case instr of
289 SPILL reg slot -> usage ([reg], [])
290 RELOAD slot reg -> usage ([], [reg])
292 LD sz addr reg -> usage (regAddr addr, [reg])
293 ST sz reg addr -> usage (reg : regAddr addr, [])
294 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
295 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
296 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
297 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
298 RDY rd -> usage ([], [rd])
299 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
300 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
301 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
302 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
303 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
304 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
305 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
306 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
307 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
308 SETHI imm reg -> usage ([], [reg])
309 FABS s r1 r2 -> usage ([r1], [r2])
310 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
311 FCMP e s r1 r2 -> usage ([r1, r2], [])
312 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
313 FMOV s r1 r2 -> usage ([r1], [r2])
314 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
315 FNEG s r1 r2 -> usage ([r1], [r2])
316 FSQRT s r1 r2 -> usage ([r1], [r2])
317 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
318 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
320 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
321 JMP addr -> usage (regAddr addr, [])
323 CALL (Left imm) n True -> noUsage
324 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
325 CALL (Right reg) n True -> usage ([reg], [])
326 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
330 usage (src, dst) = RU (filter interesting src)
331 (filter interesting dst)
333 regAddr (AddrRegReg r1 r2) = [r1, r2]
334 regAddr (AddrRegImm r1 _) = [r1]
336 regRI (RIReg r) = [r]
339 #endif /* sparc_TARGET_ARCH */
340 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
341 #if powerpc_TARGET_ARCH
343 regUsage instr = case instr of
344 SPILL reg slot -> usage ([reg], [])
345 RELOAD slot reg -> usage ([], [reg])
347 LD sz reg addr -> usage (regAddr addr, [reg])
348 LA sz reg addr -> usage (regAddr addr, [reg])
349 ST sz reg addr -> usage (reg : regAddr addr, [])
350 STU sz reg addr -> usage (reg : regAddr addr, [])
351 LIS reg imm -> usage ([], [reg])
352 LI reg imm -> usage ([], [reg])
353 MR reg1 reg2 -> usage ([reg2], [reg1])
354 CMP sz reg ri -> usage (reg : regRI ri,[])
355 CMPL sz reg ri -> usage (reg : regRI ri,[])
356 BCC cond lbl -> noUsage
357 BCCFAR cond lbl -> noUsage
358 MTCTR reg -> usage ([reg],[])
359 BCTR targets -> noUsage
360 BL imm params -> usage (params, callClobberedRegs)
361 BCTRL params -> usage (params, callClobberedRegs)
362 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
363 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
364 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
365 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
366 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
367 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
368 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
369 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
370 MULLW_MayOflo reg1 reg2 reg3
371 -> usage ([reg2,reg3], [reg1])
372 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
373 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
374 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
375 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
376 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
377 NEG reg1 reg2 -> usage ([reg2], [reg1])
378 NOT reg1 reg2 -> usage ([reg2], [reg1])
379 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
380 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
381 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
382 RLWINM reg1 reg2 sh mb me
383 -> usage ([reg2], [reg1])
384 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
385 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
386 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
387 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
388 FNEG r1 r2 -> usage ([r2], [r1])
389 FCMP r1 r2 -> usage ([r1,r2], [])
390 FCTIWZ r1 r2 -> usage ([r2], [r1])
391 FRSP r1 r2 -> usage ([r2], [r1])
392 MFCR reg -> usage ([], [reg])
393 MFLR reg -> usage ([], [reg])
394 FETCHPC reg -> usage ([], [reg])
397 usage (src, dst) = RU (filter interesting src)
398 (filter interesting dst)
399 regAddr (AddrRegReg r1 r2) = [r1, r2]
400 regAddr (AddrRegImm r1 _) = [r1]
402 regRI (RIReg r) = [r]
404 #endif /* powerpc_TARGET_ARCH */
407 -- -----------------------------------------------------------------------------
408 -- Determine the possible destinations from the current instruction.
410 -- (we always assume that the next instruction is also a valid destination;
411 -- if this isn't the case then the jump should be at the end of the basic
414 jumpDests :: Instr -> [BlockId] -> [BlockId]
417 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
419 JMP_TBL _ ids -> ids ++ acc
420 #elif powerpc_TARGET_ARCH
422 BCCFAR _ id -> id : acc
423 BCTR targets -> targets ++ acc
424 #elif sparc_TARGET_ARCH
425 BI _ _ id -> id : acc
426 BF _ _ id -> id : acc
428 #error "RegAllocInfo.jumpDests not finished"
432 patchJump :: Instr -> BlockId -> BlockId -> Instr
434 patchJump insn old new
436 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
437 JXX cc id | id == old -> JXX cc new
438 JMP_TBL op ids -> error "Cannot patch JMP_TBL"
439 #elif powerpc_TARGET_ARCH
440 BCC cc id | id == old -> BCC cc new
441 BCCFAR cc id | id == old -> BCCFAR cc new
442 BCTR targets -> error "Cannot patch BCTR"
446 data JumpDest = DestBlockId BlockId | DestImm Imm
448 canShortcut :: Instr -> Maybe JumpDest
449 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
450 canShortcut (JXX ALWAYS id) = Just (DestBlockId id)
451 canShortcut (JMP (OpImm imm)) = Just (DestImm imm)
453 canShortcut _ = Nothing
455 shortcutJump :: (BlockId -> Maybe JumpDest) -> Instr -> Instr
456 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
457 shortcutJump fn insn@(JXX cc id) =
460 Just (DestBlockId id') -> shortcutJump fn (JXX cc id')
461 Just (DestImm imm) -> shortcutJump fn (JXX_GBL cc imm)
463 shortcutJump fn other = other
465 -- Here because it knows about JumpDest
466 shortcutStatic :: (BlockId -> Maybe JumpDest) -> CmmStatic -> CmmStatic
467 shortcutStatic fn (CmmStaticLit (CmmLabel lab))
468 | Just uq <- maybeAsmTemp lab
469 = CmmStaticLit (CmmLabel (shortBlockId fn (BlockId uq)))
470 shortcutStatic fn (CmmStaticLit (CmmLabelDiffOff lbl1 lbl2 off))
471 | Just uq <- maybeAsmTemp lbl1
472 = CmmStaticLit (CmmLabelDiffOff (shortBlockId fn (BlockId uq)) lbl2 off)
473 -- slightly dodgy, we're ignoring the second label, but this
474 -- works with the way we use CmmLabelDiffOff for jump tables now.
475 shortcutStatic fn other_static
478 shortBlockId fn blockid@(BlockId uq) =
480 Nothing -> mkAsmTempLabel uq
481 Just (DestBlockId blockid') -> shortBlockId fn blockid'
482 Just (DestImm (ImmCLbl lbl)) -> lbl
483 _other -> panic "shortBlockId"
485 -- -----------------------------------------------------------------------------
486 -- 'patchRegs' function
488 -- 'patchRegs' takes an instruction and applies the given mapping to
489 -- all the register references.
491 patchRegs :: Instr -> (Reg -> Reg) -> Instr
493 #if alpha_TARGET_ARCH
495 patchRegs instr env = case instr of
496 SPILL reg slot -> SPILL (env reg) slot
497 RELOAD slot reg -> RELOAD slot (env reg)
498 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
499 LDA reg addr -> LDA (env reg) (fixAddr addr)
500 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
501 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
502 LDI sz reg imm -> LDI sz (env reg) imm
503 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
504 CLR reg -> CLR (env reg)
505 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
506 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
507 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
508 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
509 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
510 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
511 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
512 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
513 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
514 NOT ar reg -> NOT (fixRI ar) (env reg)
515 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
516 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
517 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
518 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
519 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
520 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
521 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
522 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
523 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
524 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
525 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
526 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
527 FCLR reg -> FCLR (env reg)
528 FABS r1 r2 -> FABS (env r1) (env r2)
529 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
530 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
531 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
532 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
533 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
534 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
535 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
536 FMOV r1 r2 -> FMOV (env r1) (env r2)
537 BI cond reg lbl -> BI cond (env reg) lbl
538 BF cond reg lbl -> BF cond (env reg) lbl
539 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
540 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
543 fixAddr (AddrReg r1) = AddrReg (env r1)
544 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
545 fixAddr other = other
547 fixRI (RIReg r) = RIReg (env r)
550 #endif /* alpha_TARGET_ARCH */
551 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
552 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
554 patchRegs instr env = case instr of
555 MOV sz src dst -> patch2 (MOV sz) src dst
556 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
557 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
558 LEA sz src dst -> patch2 (LEA sz) src dst
559 ADD sz src dst -> patch2 (ADD sz) src dst
560 ADC sz src dst -> patch2 (ADC sz) src dst
561 SUB sz src dst -> patch2 (SUB sz) src dst
562 IMUL sz src dst -> patch2 (IMUL sz) src dst
563 IMUL2 sz src -> patch1 (IMUL2 sz) src
564 MUL sz src dst -> patch2 (MUL sz) src dst
565 IDIV sz op -> patch1 (IDIV sz) op
566 DIV sz op -> patch1 (DIV sz) op
567 AND sz src dst -> patch2 (AND sz) src dst
568 OR sz src dst -> patch2 (OR sz) src dst
569 XOR sz src dst -> patch2 (XOR sz) src dst
570 NOT sz op -> patch1 (NOT sz) op
571 NEGI sz op -> patch1 (NEGI sz) op
572 SHL sz imm dst -> patch1 (SHL sz imm) dst
573 SAR sz imm dst -> patch1 (SAR sz imm) dst
574 SHR sz imm dst -> patch1 (SHR sz imm) dst
575 BT sz imm src -> patch1 (BT sz imm) src
576 TEST sz src dst -> patch2 (TEST sz) src dst
577 CMP sz src dst -> patch2 (CMP sz) src dst
578 PUSH sz op -> patch1 (PUSH sz) op
579 POP sz op -> patch1 (POP sz) op
580 SETCC cond op -> patch1 (SETCC cond) op
581 JMP op -> patch1 JMP op
582 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
585 GMOV src dst -> GMOV (env src) (env dst)
586 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
587 GST sz src dst -> GST sz (env src) (lookupAddr dst)
589 GLDZ dst -> GLDZ (env dst)
590 GLD1 dst -> GLD1 (env dst)
592 GFTOI src dst -> GFTOI (env src) (env dst)
593 GDTOI src dst -> GDTOI (env src) (env dst)
595 GITOF src dst -> GITOF (env src) (env dst)
596 GITOD src dst -> GITOD (env src) (env dst)
598 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
599 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
600 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
601 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
603 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
604 GABS sz src dst -> GABS sz (env src) (env dst)
605 GNEG sz src dst -> GNEG sz (env src) (env dst)
606 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
607 GSIN sz l1 l2 src dst -> GSIN sz l1 l2 (env src) (env dst)
608 GCOS sz l1 l2 src dst -> GCOS sz l1 l2 (env src) (env dst)
609 GTAN sz l1 l2 src dst -> GTAN sz l1 l2 (env src) (env dst)
612 #if x86_64_TARGET_ARCH
613 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
614 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
615 CVTTSS2SIQ src dst -> CVTTSS2SIQ (patchOp src) (env dst)
616 CVTTSD2SIQ src dst -> CVTTSD2SIQ (patchOp src) (env dst)
617 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
618 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
619 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
622 CALL (Left imm) _ -> instr
623 CALL (Right reg) p -> CALL (Right (env reg)) p
625 FETCHGOT reg -> FETCHGOT (env reg)
626 FETCHPC reg -> FETCHPC (env reg)
631 SPILL reg slot -> SPILL (env reg) slot
632 RELOAD slot reg -> RELOAD slot (env reg)
638 _other -> panic "patchRegs: unrecognised instr"
641 patch1 insn op = insn $! patchOp op
642 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
644 patchOp (OpReg reg) = OpReg $! env reg
645 patchOp (OpImm imm) = OpImm imm
646 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
648 lookupAddr (ImmAddr imm off) = ImmAddr imm off
649 lookupAddr (AddrBaseIndex base index disp)
650 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
652 lookupBase EABaseNone = EABaseNone
653 lookupBase EABaseRip = EABaseRip
654 lookupBase (EABaseReg r) = EABaseReg (env r)
656 lookupIndex EAIndexNone = EAIndexNone
657 lookupIndex (EAIndex r i) = EAIndex (env r) i
659 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
660 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
661 #if sparc_TARGET_ARCH
663 patchRegs instr env = case instr of
664 SPILL reg slot -> SPILL (env reg) slot
665 RELOAD slot reg -> RELOAD slot (env reg)
666 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
667 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
668 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
669 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
670 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
671 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
672 RDY rd -> RDY (env rd)
673 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
674 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
675 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
676 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
677 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
678 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
679 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
680 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
681 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
682 SETHI imm reg -> SETHI imm (env reg)
683 FABS s r1 r2 -> FABS s (env r1) (env r2)
684 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
685 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
686 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
687 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
688 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
689 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
690 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
691 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
692 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
693 JMP addr -> JMP (fixAddr addr)
694 CALL (Left i) n t -> CALL (Left i) n t
695 CALL (Right r) n t -> CALL (Right (env r)) n t
698 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
699 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
701 fixRI (RIReg r) = RIReg (env r)
704 #endif /* sparc_TARGET_ARCH */
705 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
706 #if powerpc_TARGET_ARCH
708 patchRegs instr env = case instr of
709 SPILL reg slot -> SPILL (env reg) slot
710 RELOAD slot reg -> RELOAD slot (env reg)
712 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
713 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
714 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
715 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
716 LIS reg imm -> LIS (env reg) imm
717 LI reg imm -> LI (env reg) imm
718 MR reg1 reg2 -> MR (env reg1) (env reg2)
719 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
720 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
721 BCC cond lbl -> BCC cond lbl
722 BCCFAR cond lbl -> BCCFAR cond lbl
723 MTCTR reg -> MTCTR (env reg)
724 BCTR targets -> BCTR targets
725 BL imm argRegs -> BL imm argRegs -- argument regs
726 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
727 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
728 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
729 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
730 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
731 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
732 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
733 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
734 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
735 MULLW_MayOflo reg1 reg2 reg3
736 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
737 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
738 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
739 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
740 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
741 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
742 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
743 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
744 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
745 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
746 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
747 RLWINM reg1 reg2 sh mb me
748 -> RLWINM (env reg1) (env reg2) sh mb me
749 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
750 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
751 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
752 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
753 FNEG r1 r2 -> FNEG (env r1) (env r2)
754 FCMP r1 r2 -> FCMP (env r1) (env r2)
755 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
756 FRSP r1 r2 -> FRSP (env r1) (env r2)
757 MFCR reg -> MFCR (env reg)
758 MFLR reg -> MFLR (env reg)
759 FETCHPC reg -> FETCHPC (env reg)
762 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
763 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
765 fixRI (RIReg r) = RIReg (env r)
767 #endif /* powerpc_TARGET_ARCH */
769 -- -----------------------------------------------------------------------------
770 -- Detecting reg->reg moves
772 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
773 -- by assigning the src and dest temporaries to the same real register.
775 isRegRegMove :: Instr -> Maybe (Reg,Reg)
777 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
779 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
781 #elif powerpc_TARGET_ARCH
782 isRegRegMove (MR dst src) = Just (src,dst)
784 #elif sparc_TARGET_ARCH
787 ADD False False src (RIReg src2) dst
788 | g0 == src2 -> Just (src, dst)
790 FMOV FF64 src dst -> Just (src, dst)
791 FMOV FF32 src dst -> Just (src, dst)
794 isRegRegMove _ = Nothing
796 -- -----------------------------------------------------------------------------
797 -- Generating spill instructions
800 :: Reg -- register to spill
801 -> Int -- current stack delta
802 -> Int -- spill slot to use
804 mkSpillInstr reg delta slot
805 = let off = spillSlotToOffset slot
807 #ifdef alpha_TARGET_ARCH
808 {-Alpha: spill below the stack pointer (?)-}
809 ST sz dyn (spRel (- (off `div` 8)))
811 #ifdef i386_TARGET_ARCH
812 let off_w = (off-delta) `div` 4
813 in case regClass reg of
814 RcInteger -> MOV II32 (OpReg reg) (OpAddr (spRel off_w))
815 _ -> GST FF80 reg (spRel off_w) {- RcFloat/RcDouble -}
817 #ifdef x86_64_TARGET_ARCH
818 let off_w = (off-delta) `div` 8
819 in case regClass reg of
820 RcInteger -> MOV II64 (OpReg reg) (OpAddr (spRel off_w))
821 RcDouble -> MOV FF64 (OpReg reg) (OpAddr (spRel off_w))
822 -- ToDo: will it work to always spill as a double?
823 -- does that cause a stall if the data was a float?
825 #ifdef sparc_TARGET_ARCH
826 {-SPARC: spill below frame pointer leaving 2 words/spill-}
827 let{off_w = 1 + (off `div` 4);
828 sz = case regClass reg of {
832 in ST sz reg (fpRel (negate off_w))
834 #ifdef powerpc_TARGET_ARCH
835 let sz = case regClass reg of
838 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
843 :: Reg -- register to load
844 -> Int -- current stack delta
845 -> Int -- spill slot to use
847 mkLoadInstr reg delta slot
848 = let off = spillSlotToOffset slot
850 #if alpha_TARGET_ARCH
851 LD sz dyn (spRel (- (off `div` 8)))
854 let off_w = (off-delta) `div` 4
855 in case regClass reg of {
856 RcInteger -> MOV II32 (OpAddr (spRel off_w)) (OpReg reg);
857 _ -> GLD FF80 (spRel off_w) reg} {- RcFloat/RcDouble -}
859 #if x86_64_TARGET_ARCH
860 let off_w = (off-delta) `div` 8
861 in case regClass reg of
862 RcInteger -> MOV II64 (OpAddr (spRel off_w)) (OpReg reg)
863 _ -> MOV FF64 (OpAddr (spRel off_w)) (OpReg reg)
865 #if sparc_TARGET_ARCH
866 let{off_w = 1 + (off `div` 4);
867 sz = case regClass reg of {
871 in LD sz (fpRel (- off_w)) reg
873 #if powerpc_TARGET_ARCH
874 let sz = case regClass reg of
877 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
884 mkRegRegMoveInstr src dst
885 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
886 = case regClass src of
887 RcInteger -> MOV wordSize (OpReg src) (OpReg dst)
889 RcDouble -> GMOV src dst
891 RcDouble -> MOV FF64 (OpReg src) (OpReg dst)
893 #elif powerpc_TARGET_ARCH
895 #elif sparc_TARGET_ARCH
896 = case regClass src of
897 RcInteger -> ADD False False src (RIReg g0) dst
898 RcDouble -> FMOV FF64 src dst
899 RcFloat -> FMOV FF32 src dst
901 #error ToDo: mkRegRegMoveInstr
907 #if alpha_TARGET_ARCH
908 mkBranchInstr id = [BR id]
911 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
912 mkBranchInstr id = [JXX ALWAYS id]
915 #if sparc_TARGET_ARCH
916 mkBranchInstr id = [BI ALWAYS False id, NOP]
919 #if powerpc_TARGET_ARCH
920 mkBranchInstr id = [BCC ALWAYS id]
925 spillSlotSize = IF_ARCH_i386(12, 8)
928 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
930 -- convert a spill slot number to a *byte* offset, with no sign:
931 -- decide on a per arch basis whether you are spilling above or below
932 -- the C stack pointer.
933 spillSlotToOffset :: Int -> Int
934 spillSlotToOffset slot
935 | slot >= 0 && slot < maxSpillSlots
936 = 64 + spillSlotSize * slot
938 = pprPanic "spillSlotToOffset:"
939 ( text "invalid spill location: " <> int slot
940 $$ text "maxSpillSlots: " <> int maxSpillSlots)