1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
27 #include "HsVersions.h"
29 import Cmm ( BlockId )
30 import MachOp ( MachRep(..), wordRep )
34 import Constants ( rESERVED_C_STACK_BYTES )
37 -- -----------------------------------------------------------------------------
40 -- @regUsage@ returns the sets of src and destination registers used
41 -- by a particular instruction. Machine registers that are
42 -- pre-allocated to stgRegs are filtered out, because they are
43 -- uninteresting from a register allocation standpoint. (We wouldn't
44 -- want them to end up on the free list!) As far as we are concerned,
45 -- the fixed registers simply don't exist (for allocation purposes,
48 -- regUsage doesn't need to do any trickery for jumps and such. Just
49 -- state precisely the regs read and written by that insn. The
50 -- consequences of control flow transfers, as far as register
51 -- allocation goes, are taken care of by the register allocator.
53 data RegUsage = RU [Reg] [Reg]
58 regUsage :: Instr -> RegUsage
60 interesting (VirtualRegI _) = True
61 interesting (VirtualRegHi _) = True
62 interesting (VirtualRegF _) = True
63 interesting (VirtualRegD _) = True
64 interesting (RealReg i) = isFastTrue (freeReg i)
68 regUsage instr = case instr of
69 LD B reg addr -> usage (regAddr addr, [reg, t9])
70 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
71 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
73 LD sz reg addr -> usage (regAddr addr, [reg])
74 LDA reg addr -> usage (regAddr addr, [reg])
75 LDAH reg addr -> usage (regAddr addr, [reg])
76 LDGP reg addr -> usage (regAddr addr, [reg])
77 LDI sz reg imm -> usage ([], [reg])
78 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
79 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
80 ST sz reg addr -> usage (reg : regAddr addr, [])
81 CLR reg -> usage ([], [reg])
82 ABS sz ri reg -> usage (regRI ri, [reg])
83 NEG sz ov ri reg -> usage (regRI ri, [reg])
84 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
89 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
91 NOT ri reg -> usage (regRI ri, [reg])
92 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
104 FCLR reg -> usage ([], [reg])
105 FABS r1 r2 -> usage ([r1], [r2])
106 FNEG sz r1 r2 -> usage ([r1], [r2])
107 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
111 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
112 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
113 FMOV r1 r2 -> usage ([r1], [r2])
116 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
117 BI cond reg lbl -> usage ([reg], [])
118 BF cond reg lbl -> usage ([reg], [])
119 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
121 BSR _ n -> RU (argRegSet n) callClobberedRegSet
122 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
127 usage (src, dst) = RU (mkRegSet (filter interesting src))
128 (mkRegSet (filter interesting dst))
130 interesting (FixedReg _) = False
133 regAddr (AddrReg r1) = [r1]
134 regAddr (AddrRegImm r1 _) = [r1]
135 regAddr (AddrImm _) = []
137 regRI (RIReg r) = [r]
140 #endif /* alpha_TARGET_ARCH */
141 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
142 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
144 regUsage instr = case instr of
145 MOV sz src dst -> usageRW src dst
146 MOVZxL sz src dst -> usageRW src dst
147 MOVSxL sz src dst -> usageRW src dst
148 LEA sz src dst -> usageRW src dst
149 ADD sz src dst -> usageRM src dst
150 ADC sz src dst -> usageRM src dst
151 SUB sz src dst -> usageRM src dst
152 IMUL sz src dst -> usageRM src dst
153 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
154 MUL sz src dst -> usageRM src dst
155 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
157 AND sz src dst -> usageRM src dst
158 OR sz src dst -> usageRM src dst
159 XOR sz src dst -> usageRM src dst
160 NOT sz op -> usageM op
161 NEGI sz op -> usageM op
162 SHL sz imm dst -> usageRM imm dst
163 SAR sz imm dst -> usageRM imm dst
164 SHR sz imm dst -> usageRM imm dst
165 BT sz imm src -> mkRUR (use_R src)
167 PUSH sz op -> mkRUR (use_R op)
168 POP sz op -> mkRU [] (def_W op)
169 TEST sz src dst -> mkRUR (use_R src ++ use_R dst)
170 CMP sz src dst -> mkRUR (use_R src ++ use_R dst)
171 SETCC cond op -> mkRU [] (def_W op)
172 JXX cond lbl -> mkRU [] []
173 JMP op -> mkRUR (use_R op)
174 JMP_TBL op ids -> mkRUR (use_R op)
175 CALL (Left imm) params -> mkRU params callClobberedRegs
176 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
177 CLTD sz -> mkRU [eax] [edx]
181 GMOV src dst -> mkRU [src] [dst]
182 GLD sz src dst -> mkRU (use_EA src) [dst]
183 GST sz src dst -> mkRUR (src : use_EA dst)
185 GLDZ dst -> mkRU [] [dst]
186 GLD1 dst -> mkRU [] [dst]
188 GFTOI src dst -> mkRU [src] [dst]
189 GDTOI src dst -> mkRU [src] [dst]
191 GITOF src dst -> mkRU [src] [dst]
192 GITOD src dst -> mkRU [src] [dst]
194 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
195 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
196 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
197 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
199 GCMP sz src1 src2 -> mkRUR [src1,src2]
200 GABS sz src dst -> mkRU [src] [dst]
201 GNEG sz src dst -> mkRU [src] [dst]
202 GSQRT sz src dst -> mkRU [src] [dst]
203 GSIN sz src dst -> mkRU [src] [dst]
204 GCOS sz src dst -> mkRU [src] [dst]
205 GTAN sz src dst -> mkRU [src] [dst]
208 #if x86_64_TARGET_ARCH
209 CVTSS2SD src dst -> mkRU [src] [dst]
210 CVTSD2SS src dst -> mkRU [src] [dst]
211 CVTSS2SI src dst -> mkRU (use_R src) [dst]
212 CVTSD2SI src dst -> mkRU (use_R src) [dst]
213 CVTSI2SS src dst -> mkRU (use_R src) [dst]
214 CVTSI2SD src dst -> mkRU (use_R src) [dst]
215 FDIV sz src dst -> usageRM src dst
218 FETCHGOT reg -> mkRU [] [reg]
219 FETCHPC reg -> mkRU [] [reg]
224 _other -> panic "regUsage: unrecognised instr"
227 #if x86_64_TARGET_ARCH
228 -- call parameters: include %eax, because it is used
229 -- to pass the number of SSE reg arguments to varargs fns.
230 params = eax : allArgRegs ++ allFPArgRegs
233 -- 2 operand form; first operand Read; second Written
234 usageRW :: Operand -> Operand -> RegUsage
235 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
236 usageRW op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
238 -- 2 operand form; first operand Read; second Modified
239 usageRM :: Operand -> Operand -> RegUsage
240 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
241 usageRM op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
243 -- 1 operand form; operand Modified
244 usageM :: Operand -> RegUsage
245 usageM (OpReg reg) = mkRU [reg] [reg]
246 usageM (OpAddr ea) = mkRUR (use_EA ea)
248 -- Registers defd when an operand is written.
249 def_W (OpReg reg) = [reg]
250 def_W (OpAddr ea) = []
252 -- Registers used when an operand is read.
253 use_R (OpReg reg) = [reg]
254 use_R (OpImm imm) = []
255 use_R (OpAddr ea) = use_EA ea
257 -- Registers used to compute an effective address.
258 use_EA (ImmAddr _ _) = []
259 use_EA (AddrBaseIndex base index _) =
260 use_base base $! use_index index
261 where use_base (EABaseReg r) x = r : x
263 use_index EAIndexNone = []
264 use_index (EAIndex i _) = [i]
266 mkRUR src = src' `seq` RU src' []
267 where src' = filter interesting src
269 mkRU src dst = src' `seq` dst' `seq` RU src' dst'
270 where src' = filter interesting src
271 dst' = filter interesting dst
273 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
274 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
275 #if sparc_TARGET_ARCH
277 regUsage instr = case instr of
278 LD sz addr reg -> usage (regAddr addr, [reg])
279 ST sz reg addr -> usage (reg : regAddr addr, [])
280 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
281 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
282 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
284 RDY rd -> usage ([], [rd])
285 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
289 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
290 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
291 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
292 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
293 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
294 SETHI imm reg -> usage ([], [reg])
295 FABS s r1 r2 -> usage ([r1], [r2])
296 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
297 FCMP e s r1 r2 -> usage ([r1, r2], [])
298 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
299 FMOV s r1 r2 -> usage ([r1], [r2])
300 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
301 FNEG s r1 r2 -> usage ([r1], [r2])
302 FSQRT s r1 r2 -> usage ([r1], [r2])
303 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
304 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
306 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
307 JMP addr -> usage (regAddr addr, [])
309 CALL (Left imm) n True -> noUsage
310 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
311 CALL (Right reg) n True -> usage ([reg], [])
312 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
316 usage (src, dst) = RU (filter interesting src)
317 (filter interesting dst)
319 regAddr (AddrRegReg r1 r2) = [r1, r2]
320 regAddr (AddrRegImm r1 _) = [r1]
322 regRI (RIReg r) = [r]
325 #endif /* sparc_TARGET_ARCH */
326 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
327 #if powerpc_TARGET_ARCH
329 regUsage instr = case instr of
330 LD sz reg addr -> usage (regAddr addr, [reg])
331 LA sz reg addr -> usage (regAddr addr, [reg])
332 ST sz reg addr -> usage (reg : regAddr addr, [])
333 STU sz reg addr -> usage (reg : regAddr addr, [])
334 LIS reg imm -> usage ([], [reg])
335 LI reg imm -> usage ([], [reg])
336 MR reg1 reg2 -> usage ([reg2], [reg1])
337 CMP sz reg ri -> usage (reg : regRI ri,[])
338 CMPL sz reg ri -> usage (reg : regRI ri,[])
339 BCC cond lbl -> noUsage
340 MTCTR reg -> usage ([reg],[])
341 BCTR targets -> noUsage
342 BL imm params -> usage (params, callClobberedRegs)
343 BCTRL params -> usage (params, callClobberedRegs)
344 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
345 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
346 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
347 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
348 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
349 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
350 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
351 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
352 MULLW_MayOflo reg1 reg2 reg3
353 -> usage ([reg2,reg3], [reg1])
354 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
355 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
356 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
357 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
358 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
359 NEG reg1 reg2 -> usage ([reg2], [reg1])
360 NOT reg1 reg2 -> usage ([reg2], [reg1])
361 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
362 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
363 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
364 RLWINM reg1 reg2 sh mb me
365 -> usage ([reg2], [reg1])
366 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
367 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
368 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
369 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
370 FNEG r1 r2 -> usage ([r2], [r1])
371 FCMP r1 r2 -> usage ([r1,r2], [])
372 FCTIWZ r1 r2 -> usage ([r2], [r1])
373 FRSP r1 r2 -> usage ([r2], [r1])
374 MFCR reg -> usage ([], [reg])
375 MFLR reg -> usage ([], [reg])
376 FETCHPC reg -> usage ([], [reg])
379 usage (src, dst) = RU (filter interesting src)
380 (filter interesting dst)
381 regAddr (AddrRegReg r1 r2) = [r1, r2]
382 regAddr (AddrRegImm r1 _) = [r1]
384 regRI (RIReg r) = [r]
386 #endif /* powerpc_TARGET_ARCH */
389 -- -----------------------------------------------------------------------------
390 -- Determine the possible destinations from the current instruction.
392 -- (we always assume that the next instruction is also a valid destination;
393 -- if this isn't the case then the jump should be at the end of the basic
396 jumpDests :: Instr -> [BlockId] -> [BlockId]
399 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
401 JMP_TBL _ ids -> ids ++ acc
402 #elif powerpc_TARGET_ARCH
404 BCTR targets -> targets ++ acc
408 patchJump :: Instr -> BlockId -> BlockId -> Instr
410 patchJump insn old new
412 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
413 JXX cc id | id == old -> JXX cc new
414 JMP_TBL op ids -> error "Cannot patch JMP_TBL"
415 #elif powerpc_TARGET_ARCH
416 BCC cc id | id == old -> BCC cc new
417 BCTR targets -> error "Cannot patch BCTR"
421 -- -----------------------------------------------------------------------------
422 -- 'patchRegs' function
424 -- 'patchRegs' takes an instruction and applies the given mapping to
425 -- all the register references.
427 patchRegs :: Instr -> (Reg -> Reg) -> Instr
429 #if alpha_TARGET_ARCH
431 patchRegs instr env = case instr of
432 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
433 LDA reg addr -> LDA (env reg) (fixAddr addr)
434 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
435 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
436 LDI sz reg imm -> LDI sz (env reg) imm
437 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
438 CLR reg -> CLR (env reg)
439 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
440 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
441 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
442 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
443 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
444 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
445 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
446 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
447 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
448 NOT ar reg -> NOT (fixRI ar) (env reg)
449 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
450 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
451 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
452 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
453 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
454 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
455 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
456 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
457 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
458 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
459 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
460 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
461 FCLR reg -> FCLR (env reg)
462 FABS r1 r2 -> FABS (env r1) (env r2)
463 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
464 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
465 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
466 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
467 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
468 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
469 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
470 FMOV r1 r2 -> FMOV (env r1) (env r2)
471 BI cond reg lbl -> BI cond (env reg) lbl
472 BF cond reg lbl -> BF cond (env reg) lbl
473 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
474 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
477 fixAddr (AddrReg r1) = AddrReg (env r1)
478 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
479 fixAddr other = other
481 fixRI (RIReg r) = RIReg (env r)
484 #endif /* alpha_TARGET_ARCH */
485 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
486 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
488 patchRegs instr env = case instr of
489 MOV sz src dst -> patch2 (MOV sz) src dst
490 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
491 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
492 LEA sz src dst -> patch2 (LEA sz) src dst
493 ADD sz src dst -> patch2 (ADD sz) src dst
494 ADC sz src dst -> patch2 (ADC sz) src dst
495 SUB sz src dst -> patch2 (SUB sz) src dst
496 IMUL sz src dst -> patch2 (IMUL sz) src dst
497 IMUL2 sz src -> patch1 (IMUL2 sz) src
498 MUL sz src dst -> patch2 (MUL sz) src dst
499 IDIV sz op -> patch1 (IDIV sz) op
500 DIV sz op -> patch1 (DIV sz) op
501 AND sz src dst -> patch2 (AND sz) src dst
502 OR sz src dst -> patch2 (OR sz) src dst
503 XOR sz src dst -> patch2 (XOR sz) src dst
504 NOT sz op -> patch1 (NOT sz) op
505 NEGI sz op -> patch1 (NEGI sz) op
506 SHL sz imm dst -> patch1 (SHL sz imm) dst
507 SAR sz imm dst -> patch1 (SAR sz imm) dst
508 SHR sz imm dst -> patch1 (SHR sz imm) dst
509 BT sz imm src -> patch1 (BT sz imm) src
510 TEST sz src dst -> patch2 (TEST sz) src dst
511 CMP sz src dst -> patch2 (CMP sz) src dst
512 PUSH sz op -> patch1 (PUSH sz) op
513 POP sz op -> patch1 (POP sz) op
514 SETCC cond op -> patch1 (SETCC cond) op
515 JMP op -> patch1 JMP op
516 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
519 GMOV src dst -> GMOV (env src) (env dst)
520 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
521 GST sz src dst -> GST sz (env src) (lookupAddr dst)
523 GLDZ dst -> GLDZ (env dst)
524 GLD1 dst -> GLD1 (env dst)
526 GFTOI src dst -> GFTOI (env src) (env dst)
527 GDTOI src dst -> GDTOI (env src) (env dst)
529 GITOF src dst -> GITOF (env src) (env dst)
530 GITOD src dst -> GITOD (env src) (env dst)
532 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
533 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
534 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
535 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
537 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
538 GABS sz src dst -> GABS sz (env src) (env dst)
539 GNEG sz src dst -> GNEG sz (env src) (env dst)
540 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
541 GSIN sz src dst -> GSIN sz (env src) (env dst)
542 GCOS sz src dst -> GCOS sz (env src) (env dst)
543 GTAN sz src dst -> GTAN sz (env src) (env dst)
546 #if x86_64_TARGET_ARCH
547 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
548 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
549 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
550 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
551 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
552 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
553 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
556 CALL (Left imm) _ -> instr
557 CALL (Right reg) p -> CALL (Right (env reg)) p
559 FETCHGOT reg -> FETCHGOT (env reg)
560 FETCHPC reg -> FETCHPC (env reg)
568 _other -> panic "patchRegs: unrecognised instr"
571 patch1 insn op = insn $! patchOp op
572 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
574 patchOp (OpReg reg) = OpReg $! env reg
575 patchOp (OpImm imm) = OpImm imm
576 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
578 lookupAddr (ImmAddr imm off) = ImmAddr imm off
579 lookupAddr (AddrBaseIndex base index disp)
580 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
582 lookupBase EABaseNone = EABaseNone
583 lookupBase EABaseRip = EABaseRip
584 lookupBase (EABaseReg r) = EABaseReg (env r)
586 lookupIndex EAIndexNone = EAIndexNone
587 lookupIndex (EAIndex r i) = EAIndex (env r) i
589 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
590 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
591 #if sparc_TARGET_ARCH
593 patchRegs instr env = case instr of
594 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
595 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
596 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
597 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
598 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
599 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
600 RDY rd -> RDY (env rd)
601 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
602 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
603 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
604 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
605 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
606 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
607 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
608 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
609 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
610 SETHI imm reg -> SETHI imm (env reg)
611 FABS s r1 r2 -> FABS s (env r1) (env r2)
612 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
613 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
614 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
615 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
616 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
617 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
618 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
619 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
620 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
621 JMP addr -> JMP (fixAddr addr)
622 CALL (Left i) n t -> CALL (Left i) n t
623 CALL (Right r) n t -> CALL (Right (env r)) n t
626 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
627 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
629 fixRI (RIReg r) = RIReg (env r)
632 #endif /* sparc_TARGET_ARCH */
633 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
634 #if powerpc_TARGET_ARCH
636 patchRegs instr env = case instr of
637 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
638 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
639 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
640 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
641 LIS reg imm -> LIS (env reg) imm
642 LI reg imm -> LI (env reg) imm
643 MR reg1 reg2 -> MR (env reg1) (env reg2)
644 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
645 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
646 BCC cond lbl -> BCC cond lbl
647 MTCTR reg -> MTCTR (env reg)
648 BCTR targets -> BCTR targets
649 BL imm argRegs -> BL imm argRegs -- argument regs
650 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
651 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
652 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
653 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
654 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
655 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
656 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
657 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
658 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
659 MULLW_MayOflo reg1 reg2 reg3
660 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
661 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
662 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
663 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
664 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
665 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
666 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
667 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
668 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
669 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
670 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
671 RLWINM reg1 reg2 sh mb me
672 -> RLWINM (env reg1) (env reg2) sh mb me
673 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
674 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
675 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
676 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
677 FNEG r1 r2 -> FNEG (env r1) (env r2)
678 FCMP r1 r2 -> FCMP (env r1) (env r2)
679 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
680 FRSP r1 r2 -> FRSP (env r1) (env r2)
681 MFCR reg -> MFCR (env reg)
682 MFLR reg -> MFLR (env reg)
683 FETCHPC reg -> FETCHPC (env reg)
686 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
687 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
689 fixRI (RIReg r) = RIReg (env r)
691 #endif /* powerpc_TARGET_ARCH */
693 -- -----------------------------------------------------------------------------
694 -- Detecting reg->reg moves
696 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
697 -- by assigning the src and dest temporaries to the same real register.
699 isRegRegMove :: Instr -> Maybe (Reg,Reg)
700 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
702 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
703 #elif powerpc_TARGET_ARCH
704 isRegRegMove (MR dst src) = Just (src,dst)
706 #warning ToDo: isRegRegMove
708 isRegRegMove _ = Nothing
710 -- -----------------------------------------------------------------------------
711 -- Generating spill instructions
714 :: Reg -- register to spill (should be a real)
715 -> Int -- current stack delta
716 -> Int -- spill slot to use
718 mkSpillInstr reg delta slot
719 = ASSERT(isRealReg reg)
721 off = spillSlotToOffset slot
723 #ifdef alpha_TARGET_ARCH
724 {-Alpha: spill below the stack pointer (?)-}
725 ST sz dyn (spRel (- (off `div` 8)))
727 #ifdef i386_TARGET_ARCH
728 let off_w = (off-delta) `div` 4
729 in case regClass reg of
730 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
731 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
733 #ifdef x86_64_TARGET_ARCH
734 let off_w = (off-delta) `div` 8
735 in case regClass reg of
736 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
737 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
738 -- ToDo: will it work to always spill as a double?
739 -- does that cause a stall if the data was a float?
741 #ifdef sparc_TARGET_ARCH
742 {-SPARC: spill below frame pointer leaving 2 words/spill-}
743 let{off_w = 1 + (off `div` 4);
744 sz = case regClass reg of {
748 in ST sz reg (fpRel (- off_w))
750 #ifdef powerpc_TARGET_ARCH
751 let sz = case regClass reg of
754 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
759 :: Reg -- register to load (should be a real)
760 -> Int -- current stack delta
761 -> Int -- spill slot to use
763 mkLoadInstr reg delta slot
764 = ASSERT(isRealReg reg)
766 off = spillSlotToOffset slot
768 #if alpha_TARGET_ARCH
769 LD sz dyn (spRel (- (off `div` 8)))
772 let off_w = (off-delta) `div` 4
773 in case regClass reg of {
774 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
775 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
777 #if x86_64_TARGET_ARCH
778 let off_w = (off-delta) `div` 8
779 in case regClass reg of
780 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
781 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
783 #if sparc_TARGET_ARCH
784 let{off_w = 1 + (off `div` 4);
785 sz = case regClass reg of {
789 in LD sz (fpRel (- off_w)) reg
791 #if powerpc_TARGET_ARCH
792 let sz = case regClass reg of
795 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
802 mkRegRegMoveInstr src dst
803 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
804 = case regClass src of
805 RcInteger -> MOV wordRep (OpReg src) (OpReg dst)
807 RcDouble -> GMOV src dst
809 RcDouble -> MOV F64 (OpReg src) (OpReg dst)
811 #elif powerpc_TARGET_ARCH
818 #if alpha_TARGET_ARCH
819 mkBranchInstr id = [BR id]
822 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
823 mkBranchInstr id = [JXX ALWAYS id]
826 #if sparc_TARGET_ARCH
827 mkBranchInstr (BlockId id) = [BI ALWAYS False (ImmCLbl (mkAsmTempLabel id)), NOP]
830 #if powerpc_TARGET_ARCH
831 mkBranchInstr id = [BCC ALWAYS id]
836 spillSlotSize = IF_ARCH_i386(12, 8)
839 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
841 -- convert a spill slot number to a *byte* offset, with no sign:
842 -- decide on a per arch basis whether you are spilling above or below
843 -- the C stack pointer.
844 spillSlotToOffset :: Int -> Int
845 spillSlotToOffset slot
846 | slot >= 0 && slot < maxSpillSlots
847 = 64 + spillSlotSize * slot
849 = pprPanic "spillSlotToOffset:"
850 (text "invalid spill location: " <> int slot)