1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
27 #include "HsVersions.h"
29 import Cmm ( BlockId )
30 import MachOp ( MachRep(..), wordRep )
34 import Constants ( rESERVED_C_STACK_BYTES )
37 -- -----------------------------------------------------------------------------
40 -- @regUsage@ returns the sets of src and destination registers used
41 -- by a particular instruction. Machine registers that are
42 -- pre-allocated to stgRegs are filtered out, because they are
43 -- uninteresting from a register allocation standpoint. (We wouldn't
44 -- want them to end up on the free list!) As far as we are concerned,
45 -- the fixed registers simply don't exist (for allocation purposes,
48 -- regUsage doesn't need to do any trickery for jumps and such. Just
49 -- state precisely the regs read and written by that insn. The
50 -- consequences of control flow transfers, as far as register
51 -- allocation goes, are taken care of by the register allocator.
53 data RegUsage = RU [Reg] [Reg]
58 regUsage :: Instr -> RegUsage
60 interesting (VirtualRegI _) = True
61 interesting (VirtualRegHi _) = True
62 interesting (VirtualRegF _) = True
63 interesting (VirtualRegD _) = True
64 interesting (RealReg i) = isFastTrue (freeReg i)
68 regUsage instr = case instr of
69 LD B reg addr -> usage (regAddr addr, [reg, t9])
70 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
71 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
73 LD sz reg addr -> usage (regAddr addr, [reg])
74 LDA reg addr -> usage (regAddr addr, [reg])
75 LDAH reg addr -> usage (regAddr addr, [reg])
76 LDGP reg addr -> usage (regAddr addr, [reg])
77 LDI sz reg imm -> usage ([], [reg])
78 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
79 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
80 ST sz reg addr -> usage (reg : regAddr addr, [])
81 CLR reg -> usage ([], [reg])
82 ABS sz ri reg -> usage (regRI ri, [reg])
83 NEG sz ov ri reg -> usage (regRI ri, [reg])
84 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
89 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
91 NOT ri reg -> usage (regRI ri, [reg])
92 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
104 FCLR reg -> usage ([], [reg])
105 FABS r1 r2 -> usage ([r1], [r2])
106 FNEG sz r1 r2 -> usage ([r1], [r2])
107 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
111 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
112 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
113 FMOV r1 r2 -> usage ([r1], [r2])
116 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
117 BI cond reg lbl -> usage ([reg], [])
118 BF cond reg lbl -> usage ([reg], [])
119 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
121 BSR _ n -> RU (argRegSet n) callClobberedRegSet
122 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
127 usage (src, dst) = RU (mkRegSet (filter interesting src))
128 (mkRegSet (filter interesting dst))
130 interesting (FixedReg _) = False
133 regAddr (AddrReg r1) = [r1]
134 regAddr (AddrRegImm r1 _) = [r1]
135 regAddr (AddrImm _) = []
137 regRI (RIReg r) = [r]
140 #endif /* alpha_TARGET_ARCH */
141 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
142 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
144 regUsage instr = case instr of
145 MOV sz src dst -> usageRW src dst
146 MOVZxL sz src dst -> usageRW src dst
147 MOVSxL sz src dst -> usageRW src dst
148 LEA sz src dst -> usageRW src dst
149 ADD sz src dst -> usageRM src dst
150 ADC sz src dst -> usageRM src dst
151 SUB sz src dst -> usageRM src dst
152 IMUL sz src dst -> usageRM src dst
153 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
154 MUL sz src dst -> usageRM src dst
155 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
157 AND sz src dst -> usageRM src dst
158 OR sz src dst -> usageRM src dst
159 XOR sz (OpReg src) (OpReg dst)
160 | src == dst -> mkRU [] [dst]
161 XOR sz src dst -> usageRM src dst
162 NOT sz op -> usageM op
163 NEGI sz op -> usageM op
164 SHL sz imm dst -> usageRM imm dst
165 SAR sz imm dst -> usageRM imm dst
166 SHR sz imm dst -> usageRM imm dst
167 BT sz imm src -> mkRUR (use_R src)
169 PUSH sz op -> mkRUR (use_R op)
170 POP sz op -> mkRU [] (def_W op)
171 TEST sz src dst -> mkRUR (use_R src ++ use_R dst)
172 CMP sz src dst -> mkRUR (use_R src ++ use_R dst)
173 SETCC cond op -> mkRU [] (def_W op)
174 JXX cond lbl -> mkRU [] []
175 JMP op -> mkRUR (use_R op)
176 JMP_TBL op ids -> mkRUR (use_R op)
177 CALL (Left imm) params -> mkRU params callClobberedRegs
178 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
179 CLTD sz -> mkRU [eax] [edx]
183 GMOV src dst -> mkRU [src] [dst]
184 GLD sz src dst -> mkRU (use_EA src) [dst]
185 GST sz src dst -> mkRUR (src : use_EA dst)
187 GLDZ dst -> mkRU [] [dst]
188 GLD1 dst -> mkRU [] [dst]
190 GFTOI src dst -> mkRU [src] [dst]
191 GDTOI src dst -> mkRU [src] [dst]
193 GITOF src dst -> mkRU [src] [dst]
194 GITOD src dst -> mkRU [src] [dst]
196 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
197 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
198 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
199 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
201 GCMP sz src1 src2 -> mkRUR [src1,src2]
202 GABS sz src dst -> mkRU [src] [dst]
203 GNEG sz src dst -> mkRU [src] [dst]
204 GSQRT sz src dst -> mkRU [src] [dst]
205 GSIN sz src dst -> mkRU [src] [dst]
206 GCOS sz src dst -> mkRU [src] [dst]
207 GTAN sz src dst -> mkRU [src] [dst]
210 #if x86_64_TARGET_ARCH
211 CVTSS2SD src dst -> mkRU [src] [dst]
212 CVTSD2SS src dst -> mkRU [src] [dst]
213 CVTSS2SI src dst -> mkRU (use_R src) [dst]
214 CVTSD2SI src dst -> mkRU (use_R src) [dst]
215 CVTSI2SS src dst -> mkRU (use_R src) [dst]
216 CVTSI2SD src dst -> mkRU (use_R src) [dst]
217 FDIV sz src dst -> usageRM src dst
220 FETCHGOT reg -> mkRU [] [reg]
221 FETCHPC reg -> mkRU [] [reg]
226 _other -> panic "regUsage: unrecognised instr"
229 -- 2 operand form; first operand Read; second Written
230 usageRW :: Operand -> Operand -> RegUsage
231 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
232 usageRW op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
234 -- 2 operand form; first operand Read; second Modified
235 usageRM :: Operand -> Operand -> RegUsage
236 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
237 usageRM op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
239 -- 1 operand form; operand Modified
240 usageM :: Operand -> RegUsage
241 usageM (OpReg reg) = mkRU [reg] [reg]
242 usageM (OpAddr ea) = mkRUR (use_EA ea)
244 -- Registers defd when an operand is written.
245 def_W (OpReg reg) = [reg]
246 def_W (OpAddr ea) = []
248 -- Registers used when an operand is read.
249 use_R (OpReg reg) = [reg]
250 use_R (OpImm imm) = []
251 use_R (OpAddr ea) = use_EA ea
253 -- Registers used to compute an effective address.
254 use_EA (ImmAddr _ _) = []
255 use_EA (AddrBaseIndex base index _) =
256 use_base base $! use_index index
257 where use_base (EABaseReg r) x = r : x
259 use_index EAIndexNone = []
260 use_index (EAIndex i _) = [i]
262 mkRUR src = src' `seq` RU src' []
263 where src' = filter interesting src
265 mkRU src dst = src' `seq` dst' `seq` RU src' dst'
266 where src' = filter interesting src
267 dst' = filter interesting dst
269 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
270 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
271 #if sparc_TARGET_ARCH
273 regUsage instr = case instr of
274 LD sz addr reg -> usage (regAddr addr, [reg])
275 ST sz reg addr -> usage (reg : regAddr addr, [])
276 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
277 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
278 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
279 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
280 RDY rd -> usage ([], [rd])
281 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
282 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
284 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
285 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
289 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
290 SETHI imm reg -> usage ([], [reg])
291 FABS s r1 r2 -> usage ([r1], [r2])
292 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
293 FCMP e s r1 r2 -> usage ([r1, r2], [])
294 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
295 FMOV s r1 r2 -> usage ([r1], [r2])
296 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
297 FNEG s r1 r2 -> usage ([r1], [r2])
298 FSQRT s r1 r2 -> usage ([r1], [r2])
299 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
300 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
302 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
303 JMP addr -> usage (regAddr addr, [])
305 CALL (Left imm) n True -> noUsage
306 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
307 CALL (Right reg) n True -> usage ([reg], [])
308 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
312 usage (src, dst) = RU (filter interesting src)
313 (filter interesting dst)
315 regAddr (AddrRegReg r1 r2) = [r1, r2]
316 regAddr (AddrRegImm r1 _) = [r1]
318 regRI (RIReg r) = [r]
321 #endif /* sparc_TARGET_ARCH */
322 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
323 #if powerpc_TARGET_ARCH
325 regUsage instr = case instr of
326 LD sz reg addr -> usage (regAddr addr, [reg])
327 LA sz reg addr -> usage (regAddr addr, [reg])
328 ST sz reg addr -> usage (reg : regAddr addr, [])
329 STU sz reg addr -> usage (reg : regAddr addr, [])
330 LIS reg imm -> usage ([], [reg])
331 LI reg imm -> usage ([], [reg])
332 MR reg1 reg2 -> usage ([reg2], [reg1])
333 CMP sz reg ri -> usage (reg : regRI ri,[])
334 CMPL sz reg ri -> usage (reg : regRI ri,[])
335 BCC cond lbl -> noUsage
336 MTCTR reg -> usage ([reg],[])
337 BCTR targets -> noUsage
338 BL imm params -> usage (params, callClobberedRegs)
339 BCTRL params -> usage (params, callClobberedRegs)
340 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
341 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
342 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
343 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
344 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
345 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
346 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
347 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
348 MULLW_MayOflo reg1 reg2 reg3
349 -> usage ([reg2,reg3], [reg1])
350 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
351 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
352 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
353 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
354 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
355 NEG reg1 reg2 -> usage ([reg2], [reg1])
356 NOT reg1 reg2 -> usage ([reg2], [reg1])
357 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
358 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
359 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
360 RLWINM reg1 reg2 sh mb me
361 -> usage ([reg2], [reg1])
362 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
363 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
364 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
365 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
366 FNEG r1 r2 -> usage ([r2], [r1])
367 FCMP r1 r2 -> usage ([r1,r2], [])
368 FCTIWZ r1 r2 -> usage ([r2], [r1])
369 FRSP r1 r2 -> usage ([r2], [r1])
370 MFCR reg -> usage ([], [reg])
371 MFLR reg -> usage ([], [reg])
372 FETCHPC reg -> usage ([], [reg])
375 usage (src, dst) = RU (filter interesting src)
376 (filter interesting dst)
377 regAddr (AddrRegReg r1 r2) = [r1, r2]
378 regAddr (AddrRegImm r1 _) = [r1]
380 regRI (RIReg r) = [r]
382 #endif /* powerpc_TARGET_ARCH */
385 -- -----------------------------------------------------------------------------
386 -- Determine the possible destinations from the current instruction.
388 -- (we always assume that the next instruction is also a valid destination;
389 -- if this isn't the case then the jump should be at the end of the basic
392 jumpDests :: Instr -> [BlockId] -> [BlockId]
395 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
397 JMP_TBL _ ids -> ids ++ acc
398 #elif powerpc_TARGET_ARCH
400 BCTR targets -> targets ++ acc
404 patchJump :: Instr -> BlockId -> BlockId -> Instr
406 patchJump insn old new
408 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
409 JXX cc id | id == old -> JXX cc new
410 JMP_TBL op ids -> error "Cannot patch JMP_TBL"
411 #elif powerpc_TARGET_ARCH
412 BCC cc id | id == old -> BCC cc new
413 BCTR targets -> error "Cannot patch BCTR"
417 -- -----------------------------------------------------------------------------
418 -- 'patchRegs' function
420 -- 'patchRegs' takes an instruction and applies the given mapping to
421 -- all the register references.
423 patchRegs :: Instr -> (Reg -> Reg) -> Instr
425 #if alpha_TARGET_ARCH
427 patchRegs instr env = case instr of
428 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
429 LDA reg addr -> LDA (env reg) (fixAddr addr)
430 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
431 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
432 LDI sz reg imm -> LDI sz (env reg) imm
433 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
434 CLR reg -> CLR (env reg)
435 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
436 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
437 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
438 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
439 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
440 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
441 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
442 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
443 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
444 NOT ar reg -> NOT (fixRI ar) (env reg)
445 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
446 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
447 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
448 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
449 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
450 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
451 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
452 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
453 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
454 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
455 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
456 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
457 FCLR reg -> FCLR (env reg)
458 FABS r1 r2 -> FABS (env r1) (env r2)
459 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
460 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
461 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
462 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
463 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
464 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
465 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
466 FMOV r1 r2 -> FMOV (env r1) (env r2)
467 BI cond reg lbl -> BI cond (env reg) lbl
468 BF cond reg lbl -> BF cond (env reg) lbl
469 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
470 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
473 fixAddr (AddrReg r1) = AddrReg (env r1)
474 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
475 fixAddr other = other
477 fixRI (RIReg r) = RIReg (env r)
480 #endif /* alpha_TARGET_ARCH */
481 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
482 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
484 patchRegs instr env = case instr of
485 MOV sz src dst -> patch2 (MOV sz) src dst
486 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
487 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
488 LEA sz src dst -> patch2 (LEA sz) src dst
489 ADD sz src dst -> patch2 (ADD sz) src dst
490 ADC sz src dst -> patch2 (ADC sz) src dst
491 SUB sz src dst -> patch2 (SUB sz) src dst
492 IMUL sz src dst -> patch2 (IMUL sz) src dst
493 IMUL2 sz src -> patch1 (IMUL2 sz) src
494 MUL sz src dst -> patch2 (MUL sz) src dst
495 IDIV sz op -> patch1 (IDIV sz) op
496 DIV sz op -> patch1 (DIV sz) op
497 AND sz src dst -> patch2 (AND sz) src dst
498 OR sz src dst -> patch2 (OR sz) src dst
499 XOR sz src dst -> patch2 (XOR sz) src dst
500 NOT sz op -> patch1 (NOT sz) op
501 NEGI sz op -> patch1 (NEGI sz) op
502 SHL sz imm dst -> patch1 (SHL sz imm) dst
503 SAR sz imm dst -> patch1 (SAR sz imm) dst
504 SHR sz imm dst -> patch1 (SHR sz imm) dst
505 BT sz imm src -> patch1 (BT sz imm) src
506 TEST sz src dst -> patch2 (TEST sz) src dst
507 CMP sz src dst -> patch2 (CMP sz) src dst
508 PUSH sz op -> patch1 (PUSH sz) op
509 POP sz op -> patch1 (POP sz) op
510 SETCC cond op -> patch1 (SETCC cond) op
511 JMP op -> patch1 JMP op
512 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
515 GMOV src dst -> GMOV (env src) (env dst)
516 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
517 GST sz src dst -> GST sz (env src) (lookupAddr dst)
519 GLDZ dst -> GLDZ (env dst)
520 GLD1 dst -> GLD1 (env dst)
522 GFTOI src dst -> GFTOI (env src) (env dst)
523 GDTOI src dst -> GDTOI (env src) (env dst)
525 GITOF src dst -> GITOF (env src) (env dst)
526 GITOD src dst -> GITOD (env src) (env dst)
528 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
529 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
530 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
531 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
533 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
534 GABS sz src dst -> GABS sz (env src) (env dst)
535 GNEG sz src dst -> GNEG sz (env src) (env dst)
536 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
537 GSIN sz src dst -> GSIN sz (env src) (env dst)
538 GCOS sz src dst -> GCOS sz (env src) (env dst)
539 GTAN sz src dst -> GTAN sz (env src) (env dst)
542 #if x86_64_TARGET_ARCH
543 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
544 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
545 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
546 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
547 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
548 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
549 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
552 CALL (Left imm) _ -> instr
553 CALL (Right reg) p -> CALL (Right (env reg)) p
555 FETCHGOT reg -> FETCHGOT (env reg)
556 FETCHPC reg -> FETCHPC (env reg)
564 _other -> panic "patchRegs: unrecognised instr"
567 patch1 insn op = insn $! patchOp op
568 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
570 patchOp (OpReg reg) = OpReg $! env reg
571 patchOp (OpImm imm) = OpImm imm
572 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
574 lookupAddr (ImmAddr imm off) = ImmAddr imm off
575 lookupAddr (AddrBaseIndex base index disp)
576 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
578 lookupBase EABaseNone = EABaseNone
579 lookupBase EABaseRip = EABaseRip
580 lookupBase (EABaseReg r) = EABaseReg (env r)
582 lookupIndex EAIndexNone = EAIndexNone
583 lookupIndex (EAIndex r i) = EAIndex (env r) i
585 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
586 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
587 #if sparc_TARGET_ARCH
589 patchRegs instr env = case instr of
590 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
591 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
592 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
593 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
594 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
595 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
596 RDY rd -> RDY (env rd)
597 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
598 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
599 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
600 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
601 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
602 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
603 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
604 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
605 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
606 SETHI imm reg -> SETHI imm (env reg)
607 FABS s r1 r2 -> FABS s (env r1) (env r2)
608 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
609 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
610 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
611 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
612 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
613 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
614 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
615 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
616 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
617 JMP addr -> JMP (fixAddr addr)
618 CALL (Left i) n t -> CALL (Left i) n t
619 CALL (Right r) n t -> CALL (Right (env r)) n t
622 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
623 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
625 fixRI (RIReg r) = RIReg (env r)
628 #endif /* sparc_TARGET_ARCH */
629 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
630 #if powerpc_TARGET_ARCH
632 patchRegs instr env = case instr of
633 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
634 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
635 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
636 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
637 LIS reg imm -> LIS (env reg) imm
638 LI reg imm -> LI (env reg) imm
639 MR reg1 reg2 -> MR (env reg1) (env reg2)
640 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
641 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
642 BCC cond lbl -> BCC cond lbl
643 MTCTR reg -> MTCTR (env reg)
644 BCTR targets -> BCTR targets
645 BL imm argRegs -> BL imm argRegs -- argument regs
646 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
647 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
648 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
649 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
650 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
651 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
652 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
653 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
654 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
655 MULLW_MayOflo reg1 reg2 reg3
656 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
657 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
658 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
659 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
660 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
661 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
662 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
663 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
664 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
665 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
666 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
667 RLWINM reg1 reg2 sh mb me
668 -> RLWINM (env reg1) (env reg2) sh mb me
669 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
670 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
671 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
672 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
673 FNEG r1 r2 -> FNEG (env r1) (env r2)
674 FCMP r1 r2 -> FCMP (env r1) (env r2)
675 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
676 FRSP r1 r2 -> FRSP (env r1) (env r2)
677 MFCR reg -> MFCR (env reg)
678 MFLR reg -> MFLR (env reg)
679 FETCHPC reg -> FETCHPC (env reg)
682 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
683 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
685 fixRI (RIReg r) = RIReg (env r)
687 #endif /* powerpc_TARGET_ARCH */
689 -- -----------------------------------------------------------------------------
690 -- Detecting reg->reg moves
692 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
693 -- by assigning the src and dest temporaries to the same real register.
695 isRegRegMove :: Instr -> Maybe (Reg,Reg)
696 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
698 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
699 #elif powerpc_TARGET_ARCH
700 isRegRegMove (MR dst src) = Just (src,dst)
702 #warning ToDo: isRegRegMove
704 isRegRegMove _ = Nothing
706 -- -----------------------------------------------------------------------------
707 -- Generating spill instructions
710 :: Reg -- register to spill (should be a real)
711 -> Int -- current stack delta
712 -> Int -- spill slot to use
714 mkSpillInstr reg delta slot
715 = ASSERT(isRealReg reg)
717 off = spillSlotToOffset slot
719 #ifdef alpha_TARGET_ARCH
720 {-Alpha: spill below the stack pointer (?)-}
721 ST sz dyn (spRel (- (off `div` 8)))
723 #ifdef i386_TARGET_ARCH
724 let off_w = (off-delta) `div` 4
725 in case regClass reg of
726 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
727 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
729 #ifdef x86_64_TARGET_ARCH
730 let off_w = (off-delta) `div` 8
731 in case regClass reg of
732 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
733 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
734 -- ToDo: will it work to always spill as a double?
735 -- does that cause a stall if the data was a float?
737 #ifdef sparc_TARGET_ARCH
738 {-SPARC: spill below frame pointer leaving 2 words/spill-}
739 let{off_w = 1 + (off `div` 4);
740 sz = case regClass reg of {
744 in ST sz reg (fpRel (- off_w))
746 #ifdef powerpc_TARGET_ARCH
747 let sz = case regClass reg of
750 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
755 :: Reg -- register to load (should be a real)
756 -> Int -- current stack delta
757 -> Int -- spill slot to use
759 mkLoadInstr reg delta slot
760 = ASSERT(isRealReg reg)
762 off = spillSlotToOffset slot
764 #if alpha_TARGET_ARCH
765 LD sz dyn (spRel (- (off `div` 8)))
768 let off_w = (off-delta) `div` 4
769 in case regClass reg of {
770 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
771 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
773 #if x86_64_TARGET_ARCH
774 let off_w = (off-delta) `div` 8
775 in case regClass reg of
776 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
777 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
779 #if sparc_TARGET_ARCH
780 let{off_w = 1 + (off `div` 4);
781 sz = case regClass reg of {
785 in LD sz (fpRel (- off_w)) reg
787 #if powerpc_TARGET_ARCH
788 let sz = case regClass reg of
791 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
798 mkRegRegMoveInstr src dst
799 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
800 = case regClass src of
801 RcInteger -> MOV wordRep (OpReg src) (OpReg dst)
803 RcDouble -> GMOV src dst
805 RcDouble -> MOV F64 (OpReg src) (OpReg dst)
807 #elif powerpc_TARGET_ARCH
814 #if alpha_TARGET_ARCH
815 mkBranchInstr id = [BR id]
818 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
819 mkBranchInstr id = [JXX ALWAYS id]
822 #if sparc_TARGET_ARCH
823 mkBranchInstr (BlockId id) = [BI ALWAYS False (ImmCLbl (mkAsmTempLabel id)), NOP]
826 #if powerpc_TARGET_ARCH
827 mkBranchInstr id = [BCC ALWAYS id]
832 spillSlotSize = IF_ARCH_i386(12, 8)
835 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
837 -- convert a spill slot number to a *byte* offset, with no sign:
838 -- decide on a per arch basis whether you are spilling above or below
839 -- the C stack pointer.
840 spillSlotToOffset :: Int -> Int
841 spillSlotToOffset slot
842 | slot >= 0 && slot < maxSpillSlots
843 = 64 + spillSlotSize * slot
845 = pprPanic "spillSlotToOffset:"
846 (text "invalid spill location: " <> int slot)