1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
27 #include "HsVersions.h"
29 import Cmm ( BlockId )
30 import MachOp ( MachRep(..), wordRep )
34 import Constants ( rESERVED_C_STACK_BYTES )
37 -- -----------------------------------------------------------------------------
40 -- @regUsage@ returns the sets of src and destination registers used
41 -- by a particular instruction. Machine registers that are
42 -- pre-allocated to stgRegs are filtered out, because they are
43 -- uninteresting from a register allocation standpoint. (We wouldn't
44 -- want them to end up on the free list!) As far as we are concerned,
45 -- the fixed registers simply don't exist (for allocation purposes,
48 -- regUsage doesn't need to do any trickery for jumps and such. Just
49 -- state precisely the regs read and written by that insn. The
50 -- consequences of control flow transfers, as far as register
51 -- allocation goes, are taken care of by the register allocator.
53 data RegUsage = RU [Reg] [Reg]
58 regUsage :: Instr -> RegUsage
60 interesting (VirtualRegI _) = True
61 interesting (VirtualRegHi _) = True
62 interesting (VirtualRegF _) = True
63 interesting (VirtualRegD _) = True
64 interesting (RealReg i) = isFastTrue (freeReg i)
68 regUsage instr = case instr of
69 LD B reg addr -> usage (regAddr addr, [reg, t9])
70 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
71 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
73 LD sz reg addr -> usage (regAddr addr, [reg])
74 LDA reg addr -> usage (regAddr addr, [reg])
75 LDAH reg addr -> usage (regAddr addr, [reg])
76 LDGP reg addr -> usage (regAddr addr, [reg])
77 LDI sz reg imm -> usage ([], [reg])
78 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
79 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
80 ST sz reg addr -> usage (reg : regAddr addr, [])
81 CLR reg -> usage ([], [reg])
82 ABS sz ri reg -> usage (regRI ri, [reg])
83 NEG sz ov ri reg -> usage (regRI ri, [reg])
84 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
89 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
91 NOT ri reg -> usage (regRI ri, [reg])
92 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
104 FCLR reg -> usage ([], [reg])
105 FABS r1 r2 -> usage ([r1], [r2])
106 FNEG sz r1 r2 -> usage ([r1], [r2])
107 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
111 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
112 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
113 FMOV r1 r2 -> usage ([r1], [r2])
116 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
117 BI cond reg lbl -> usage ([reg], [])
118 BF cond reg lbl -> usage ([reg], [])
119 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
121 BSR _ n -> RU (argRegSet n) callClobberedRegSet
122 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
127 usage (src, dst) = RU (mkRegSet (filter interesting src))
128 (mkRegSet (filter interesting dst))
130 interesting (FixedReg _) = False
133 regAddr (AddrReg r1) = [r1]
134 regAddr (AddrRegImm r1 _) = [r1]
135 regAddr (AddrImm _) = []
137 regRI (RIReg r) = [r]
140 #endif /* alpha_TARGET_ARCH */
141 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
142 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
144 regUsage instr = case instr of
145 MOV sz src dst -> usageRW src dst
146 MOVZxL sz src dst -> usageRW src dst
147 MOVSxL sz src dst -> usageRW src dst
148 LEA sz src dst -> usageRW src dst
149 ADD sz src dst -> usageRM src dst
150 ADC sz src dst -> usageRM src dst
151 SUB sz src dst -> usageRM src dst
152 IMUL sz src dst -> usageRM src dst
153 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
154 MUL sz src dst -> usageRM src dst
155 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
157 AND sz src dst -> usageRM src dst
158 OR sz src dst -> usageRM src dst
159 XOR sz src dst -> usageRM src dst
160 NOT sz op -> usageM op
161 NEGI sz op -> usageM op
162 SHL sz imm dst -> usageRM imm dst
163 SAR sz imm dst -> usageRM imm dst
164 SHR sz imm dst -> usageRM imm dst
165 BT sz imm src -> mkRUR (use_R src)
167 PUSH sz op -> mkRUR (use_R op)
168 POP sz op -> mkRU [] (def_W op)
169 TEST sz src dst -> mkRUR (use_R src ++ use_R dst)
170 CMP sz src dst -> mkRUR (use_R src ++ use_R dst)
171 SETCC cond op -> mkRU [] (def_W op)
172 JXX cond lbl -> mkRU [] []
173 JMP op -> mkRUR (use_R op)
174 JMP_TBL op ids -> mkRUR (use_R op)
175 CALL (Left imm) params -> mkRU params callClobberedRegs
176 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
177 CLTD sz -> mkRU [eax] [edx]
181 GMOV src dst -> mkRU [src] [dst]
182 GLD sz src dst -> mkRU (use_EA src) [dst]
183 GST sz src dst -> mkRUR (src : use_EA dst)
185 GLDZ dst -> mkRU [] [dst]
186 GLD1 dst -> mkRU [] [dst]
188 GFTOI src dst -> mkRU [src] [dst]
189 GDTOI src dst -> mkRU [src] [dst]
191 GITOF src dst -> mkRU [src] [dst]
192 GITOD src dst -> mkRU [src] [dst]
194 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
195 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
196 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
197 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
199 GCMP sz src1 src2 -> mkRUR [src1,src2]
200 GABS sz src dst -> mkRU [src] [dst]
201 GNEG sz src dst -> mkRU [src] [dst]
202 GSQRT sz src dst -> mkRU [src] [dst]
203 GSIN sz src dst -> mkRU [src] [dst]
204 GCOS sz src dst -> mkRU [src] [dst]
205 GTAN sz src dst -> mkRU [src] [dst]
208 #if x86_64_TARGET_ARCH
209 CVTSS2SD src dst -> mkRU [src] [dst]
210 CVTSD2SS src dst -> mkRU [src] [dst]
211 CVTSS2SI src dst -> mkRU (use_R src) [dst]
212 CVTSD2SI src dst -> mkRU (use_R src) [dst]
213 CVTSI2SS src dst -> mkRU (use_R src) [dst]
214 CVTSI2SD src dst -> mkRU (use_R src) [dst]
215 FDIV sz src dst -> usageRM src dst
218 FETCHGOT reg -> mkRU [] [reg]
219 FETCHPC reg -> mkRU [] [reg]
224 _other -> panic "regUsage: unrecognised instr"
227 -- 2 operand form; first operand Read; second Written
228 usageRW :: Operand -> Operand -> RegUsage
229 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
230 usageRW op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
232 -- 2 operand form; first operand Read; second Modified
233 usageRM :: Operand -> Operand -> RegUsage
234 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
235 usageRM op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
237 -- 1 operand form; operand Modified
238 usageM :: Operand -> RegUsage
239 usageM (OpReg reg) = mkRU [reg] [reg]
240 usageM (OpAddr ea) = mkRUR (use_EA ea)
242 -- Registers defd when an operand is written.
243 def_W (OpReg reg) = [reg]
244 def_W (OpAddr ea) = []
246 -- Registers used when an operand is read.
247 use_R (OpReg reg) = [reg]
248 use_R (OpImm imm) = []
249 use_R (OpAddr ea) = use_EA ea
251 -- Registers used to compute an effective address.
252 use_EA (ImmAddr _ _) = []
253 use_EA (AddrBaseIndex base index _) =
254 use_base base $! use_index index
255 where use_base (EABaseReg r) x = r : x
257 use_index EAIndexNone = []
258 use_index (EAIndex i _) = [i]
260 mkRUR src = src' `seq` RU src' []
261 where src' = filter interesting src
263 mkRU src dst = src' `seq` dst' `seq` RU src' dst'
264 where src' = filter interesting src
265 dst' = filter interesting dst
267 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
268 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
269 #if sparc_TARGET_ARCH
271 regUsage instr = case instr of
272 LD sz addr reg -> usage (regAddr addr, [reg])
273 ST sz reg addr -> usage (reg : regAddr addr, [])
274 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
275 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
276 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
277 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
278 RDY rd -> usage ([], [rd])
279 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
280 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
281 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
282 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
284 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
285 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 SETHI imm reg -> usage ([], [reg])
289 FABS s r1 r2 -> usage ([r1], [r2])
290 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
291 FCMP e s r1 r2 -> usage ([r1, r2], [])
292 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
293 FMOV s r1 r2 -> usage ([r1], [r2])
294 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
295 FNEG s r1 r2 -> usage ([r1], [r2])
296 FSQRT s r1 r2 -> usage ([r1], [r2])
297 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
298 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
300 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
301 JMP addr -> usage (regAddr addr, [])
303 CALL (Left imm) n True -> noUsage
304 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
305 CALL (Right reg) n True -> usage ([reg], [])
306 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
310 usage (src, dst) = RU (filter interesting src)
311 (filter interesting dst)
313 regAddr (AddrRegReg r1 r2) = [r1, r2]
314 regAddr (AddrRegImm r1 _) = [r1]
316 regRI (RIReg r) = [r]
319 #endif /* sparc_TARGET_ARCH */
320 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
321 #if powerpc_TARGET_ARCH
323 regUsage instr = case instr of
324 LD sz reg addr -> usage (regAddr addr, [reg])
325 LA sz reg addr -> usage (regAddr addr, [reg])
326 ST sz reg addr -> usage (reg : regAddr addr, [])
327 STU sz reg addr -> usage (reg : regAddr addr, [])
328 LIS reg imm -> usage ([], [reg])
329 LI reg imm -> usage ([], [reg])
330 MR reg1 reg2 -> usage ([reg2], [reg1])
331 CMP sz reg ri -> usage (reg : regRI ri,[])
332 CMPL sz reg ri -> usage (reg : regRI ri,[])
333 BCC cond lbl -> noUsage
334 MTCTR reg -> usage ([reg],[])
335 BCTR targets -> noUsage
336 BL imm params -> usage (params, callClobberedRegs)
337 BCTRL params -> usage (params, callClobberedRegs)
338 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
339 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
340 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
341 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
342 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
343 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
344 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
345 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
346 MULLW_MayOflo reg1 reg2 reg3
347 -> usage ([reg2,reg3], [reg1])
348 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
349 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
350 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
351 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
352 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
353 NEG reg1 reg2 -> usage ([reg2], [reg1])
354 NOT reg1 reg2 -> usage ([reg2], [reg1])
355 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
356 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
357 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
358 RLWINM reg1 reg2 sh mb me
359 -> usage ([reg2], [reg1])
360 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
361 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
362 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
363 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
364 FNEG r1 r2 -> usage ([r2], [r1])
365 FCMP r1 r2 -> usage ([r1,r2], [])
366 FCTIWZ r1 r2 -> usage ([r2], [r1])
367 FRSP r1 r2 -> usage ([r2], [r1])
368 MFCR reg -> usage ([], [reg])
369 MFLR reg -> usage ([], [reg])
370 FETCHPC reg -> usage ([], [reg])
373 usage (src, dst) = RU (filter interesting src)
374 (filter interesting dst)
375 regAddr (AddrRegReg r1 r2) = [r1, r2]
376 regAddr (AddrRegImm r1 _) = [r1]
378 regRI (RIReg r) = [r]
380 #endif /* powerpc_TARGET_ARCH */
383 -- -----------------------------------------------------------------------------
384 -- Determine the possible destinations from the current instruction.
386 -- (we always assume that the next instruction is also a valid destination;
387 -- if this isn't the case then the jump should be at the end of the basic
390 jumpDests :: Instr -> [BlockId] -> [BlockId]
393 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
395 JMP_TBL _ ids -> ids ++ acc
396 #elif powerpc_TARGET_ARCH
398 BCTR targets -> targets ++ acc
402 patchJump :: Instr -> BlockId -> BlockId -> Instr
404 patchJump insn old new
406 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
407 JXX cc id | id == old -> JXX cc new
408 JMP_TBL op ids -> error "Cannot patch JMP_TBL"
409 #elif powerpc_TARGET_ARCH
410 BCC cc id | id == old -> BCC cc new
411 BCTR targets -> error "Cannot patch BCTR"
415 -- -----------------------------------------------------------------------------
416 -- 'patchRegs' function
418 -- 'patchRegs' takes an instruction and applies the given mapping to
419 -- all the register references.
421 patchRegs :: Instr -> (Reg -> Reg) -> Instr
423 #if alpha_TARGET_ARCH
425 patchRegs instr env = case instr of
426 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
427 LDA reg addr -> LDA (env reg) (fixAddr addr)
428 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
429 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
430 LDI sz reg imm -> LDI sz (env reg) imm
431 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
432 CLR reg -> CLR (env reg)
433 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
434 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
435 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
436 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
437 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
438 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
439 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
440 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
441 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
442 NOT ar reg -> NOT (fixRI ar) (env reg)
443 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
444 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
445 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
446 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
447 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
448 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
449 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
450 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
451 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
452 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
453 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
454 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
455 FCLR reg -> FCLR (env reg)
456 FABS r1 r2 -> FABS (env r1) (env r2)
457 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
458 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
459 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
460 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
461 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
462 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
463 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
464 FMOV r1 r2 -> FMOV (env r1) (env r2)
465 BI cond reg lbl -> BI cond (env reg) lbl
466 BF cond reg lbl -> BF cond (env reg) lbl
467 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
468 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
471 fixAddr (AddrReg r1) = AddrReg (env r1)
472 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
473 fixAddr other = other
475 fixRI (RIReg r) = RIReg (env r)
478 #endif /* alpha_TARGET_ARCH */
479 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
480 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
482 patchRegs instr env = case instr of
483 MOV sz src dst -> patch2 (MOV sz) src dst
484 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
485 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
486 LEA sz src dst -> patch2 (LEA sz) src dst
487 ADD sz src dst -> patch2 (ADD sz) src dst
488 ADC sz src dst -> patch2 (ADC sz) src dst
489 SUB sz src dst -> patch2 (SUB sz) src dst
490 IMUL sz src dst -> patch2 (IMUL sz) src dst
491 IMUL2 sz src -> patch1 (IMUL2 sz) src
492 MUL sz src dst -> patch2 (MUL sz) src dst
493 IDIV sz op -> patch1 (IDIV sz) op
494 DIV sz op -> patch1 (DIV sz) op
495 AND sz src dst -> patch2 (AND sz) src dst
496 OR sz src dst -> patch2 (OR sz) src dst
497 XOR sz src dst -> patch2 (XOR sz) src dst
498 NOT sz op -> patch1 (NOT sz) op
499 NEGI sz op -> patch1 (NEGI sz) op
500 SHL sz imm dst -> patch1 (SHL sz imm) dst
501 SAR sz imm dst -> patch1 (SAR sz imm) dst
502 SHR sz imm dst -> patch1 (SHR sz imm) dst
503 BT sz imm src -> patch1 (BT sz imm) src
504 TEST sz src dst -> patch2 (TEST sz) src dst
505 CMP sz src dst -> patch2 (CMP sz) src dst
506 PUSH sz op -> patch1 (PUSH sz) op
507 POP sz op -> patch1 (POP sz) op
508 SETCC cond op -> patch1 (SETCC cond) op
509 JMP op -> patch1 JMP op
510 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
513 GMOV src dst -> GMOV (env src) (env dst)
514 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
515 GST sz src dst -> GST sz (env src) (lookupAddr dst)
517 GLDZ dst -> GLDZ (env dst)
518 GLD1 dst -> GLD1 (env dst)
520 GFTOI src dst -> GFTOI (env src) (env dst)
521 GDTOI src dst -> GDTOI (env src) (env dst)
523 GITOF src dst -> GITOF (env src) (env dst)
524 GITOD src dst -> GITOD (env src) (env dst)
526 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
527 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
528 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
529 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
531 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
532 GABS sz src dst -> GABS sz (env src) (env dst)
533 GNEG sz src dst -> GNEG sz (env src) (env dst)
534 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
535 GSIN sz src dst -> GSIN sz (env src) (env dst)
536 GCOS sz src dst -> GCOS sz (env src) (env dst)
537 GTAN sz src dst -> GTAN sz (env src) (env dst)
540 #if x86_64_TARGET_ARCH
541 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
542 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
543 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
544 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
545 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
546 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
547 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
550 CALL (Left imm) _ -> instr
551 CALL (Right reg) p -> CALL (Right (env reg)) p
553 FETCHGOT reg -> FETCHGOT (env reg)
554 FETCHPC reg -> FETCHPC (env reg)
562 _other -> panic "patchRegs: unrecognised instr"
565 patch1 insn op = insn $! patchOp op
566 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
568 patchOp (OpReg reg) = OpReg $! env reg
569 patchOp (OpImm imm) = OpImm imm
570 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
572 lookupAddr (ImmAddr imm off) = ImmAddr imm off
573 lookupAddr (AddrBaseIndex base index disp)
574 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
576 lookupBase EABaseNone = EABaseNone
577 lookupBase EABaseRip = EABaseRip
578 lookupBase (EABaseReg r) = EABaseReg (env r)
580 lookupIndex EAIndexNone = EAIndexNone
581 lookupIndex (EAIndex r i) = EAIndex (env r) i
583 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
584 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
585 #if sparc_TARGET_ARCH
587 patchRegs instr env = case instr of
588 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
589 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
590 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
591 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
592 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
593 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
594 RDY rd -> RDY (env rd)
595 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
596 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
597 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
598 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
599 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
600 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
601 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
602 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
603 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
604 SETHI imm reg -> SETHI imm (env reg)
605 FABS s r1 r2 -> FABS s (env r1) (env r2)
606 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
607 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
608 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
609 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
610 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
611 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
612 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
613 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
614 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
615 JMP addr -> JMP (fixAddr addr)
616 CALL (Left i) n t -> CALL (Left i) n t
617 CALL (Right r) n t -> CALL (Right (env r)) n t
620 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
621 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
623 fixRI (RIReg r) = RIReg (env r)
626 #endif /* sparc_TARGET_ARCH */
627 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
628 #if powerpc_TARGET_ARCH
630 patchRegs instr env = case instr of
631 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
632 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
633 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
634 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
635 LIS reg imm -> LIS (env reg) imm
636 LI reg imm -> LI (env reg) imm
637 MR reg1 reg2 -> MR (env reg1) (env reg2)
638 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
639 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
640 BCC cond lbl -> BCC cond lbl
641 MTCTR reg -> MTCTR (env reg)
642 BCTR targets -> BCTR targets
643 BL imm argRegs -> BL imm argRegs -- argument regs
644 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
645 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
646 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
647 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
648 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
649 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
650 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
651 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
652 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
653 MULLW_MayOflo reg1 reg2 reg3
654 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
655 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
656 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
657 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
658 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
659 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
660 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
661 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
662 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
663 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
664 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
665 RLWINM reg1 reg2 sh mb me
666 -> RLWINM (env reg1) (env reg2) sh mb me
667 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
668 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
669 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
670 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
671 FNEG r1 r2 -> FNEG (env r1) (env r2)
672 FCMP r1 r2 -> FCMP (env r1) (env r2)
673 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
674 FRSP r1 r2 -> FRSP (env r1) (env r2)
675 MFCR reg -> MFCR (env reg)
676 MFLR reg -> MFLR (env reg)
677 FETCHPC reg -> FETCHPC (env reg)
680 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
681 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
683 fixRI (RIReg r) = RIReg (env r)
685 #endif /* powerpc_TARGET_ARCH */
687 -- -----------------------------------------------------------------------------
688 -- Detecting reg->reg moves
690 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
691 -- by assigning the src and dest temporaries to the same real register.
693 isRegRegMove :: Instr -> Maybe (Reg,Reg)
694 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
696 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
697 #elif powerpc_TARGET_ARCH
698 isRegRegMove (MR dst src) = Just (src,dst)
700 #warning ToDo: isRegRegMove
702 isRegRegMove _ = Nothing
704 -- -----------------------------------------------------------------------------
705 -- Generating spill instructions
708 :: Reg -- register to spill (should be a real)
709 -> Int -- current stack delta
710 -> Int -- spill slot to use
712 mkSpillInstr reg delta slot
713 = ASSERT(isRealReg reg)
715 off = spillSlotToOffset slot
717 #ifdef alpha_TARGET_ARCH
718 {-Alpha: spill below the stack pointer (?)-}
719 ST sz dyn (spRel (- (off `div` 8)))
721 #ifdef i386_TARGET_ARCH
722 let off_w = (off-delta) `div` 4
723 in case regClass reg of
724 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
725 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
727 #ifdef x86_64_TARGET_ARCH
728 let off_w = (off-delta) `div` 8
729 in case regClass reg of
730 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
731 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
732 -- ToDo: will it work to always spill as a double?
733 -- does that cause a stall if the data was a float?
735 #ifdef sparc_TARGET_ARCH
736 {-SPARC: spill below frame pointer leaving 2 words/spill-}
737 let{off_w = 1 + (off `div` 4);
738 sz = case regClass reg of {
742 in ST sz reg (fpRel (- off_w))
744 #ifdef powerpc_TARGET_ARCH
745 let sz = case regClass reg of
748 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
753 :: Reg -- register to load (should be a real)
754 -> Int -- current stack delta
755 -> Int -- spill slot to use
757 mkLoadInstr reg delta slot
758 = ASSERT(isRealReg reg)
760 off = spillSlotToOffset slot
762 #if alpha_TARGET_ARCH
763 LD sz dyn (spRel (- (off `div` 8)))
766 let off_w = (off-delta) `div` 4
767 in case regClass reg of {
768 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
769 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
771 #if x86_64_TARGET_ARCH
772 let off_w = (off-delta) `div` 8
773 in case regClass reg of
774 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
775 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
777 #if sparc_TARGET_ARCH
778 let{off_w = 1 + (off `div` 4);
779 sz = case regClass reg of {
783 in LD sz (fpRel (- off_w)) reg
785 #if powerpc_TARGET_ARCH
786 let sz = case regClass reg of
789 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
796 mkRegRegMoveInstr src dst
797 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
798 = case regClass src of
799 RcInteger -> MOV wordRep (OpReg src) (OpReg dst)
801 RcDouble -> GMOV src dst
803 RcDouble -> MOV F64 (OpReg src) (OpReg dst)
805 #elif powerpc_TARGET_ARCH
812 #if alpha_TARGET_ARCH
813 mkBranchInstr id = [BR id]
816 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
817 mkBranchInstr id = [JXX ALWAYS id]
820 #if sparc_TARGET_ARCH
821 mkBranchInstr (BlockId id) = [BI ALWAYS False (ImmCLbl (mkAsmTempLabel id)), NOP]
824 #if powerpc_TARGET_ARCH
825 mkBranchInstr id = [BCC ALWAYS id]
830 spillSlotSize = IF_ARCH_i386(12, 8)
833 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
835 -- convert a spill slot number to a *byte* offset, with no sign:
836 -- decide on a per arch basis whether you are spilling above or below
837 -- the C stack pointer.
838 spillSlotToOffset :: Int -> Int
839 spillSlotToOffset slot
840 | slot >= 0 && slot < maxSpillSlots
841 = 64 + spillSlotSize * slot
843 = pprPanic "spillSlotToOffset:"
844 (text "invalid spill location: " <> int slot)