1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
20 JumpDest, canShortcut, shortcutJump, shortcutStatic,
29 #include "HsVersions.h"
33 import MachOp ( MachRep(..), wordRep )
37 import Constants ( rESERVED_C_STACK_BYTES )
40 -- -----------------------------------------------------------------------------
43 -- @regUsage@ returns the sets of src and destination registers used
44 -- by a particular instruction. Machine registers that are
45 -- pre-allocated to stgRegs are filtered out, because they are
46 -- uninteresting from a register allocation standpoint. (We wouldn't
47 -- want them to end up on the free list!) As far as we are concerned,
48 -- the fixed registers simply don't exist (for allocation purposes,
51 -- regUsage doesn't need to do any trickery for jumps and such. Just
52 -- state precisely the regs read and written by that insn. The
53 -- consequences of control flow transfers, as far as register
54 -- allocation goes, are taken care of by the register allocator.
56 data RegUsage = RU [Reg] [Reg]
61 regUsage :: Instr -> RegUsage
63 interesting (VirtualRegI _) = True
64 interesting (VirtualRegHi _) = True
65 interesting (VirtualRegF _) = True
66 interesting (VirtualRegD _) = True
67 interesting (RealReg i) = isFastTrue (freeReg i)
71 regUsage instr = case instr of
72 SPILL reg slot -> usage ([reg], [])
73 RELOAD slot reg -> usage ([], [reg])
74 LD B reg addr -> usage (regAddr addr, [reg, t9])
75 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
76 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
77 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
78 LD sz reg addr -> usage (regAddr addr, [reg])
79 LDA reg addr -> usage (regAddr addr, [reg])
80 LDAH reg addr -> usage (regAddr addr, [reg])
81 LDGP reg addr -> usage (regAddr addr, [reg])
82 LDI sz reg imm -> usage ([], [reg])
83 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
84 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
85 ST sz reg addr -> usage (reg : regAddr addr, [])
86 CLR reg -> usage ([], [reg])
87 ABS sz ri reg -> usage (regRI ri, [reg])
88 NEG sz ov ri reg -> usage (regRI ri, [reg])
89 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
90 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
91 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
95 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
96 NOT ri reg -> usage (regRI ri, [reg])
97 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
104 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
105 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
106 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
107 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
108 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
109 FCLR reg -> usage ([], [reg])
110 FABS r1 r2 -> usage ([r1], [r2])
111 FNEG sz r1 r2 -> usage ([r1], [r2])
112 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
113 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
114 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
115 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
116 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
117 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
118 FMOV r1 r2 -> usage ([r1], [r2])
121 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
122 BI cond reg lbl -> usage ([reg], [])
123 BF cond reg lbl -> usage ([reg], [])
124 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
126 BSR _ n -> RU (argRegSet n) callClobberedRegSet
127 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
132 usage (src, dst) = RU (mkRegSet (filter interesting src))
133 (mkRegSet (filter interesting dst))
135 interesting (FixedReg _) = False
138 regAddr (AddrReg r1) = [r1]
139 regAddr (AddrRegImm r1 _) = [r1]
140 regAddr (AddrImm _) = []
142 regRI (RIReg r) = [r]
145 #endif /* alpha_TARGET_ARCH */
146 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
147 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
149 regUsage instr = case instr of
150 MOV sz src dst -> usageRW src dst
151 MOVZxL sz src dst -> usageRW src dst
152 MOVSxL sz src dst -> usageRW src dst
153 LEA sz src dst -> usageRW src dst
154 ADD sz src dst -> usageRM src dst
155 ADC sz src dst -> usageRM src dst
156 SUB sz src dst -> usageRM src dst
157 IMUL sz src dst -> usageRM src dst
158 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
159 MUL sz src dst -> usageRM src dst
160 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
161 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
162 AND sz src dst -> usageRM src dst
163 OR sz src dst -> usageRM src dst
164 XOR sz (OpReg src) (OpReg dst)
165 | src == dst -> mkRU [] [dst]
166 XOR sz src dst -> usageRM src dst
167 NOT sz op -> usageM op
168 NEGI sz op -> usageM op
169 SHL sz imm dst -> usageRM imm dst
170 SAR sz imm dst -> usageRM imm dst
171 SHR sz imm dst -> usageRM imm dst
172 BT sz imm src -> mkRUR (use_R src)
174 PUSH sz op -> mkRUR (use_R op)
175 POP sz op -> mkRU [] (def_W op)
176 TEST sz src dst -> mkRUR (use_R src ++ use_R dst)
177 CMP sz src dst -> mkRUR (use_R src ++ use_R dst)
178 SETCC cond op -> mkRU [] (def_W op)
179 JXX cond lbl -> mkRU [] []
180 JXX_GBL cond lbl -> mkRU [] []
181 JMP op -> mkRUR (use_R op)
182 JMP_TBL op ids -> mkRUR (use_R op)
183 CALL (Left imm) params -> mkRU params callClobberedRegs
184 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
185 CLTD sz -> mkRU [eax] [edx]
189 GMOV src dst -> mkRU [src] [dst]
190 GLD sz src dst -> mkRU (use_EA src) [dst]
191 GST sz src dst -> mkRUR (src : use_EA dst)
193 GLDZ dst -> mkRU [] [dst]
194 GLD1 dst -> mkRU [] [dst]
196 GFTOI src dst -> mkRU [src] [dst]
197 GDTOI src dst -> mkRU [src] [dst]
199 GITOF src dst -> mkRU [src] [dst]
200 GITOD src dst -> mkRU [src] [dst]
202 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
203 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
204 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
205 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
207 GCMP sz src1 src2 -> mkRUR [src1,src2]
208 GABS sz src dst -> mkRU [src] [dst]
209 GNEG sz src dst -> mkRU [src] [dst]
210 GSQRT sz src dst -> mkRU [src] [dst]
211 GSIN sz src dst -> mkRU [src] [dst]
212 GCOS sz src dst -> mkRU [src] [dst]
213 GTAN sz src dst -> mkRU [src] [dst]
216 #if x86_64_TARGET_ARCH
217 CVTSS2SD src dst -> mkRU [src] [dst]
218 CVTSD2SS src dst -> mkRU [src] [dst]
219 CVTTSS2SIQ src dst -> mkRU (use_R src) [dst]
220 CVTTSD2SIQ src dst -> mkRU (use_R src) [dst]
221 CVTSI2SS src dst -> mkRU (use_R src) [dst]
222 CVTSI2SD src dst -> mkRU (use_R src) [dst]
223 FDIV sz src dst -> usageRM src dst
226 FETCHGOT reg -> mkRU [] [reg]
227 FETCHPC reg -> mkRU [] [reg]
231 SPILL reg slot -> mkRU [reg] []
232 RELOAD slot reg -> mkRU [] [reg]
234 _other -> panic "regUsage: unrecognised instr"
237 -- 2 operand form; first operand Read; second Written
238 usageRW :: Operand -> Operand -> RegUsage
239 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
240 usageRW op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
242 -- 2 operand form; first operand Read; second Modified
243 usageRM :: Operand -> Operand -> RegUsage
244 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
245 usageRM op (OpAddr ea) = mkRUR (use_R op ++ use_EA ea)
247 -- 1 operand form; operand Modified
248 usageM :: Operand -> RegUsage
249 usageM (OpReg reg) = mkRU [reg] [reg]
250 usageM (OpAddr ea) = mkRUR (use_EA ea)
252 -- Registers defd when an operand is written.
253 def_W (OpReg reg) = [reg]
254 def_W (OpAddr ea) = []
256 -- Registers used when an operand is read.
257 use_R (OpReg reg) = [reg]
258 use_R (OpImm imm) = []
259 use_R (OpAddr ea) = use_EA ea
261 -- Registers used to compute an effective address.
262 use_EA (ImmAddr _ _) = []
263 use_EA (AddrBaseIndex base index _) =
264 use_base base $! use_index index
265 where use_base (EABaseReg r) x = r : x
267 use_index EAIndexNone = []
268 use_index (EAIndex i _) = [i]
270 mkRUR src = src' `seq` RU src' []
271 where src' = filter interesting src
273 mkRU src dst = src' `seq` dst' `seq` RU src' dst'
274 where src' = filter interesting src
275 dst' = filter interesting dst
277 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
278 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
279 #if sparc_TARGET_ARCH
281 regUsage instr = case instr of
282 SPILL reg slot -> usage ([reg], [])
283 RELOAD slot reg -> usage ([], [reg])
285 LD sz addr reg -> usage (regAddr addr, [reg])
286 ST sz reg addr -> usage (reg : regAddr addr, [])
287 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
289 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
290 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
291 RDY rd -> usage ([], [rd])
292 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
293 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
294 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
295 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
296 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
297 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
298 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
299 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
300 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
301 SETHI imm reg -> usage ([], [reg])
302 FABS s r1 r2 -> usage ([r1], [r2])
303 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
304 FCMP e s r1 r2 -> usage ([r1, r2], [])
305 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
306 FMOV s r1 r2 -> usage ([r1], [r2])
307 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
308 FNEG s r1 r2 -> usage ([r1], [r2])
309 FSQRT s r1 r2 -> usage ([r1], [r2])
310 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
311 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
313 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
314 JMP addr -> usage (regAddr addr, [])
316 CALL (Left imm) n True -> noUsage
317 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
318 CALL (Right reg) n True -> usage ([reg], [])
319 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
323 usage (src, dst) = RU (filter interesting src)
324 (filter interesting dst)
326 regAddr (AddrRegReg r1 r2) = [r1, r2]
327 regAddr (AddrRegImm r1 _) = [r1]
329 regRI (RIReg r) = [r]
332 #endif /* sparc_TARGET_ARCH */
333 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
334 #if powerpc_TARGET_ARCH
336 regUsage instr = case instr of
337 SPILL reg slot -> usage ([reg], [])
338 RELOAD slot reg -> usage ([], [reg])
340 LD sz reg addr -> usage (regAddr addr, [reg])
341 LA sz reg addr -> usage (regAddr addr, [reg])
342 ST sz reg addr -> usage (reg : regAddr addr, [])
343 STU sz reg addr -> usage (reg : regAddr addr, [])
344 LIS reg imm -> usage ([], [reg])
345 LI reg imm -> usage ([], [reg])
346 MR reg1 reg2 -> usage ([reg2], [reg1])
347 CMP sz reg ri -> usage (reg : regRI ri,[])
348 CMPL sz reg ri -> usage (reg : regRI ri,[])
349 BCC cond lbl -> noUsage
350 BCCFAR cond lbl -> noUsage
351 MTCTR reg -> usage ([reg],[])
352 BCTR targets -> noUsage
353 BL imm params -> usage (params, callClobberedRegs)
354 BCTRL params -> usage (params, callClobberedRegs)
355 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
356 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
357 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
358 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
359 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
360 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
361 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
362 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
363 MULLW_MayOflo reg1 reg2 reg3
364 -> usage ([reg2,reg3], [reg1])
365 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
366 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
367 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
368 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
369 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
370 NEG reg1 reg2 -> usage ([reg2], [reg1])
371 NOT reg1 reg2 -> usage ([reg2], [reg1])
372 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
373 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
374 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
375 RLWINM reg1 reg2 sh mb me
376 -> usage ([reg2], [reg1])
377 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
378 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
379 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
380 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
381 FNEG r1 r2 -> usage ([r2], [r1])
382 FCMP r1 r2 -> usage ([r1,r2], [])
383 FCTIWZ r1 r2 -> usage ([r2], [r1])
384 FRSP r1 r2 -> usage ([r2], [r1])
385 MFCR reg -> usage ([], [reg])
386 MFLR reg -> usage ([], [reg])
387 FETCHPC reg -> usage ([], [reg])
390 usage (src, dst) = RU (filter interesting src)
391 (filter interesting dst)
392 regAddr (AddrRegReg r1 r2) = [r1, r2]
393 regAddr (AddrRegImm r1 _) = [r1]
395 regRI (RIReg r) = [r]
397 #endif /* powerpc_TARGET_ARCH */
400 -- -----------------------------------------------------------------------------
401 -- Determine the possible destinations from the current instruction.
403 -- (we always assume that the next instruction is also a valid destination;
404 -- if this isn't the case then the jump should be at the end of the basic
407 jumpDests :: Instr -> [BlockId] -> [BlockId]
410 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
412 JMP_TBL _ ids -> ids ++ acc
413 #elif powerpc_TARGET_ARCH
415 BCCFAR _ id -> id : acc
416 BCTR targets -> targets ++ acc
420 patchJump :: Instr -> BlockId -> BlockId -> Instr
422 patchJump insn old new
424 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
425 JXX cc id | id == old -> JXX cc new
426 JMP_TBL op ids -> error "Cannot patch JMP_TBL"
427 #elif powerpc_TARGET_ARCH
428 BCC cc id | id == old -> BCC cc new
429 BCCFAR cc id | id == old -> BCCFAR cc new
430 BCTR targets -> error "Cannot patch BCTR"
434 data JumpDest = DestBlockId BlockId | DestImm Imm
436 canShortcut :: Instr -> Maybe JumpDest
437 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
438 canShortcut (JXX ALWAYS id) = Just (DestBlockId id)
439 canShortcut (JMP (OpImm imm)) = Just (DestImm imm)
441 canShortcut _ = Nothing
443 shortcutJump :: (BlockId -> Maybe JumpDest) -> Instr -> Instr
444 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
445 shortcutJump fn insn@(JXX cc id) =
448 Just (DestBlockId id') -> shortcutJump fn (JXX cc id')
449 Just (DestImm imm) -> shortcutJump fn (JXX_GBL cc imm)
451 shortcutJump fn other = other
453 -- Here because it knows about JumpDest
454 shortcutStatic :: (BlockId -> Maybe JumpDest) -> CmmStatic -> CmmStatic
455 shortcutStatic fn (CmmStaticLit (CmmLabel lab))
456 | Just uq <- maybeAsmTemp lab
457 = CmmStaticLit (CmmLabel (shortBlockId fn (BlockId uq)))
458 shortcutStatic fn (CmmStaticLit (CmmLabelDiffOff lbl1 lbl2 off))
459 | Just uq <- maybeAsmTemp lbl1
460 = CmmStaticLit (CmmLabelDiffOff (shortBlockId fn (BlockId uq)) lbl2 off)
461 -- slightly dodgy, we're ignoring the second label, but this
462 -- works with the way we use CmmLabelDiffOff for jump tables now.
463 shortcutStatic fn other_static
466 shortBlockId fn blockid@(BlockId uq) =
468 Nothing -> mkAsmTempLabel uq
469 Just (DestBlockId blockid') -> shortBlockId fn blockid'
470 Just (DestImm (ImmCLbl lbl)) -> lbl
471 _other -> panic "shortBlockId"
473 -- -----------------------------------------------------------------------------
474 -- 'patchRegs' function
476 -- 'patchRegs' takes an instruction and applies the given mapping to
477 -- all the register references.
479 patchRegs :: Instr -> (Reg -> Reg) -> Instr
481 #if alpha_TARGET_ARCH
483 patchRegs instr env = case instr of
484 SPILL reg slot -> SPILL (env reg) slot
485 RELOAD slot reg -> RELOAD slot (env reg)
486 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
487 LDA reg addr -> LDA (env reg) (fixAddr addr)
488 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
489 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
490 LDI sz reg imm -> LDI sz (env reg) imm
491 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
492 CLR reg -> CLR (env reg)
493 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
494 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
495 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
496 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
497 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
498 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
499 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
500 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
501 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
502 NOT ar reg -> NOT (fixRI ar) (env reg)
503 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
504 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
505 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
506 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
507 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
508 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
509 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
510 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
511 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
512 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
513 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
514 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
515 FCLR reg -> FCLR (env reg)
516 FABS r1 r2 -> FABS (env r1) (env r2)
517 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
518 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
519 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
520 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
521 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
522 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
523 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
524 FMOV r1 r2 -> FMOV (env r1) (env r2)
525 BI cond reg lbl -> BI cond (env reg) lbl
526 BF cond reg lbl -> BF cond (env reg) lbl
527 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
528 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
531 fixAddr (AddrReg r1) = AddrReg (env r1)
532 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
533 fixAddr other = other
535 fixRI (RIReg r) = RIReg (env r)
538 #endif /* alpha_TARGET_ARCH */
539 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
540 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
542 patchRegs instr env = case instr of
543 MOV sz src dst -> patch2 (MOV sz) src dst
544 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
545 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
546 LEA sz src dst -> patch2 (LEA sz) src dst
547 ADD sz src dst -> patch2 (ADD sz) src dst
548 ADC sz src dst -> patch2 (ADC sz) src dst
549 SUB sz src dst -> patch2 (SUB sz) src dst
550 IMUL sz src dst -> patch2 (IMUL sz) src dst
551 IMUL2 sz src -> patch1 (IMUL2 sz) src
552 MUL sz src dst -> patch2 (MUL sz) src dst
553 IDIV sz op -> patch1 (IDIV sz) op
554 DIV sz op -> patch1 (DIV sz) op
555 AND sz src dst -> patch2 (AND sz) src dst
556 OR sz src dst -> patch2 (OR sz) src dst
557 XOR sz src dst -> patch2 (XOR sz) src dst
558 NOT sz op -> patch1 (NOT sz) op
559 NEGI sz op -> patch1 (NEGI sz) op
560 SHL sz imm dst -> patch1 (SHL sz imm) dst
561 SAR sz imm dst -> patch1 (SAR sz imm) dst
562 SHR sz imm dst -> patch1 (SHR sz imm) dst
563 BT sz imm src -> patch1 (BT sz imm) src
564 TEST sz src dst -> patch2 (TEST sz) src dst
565 CMP sz src dst -> patch2 (CMP sz) src dst
566 PUSH sz op -> patch1 (PUSH sz) op
567 POP sz op -> patch1 (POP sz) op
568 SETCC cond op -> patch1 (SETCC cond) op
569 JMP op -> patch1 JMP op
570 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
573 GMOV src dst -> GMOV (env src) (env dst)
574 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
575 GST sz src dst -> GST sz (env src) (lookupAddr dst)
577 GLDZ dst -> GLDZ (env dst)
578 GLD1 dst -> GLD1 (env dst)
580 GFTOI src dst -> GFTOI (env src) (env dst)
581 GDTOI src dst -> GDTOI (env src) (env dst)
583 GITOF src dst -> GITOF (env src) (env dst)
584 GITOD src dst -> GITOD (env src) (env dst)
586 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
587 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
588 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
589 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
591 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
592 GABS sz src dst -> GABS sz (env src) (env dst)
593 GNEG sz src dst -> GNEG sz (env src) (env dst)
594 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
595 GSIN sz src dst -> GSIN sz (env src) (env dst)
596 GCOS sz src dst -> GCOS sz (env src) (env dst)
597 GTAN sz src dst -> GTAN sz (env src) (env dst)
600 #if x86_64_TARGET_ARCH
601 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
602 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
603 CVTTSS2SIQ src dst -> CVTTSS2SIQ (patchOp src) (env dst)
604 CVTTSD2SIQ src dst -> CVTTSD2SIQ (patchOp src) (env dst)
605 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
606 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
607 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
610 CALL (Left imm) _ -> instr
611 CALL (Right reg) p -> CALL (Right (env reg)) p
613 FETCHGOT reg -> FETCHGOT (env reg)
614 FETCHPC reg -> FETCHPC (env reg)
619 SPILL reg slot -> SPILL (env reg) slot
620 RELOAD slot reg -> RELOAD slot (env reg)
626 _other -> panic "patchRegs: unrecognised instr"
629 patch1 insn op = insn $! patchOp op
630 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
632 patchOp (OpReg reg) = OpReg $! env reg
633 patchOp (OpImm imm) = OpImm imm
634 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
636 lookupAddr (ImmAddr imm off) = ImmAddr imm off
637 lookupAddr (AddrBaseIndex base index disp)
638 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
640 lookupBase EABaseNone = EABaseNone
641 lookupBase EABaseRip = EABaseRip
642 lookupBase (EABaseReg r) = EABaseReg (env r)
644 lookupIndex EAIndexNone = EAIndexNone
645 lookupIndex (EAIndex r i) = EAIndex (env r) i
647 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
648 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
649 #if sparc_TARGET_ARCH
651 patchRegs instr env = case instr of
652 SPILL reg slot -> SPILL (env reg) slot
653 RELOAD slot reg -> RELOAD slot (env reg)
654 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
655 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
656 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
657 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
658 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
659 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
660 RDY rd -> RDY (env rd)
661 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
662 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
663 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
664 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
665 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
666 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
667 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
668 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
669 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
670 SETHI imm reg -> SETHI imm (env reg)
671 FABS s r1 r2 -> FABS s (env r1) (env r2)
672 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
673 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
674 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
675 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
676 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
677 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
678 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
679 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
680 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
681 JMP addr -> JMP (fixAddr addr)
682 CALL (Left i) n t -> CALL (Left i) n t
683 CALL (Right r) n t -> CALL (Right (env r)) n t
686 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
687 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
689 fixRI (RIReg r) = RIReg (env r)
692 #endif /* sparc_TARGET_ARCH */
693 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
694 #if powerpc_TARGET_ARCH
696 patchRegs instr env = case instr of
697 SPILL reg slot -> SPILL (env reg) slot
698 RELOAD slot reg -> RELOAD slot (env reg)
700 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
701 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
702 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
703 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
704 LIS reg imm -> LIS (env reg) imm
705 LI reg imm -> LI (env reg) imm
706 MR reg1 reg2 -> MR (env reg1) (env reg2)
707 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
708 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
709 BCC cond lbl -> BCC cond lbl
710 BCCFAR cond lbl -> BCCFAR cond lbl
711 MTCTR reg -> MTCTR (env reg)
712 BCTR targets -> BCTR targets
713 BL imm argRegs -> BL imm argRegs -- argument regs
714 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
715 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
716 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
717 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
718 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
719 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
720 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
721 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
722 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
723 MULLW_MayOflo reg1 reg2 reg3
724 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
725 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
726 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
727 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
728 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
729 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
730 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
731 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
732 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
733 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
734 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
735 RLWINM reg1 reg2 sh mb me
736 -> RLWINM (env reg1) (env reg2) sh mb me
737 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
738 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
739 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
740 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
741 FNEG r1 r2 -> FNEG (env r1) (env r2)
742 FCMP r1 r2 -> FCMP (env r1) (env r2)
743 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
744 FRSP r1 r2 -> FRSP (env r1) (env r2)
745 MFCR reg -> MFCR (env reg)
746 MFLR reg -> MFLR (env reg)
747 FETCHPC reg -> FETCHPC (env reg)
750 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
751 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
753 fixRI (RIReg r) = RIReg (env r)
755 #endif /* powerpc_TARGET_ARCH */
757 -- -----------------------------------------------------------------------------
758 -- Detecting reg->reg moves
760 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
761 -- by assigning the src and dest temporaries to the same real register.
763 isRegRegMove :: Instr -> Maybe (Reg,Reg)
764 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
766 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
767 #elif powerpc_TARGET_ARCH
768 isRegRegMove (MR dst src) = Just (src,dst)
770 #warning ToDo: isRegRegMove
772 isRegRegMove _ = Nothing
774 -- -----------------------------------------------------------------------------
775 -- Generating spill instructions
778 :: Reg -- register to spill
779 -> Int -- current stack delta
780 -> Int -- spill slot to use
782 mkSpillInstr reg delta slot
783 = let off = spillSlotToOffset slot
785 #ifdef alpha_TARGET_ARCH
786 {-Alpha: spill below the stack pointer (?)-}
787 ST sz dyn (spRel (- (off `div` 8)))
789 #ifdef i386_TARGET_ARCH
790 let off_w = (off-delta) `div` 4
791 in case regClass reg of
792 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
793 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
795 #ifdef x86_64_TARGET_ARCH
796 let off_w = (off-delta) `div` 8
797 in case regClass reg of
798 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
799 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
800 -- ToDo: will it work to always spill as a double?
801 -- does that cause a stall if the data was a float?
803 #ifdef sparc_TARGET_ARCH
804 {-SPARC: spill below frame pointer leaving 2 words/spill-}
805 let{off_w = 1 + (off `div` 4);
806 sz = case regClass reg of {
810 in ST sz reg (fpRel (- off_w))
812 #ifdef powerpc_TARGET_ARCH
813 let sz = case regClass reg of
816 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
821 :: Reg -- register to load
822 -> Int -- current stack delta
823 -> Int -- spill slot to use
825 mkLoadInstr reg delta slot
826 = let off = spillSlotToOffset slot
828 #if alpha_TARGET_ARCH
829 LD sz dyn (spRel (- (off `div` 8)))
832 let off_w = (off-delta) `div` 4
833 in case regClass reg of {
834 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
835 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
837 #if x86_64_TARGET_ARCH
838 let off_w = (off-delta) `div` 8
839 in case regClass reg of
840 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
841 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
843 #if sparc_TARGET_ARCH
844 let{off_w = 1 + (off `div` 4);
845 sz = case regClass reg of {
849 in LD sz (fpRel (- off_w)) reg
851 #if powerpc_TARGET_ARCH
852 let sz = case regClass reg of
855 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
862 mkRegRegMoveInstr src dst
863 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
864 = case regClass src of
865 RcInteger -> MOV wordRep (OpReg src) (OpReg dst)
867 RcDouble -> GMOV src dst
869 RcDouble -> MOV F64 (OpReg src) (OpReg dst)
871 #elif powerpc_TARGET_ARCH
878 #if alpha_TARGET_ARCH
879 mkBranchInstr id = [BR id]
882 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
883 mkBranchInstr id = [JXX ALWAYS id]
886 #if sparc_TARGET_ARCH
887 mkBranchInstr (BlockId id) = [BI ALWAYS False (ImmCLbl (mkAsmTempLabel id)), NOP]
890 #if powerpc_TARGET_ARCH
891 mkBranchInstr id = [BCC ALWAYS id]
896 spillSlotSize = IF_ARCH_i386(12, 8)
899 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
901 -- convert a spill slot number to a *byte* offset, with no sign:
902 -- decide on a per arch basis whether you are spilling above or below
903 -- the C stack pointer.
904 spillSlotToOffset :: Int -> Int
905 spillSlotToOffset slot
906 | slot >= 0 && slot < maxSpillSlots
907 = 64 + spillSlotSize * slot
909 = pprPanic "spillSlotToOffset:"
910 ( text "invalid spill location: " <> int slot
911 $$ text "maxSpillSlots: " <> int maxSpillSlots)