1 {-# OPTIONS -fno-warn-missing-signatures #-}
2 -----------------------------------------------------------------------------
4 -- The register allocator
6 -- (c) The University of Glasgow 2004
8 -----------------------------------------------------------------------------
11 The algorithm is roughly:
13 1) Compute strongly connected components of the basic block list.
15 2) Compute liveness (mapping from pseudo register to
18 3) Walk instructions in each basic block. We keep track of
19 (a) Free real registers (a bitmap?)
20 (b) Current assignment of temporaries to machine registers and/or
21 spill slots (call this the "assignment").
22 (c) Partial mapping from basic block ids to a virt-to-loc mapping.
23 When we first encounter a branch to a basic block,
24 we fill in its entry in this table with the current mapping.
27 (a) For each real register clobbered by this instruction:
28 If a temporary resides in it,
29 If the temporary is live after this instruction,
30 Move the temporary to another (non-clobbered & free) reg,
31 or spill it to memory. Mark the temporary as residing
32 in both memory and a register if it was spilled (it might
33 need to be read by this instruction).
34 (ToDo: this is wrong for jump instructions?)
36 (b) For each temporary *read* by the instruction:
37 If the temporary does not have a real register allocation:
38 - Allocate a real register from the free list. If
40 - Find a temporary to spill. Pick one that is
41 not used in this instruction (ToDo: not
43 - generate a spill instruction
44 - If the temporary was previously spilled,
45 generate an instruction to read the temp from its spill loc.
46 (optimisation: if we can see that a real register is going to
47 be used soon, then don't use it for allocation).
49 (c) Update the current assignment
51 (d) If the intstruction is a branch:
52 if the destination block already has a register assignment,
53 Generate a new block with fixup code and redirect the
54 jump to the new block.
56 Update the block id->assignment mapping with the current
59 (e) Delete all register assignments for temps which are read
60 (only) and die here. Update the free register list.
62 (f) Mark all registers clobbered by this instruction as not free,
63 and mark temporaries which have been spilled due to clobbering
64 as in memory (step (a) marks then as in both mem & reg).
66 (g) For each temporary *written* by this instruction:
67 Allocate a real register as for (b), spilling something
69 - except when updating the assignment, drop any memory
70 locations that the temporary was previously in, since
71 they will be no longer valid after this instruction.
73 (h) Delete all register assignments for temps which are
74 written and die here (there should rarely be any). Update
75 the free register list.
77 (i) Rewrite the instruction with the new mapping.
79 (j) For each spilled reg known to be now dead, re-add its stack slot
84 module RegAllocLinear (
86 RegAllocStats, pprStats
89 #include "HsVersions.h"
96 import Cmm hiding (RegSet)
99 import Unique ( Uniquable(getUnique), Unique )
114 -- -----------------------------------------------------------------------------
115 -- The free register set
117 -- This needs to be *efficient*
119 {- Here's an inefficient 'executable specification' of the FreeRegs data type:
120 type FreeRegs = [RegNo]
123 releaseReg n f = if n `elem` f then f else (n : f)
124 initFreeRegs = allocatableRegs
125 getFreeRegs cls f = filter ( (==cls) . regClass . RealReg ) f
126 allocateReg f r = filter (/= r) f
129 #if defined(powerpc_TARGET_ARCH)
131 -- The PowerPC has 32 integer and 32 floating point registers.
132 -- This is 32bit PowerPC, so Word64 is inefficient - two Word32s are much
134 -- Note that when getFreeRegs scans for free registers, it starts at register
135 -- 31 and counts down. This is a hack for the PowerPC - the higher-numbered
136 -- registers are callee-saves, while the lower regs are caller-saves, so it
137 -- makes sense to start at the high end.
138 -- Apart from that, the code does nothing PowerPC-specific, so feel free to
139 -- add your favourite platform to the #if (if you have 64 registers but only
142 data FreeRegs = FreeRegs !Word32 !Word32
143 deriving( Show ) -- The Show is used in an ASSERT
145 noFreeRegs :: FreeRegs
146 noFreeRegs = FreeRegs 0 0
148 releaseReg :: RegNo -> FreeRegs -> FreeRegs
149 releaseReg r (FreeRegs g f)
150 | r > 31 = FreeRegs g (f .|. (1 `shiftL` (fromIntegral r - 32)))
151 | otherwise = FreeRegs (g .|. (1 `shiftL` fromIntegral r)) f
153 initFreeRegs :: FreeRegs
154 initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
156 getFreeRegs :: RegClass -> FreeRegs -> [RegNo] -- lazilly
157 getFreeRegs cls (FreeRegs g f)
158 | RcDouble <- cls = go f (0x80000000) 63
159 | RcInteger <- cls = go g (0x80000000) 31
160 | otherwise = pprPanic "RegAllocLinear.getFreeRegs: Bad cls" (ppr cls)
163 go x m i | x .&. m /= 0 = i : (go x (m `shiftR` 1) $! i-1)
164 | otherwise = go x (m `shiftR` 1) $! i-1
166 allocateReg :: RegNo -> FreeRegs -> FreeRegs
167 allocateReg r (FreeRegs g f)
168 | r > 31 = FreeRegs g (f .&. complement (1 `shiftL` (fromIntegral r - 32)))
169 | otherwise = FreeRegs (g .&. complement (1 `shiftL` fromIntegral r)) f
173 -- If we have less than 32 registers, or if we have efficient 64-bit words,
174 -- we will just use a single bitfield.
176 #if defined(alpha_TARGET_ARCH)
177 type FreeRegs = Word64
179 type FreeRegs = Word32
182 noFreeRegs :: FreeRegs
185 releaseReg :: RegNo -> FreeRegs -> FreeRegs
186 releaseReg n f = f .|. (1 `shiftL` n)
188 initFreeRegs :: FreeRegs
189 initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
191 getFreeRegs :: RegClass -> FreeRegs -> [RegNo] -- lazilly
192 getFreeRegs cls f = go f 0
195 | n .&. 1 /= 0 && regClass (RealReg m) == cls
196 = m : (go (n `shiftR` 1) $! (m+1))
198 = go (n `shiftR` 1) $! (m+1)
199 -- ToDo: there's no point looking through all the integer registers
200 -- in order to find a floating-point one.
202 allocateReg :: RegNo -> FreeRegs -> FreeRegs
203 allocateReg r f = f .&. complement (1 `shiftL` fromIntegral r)
207 -- -----------------------------------------------------------------------------
208 -- The assignment of virtual registers to stack slots
210 -- We have lots of stack slots. Memory-to-memory moves are a pain on most
211 -- architectures. Therefore, we avoid having to generate memory-to-memory moves
212 -- by simply giving every virtual register its own stack slot.
214 -- The StackMap stack map keeps track of virtual register - stack slot
215 -- associations and of which stack slots are still free. Once it has been
216 -- associated, a stack slot is never "freed" or removed from the StackMap again,
217 -- it remains associated until we are done with the current CmmProc.
220 data StackMap = StackMap [StackSlot] (UniqFM StackSlot)
222 emptyStackMap :: StackMap
223 emptyStackMap = StackMap [0..maxSpillSlots] emptyUFM
225 getStackSlotFor :: StackMap -> Unique -> (StackMap,Int)
226 getStackSlotFor (StackMap [] _) _
227 = panic "RegAllocLinear.getStackSlotFor: out of stack slots, try -fregs-graph"
228 -- This happens with darcs' SHA1.hs, see #1993
230 getStackSlotFor fs@(StackMap (freeSlot:stack') reserved) reg =
231 case lookupUFM reserved reg of
232 Just slot -> (fs,slot)
233 Nothing -> (StackMap stack' (addToUFM reserved reg freeSlot), freeSlot)
235 -- -----------------------------------------------------------------------------
236 -- Top level of the register allocator
238 -- Allocate registers
241 -> UniqSM (NatCmmTop, Maybe RegAllocStats)
243 regAlloc (CmmData sec d)
248 regAlloc (CmmProc (LiveInfo info _ _) lbl params (ListGraph []))
249 = return ( CmmProc info lbl params (ListGraph [])
252 regAlloc (CmmProc static lbl params (ListGraph comps))
253 | LiveInfo info (Just first_id) block_live <- static
255 -- do register allocation on each component.
256 (final_blocks, stats)
257 <- linearRegAlloc first_id block_live
258 $ map (\b -> case b of
259 BasicBlock _ [b] -> AcyclicSCC b
260 BasicBlock _ bs -> CyclicSCC bs)
263 -- make sure the block that was first in the input list
264 -- stays at the front of the output
265 let ((first':_), rest')
266 = partition ((== first_id) . blockId) final_blocks
268 return ( CmmProc info lbl params (ListGraph (first' : rest'))
271 -- bogus. to make non-exhaustive match warning go away.
272 regAlloc (CmmProc _ _ _ _)
273 = panic "RegAllocLinear.regAlloc: no match"
276 -- -----------------------------------------------------------------------------
277 -- Linear sweep to allocate registers
279 data Loc = InReg {-# UNPACK #-} !RegNo
280 | InMem {-# UNPACK #-} !Int -- stack slot
281 | InBoth {-# UNPACK #-} !RegNo
282 {-# UNPACK #-} !Int -- stack slot
283 deriving (Eq, Show, Ord)
286 A temporary can be marked as living in both a register and memory
287 (InBoth), for example if it was recently loaded from a spill location.
288 This makes it cheap to spill (no save instruction required), but we
289 have to be careful to turn this into InReg if the value in the
292 This is also useful when a temporary is about to be clobbered. We
293 save it in a spill location, but mark it as InBoth because the current
294 instruction might still want to read it.
297 instance Outputable Loc where
298 ppr l = text (show l)
301 -- | Do register allocation on some basic blocks.
302 -- But be careful to allocate a block in an SCC only if it has
303 -- an entry in the block map or it is the first block.
306 :: BlockId -- ^ the first block
307 -> BlockMap RegSet -- ^ live regs on entry to each basic block
308 -> [SCC LiveBasicBlock] -- ^ instructions annotated with "deaths"
309 -> UniqSM ([NatBasicBlock], RegAllocStats)
311 linearRegAlloc first_id block_live sccs
313 let (_, _, stats, blocks) =
314 runR emptyBlockMap initFreeRegs emptyRegMap emptyStackMap us
315 $ linearRA_SCCs first_id block_live [] sccs
317 return (blocks, stats)
319 linearRA_SCCs _ _ blocksAcc []
320 = return $ reverse blocksAcc
322 linearRA_SCCs first_id block_live blocksAcc (AcyclicSCC block : sccs)
323 = do blocks' <- processBlock block_live block
324 linearRA_SCCs first_id block_live
325 ((reverse blocks') ++ blocksAcc)
328 linearRA_SCCs first_id block_live blocksAcc (CyclicSCC blocks : sccs)
329 = do let process [] [] accum = return $ reverse accum
330 process [] next_round accum = process next_round [] accum
331 process (b@(BasicBlock id _) : blocks) next_round accum =
332 do block_assig <- getBlockAssigR
333 if isJust (lookupBlockEnv block_assig id) || id == first_id
334 then do b' <- processBlock block_live b
335 process blocks next_round (b' : accum)
336 else process blocks (b : next_round) accum
337 blockss' <- process blocks [] (return [])
338 linearRA_SCCs first_id block_live
339 (reverse (concat blockss') ++ blocksAcc)
343 -- | Do register allocation on this basic block
346 :: BlockMap RegSet -- ^ live regs on entry to each basic block
347 -> LiveBasicBlock -- ^ block to do register allocation on
348 -> RegM [NatBasicBlock] -- ^ block with registers allocated
350 processBlock block_live (BasicBlock id instrs)
353 <- linearRA block_live [] [] instrs
355 return $ BasicBlock id instrs' : fixups
358 -- | Load the freeregs and current reg assignment into the RegM state
359 -- for the basic block with this BlockId.
360 initBlock :: BlockId -> RegM ()
362 = do block_assig <- getBlockAssigR
363 case lookupBlockEnv block_assig id of
364 -- no prior info about this block: assume everything is
365 -- free and the assignment is empty.
367 -> do setFreeRegsR initFreeRegs
368 setAssigR emptyRegMap
370 -- load info about register assignments leading into this block.
371 Just (freeregs, assig)
372 -> do setFreeRegsR freeregs
378 -> [Instr] -> [NatBasicBlock] -> [LiveInstr]
379 -> RegM ([Instr], [NatBasicBlock])
381 linearRA _ instr_acc fixups []
382 = return (reverse instr_acc, fixups)
384 linearRA block_live instr_acc fixups (instr:instrs)
385 = do (instr_acc', new_fixups) <- raInsn block_live instr_acc instr
386 linearRA block_live instr_acc' (new_fixups++fixups) instrs
388 -- -----------------------------------------------------------------------------
389 -- Register allocation for a single instruction
391 type BlockAssignment = BlockMap (FreeRegs, RegMap Loc)
393 raInsn :: BlockMap RegSet -- Live temporaries at each basic block
394 -> [Instr] -- new instructions (accum.)
395 -> LiveInstr -- the instruction (with "deaths")
397 [Instr], -- new instructions
398 [NatBasicBlock] -- extra fixup blocks
401 raInsn _ new_instrs (Instr (COMMENT _) Nothing)
402 = return (new_instrs, [])
404 raInsn _ new_instrs (Instr (DELTA n) Nothing)
407 return (new_instrs, [])
409 raInsn block_live new_instrs (Instr instr (Just live))
413 -- If we have a reg->reg move between virtual registers, where the
414 -- src register is not live after this instruction, and the dst
415 -- register does not already have an assignment,
416 -- and the source register is assigned to a register, not to a spill slot,
417 -- then we can eliminate the instruction.
418 -- (we can't eliminitate it if the source register is on the stack, because
419 -- we do not want to use one spill slot for different virtual registers)
420 case isRegRegMove instr of
421 Just (src,dst) | src `elementOfUniqSet` (liveDieRead live),
423 not (dst `elemUFM` assig),
424 Just (InReg _) <- (lookupUFM assig src) -> do
426 RealReg i -> setAssigR (addToUFM assig dst (InReg i))
427 -- if src is a fixed reg, then we just map dest to this
428 -- reg in the assignment. src must be an allocatable reg,
429 -- otherwise it wouldn't be in r_dying.
430 _virt -> case lookupUFM assig src of
431 Nothing -> panic "raInsn"
433 setAssigR (addToUFM (delFromUFM assig src) dst loc)
435 -- we have eliminated this instruction
437 freeregs <- getFreeRegsR
439 pprTrace "raInsn" (text "ELIMINATED: " <> docToSDoc (pprInstr instr) $$ ppr r_dying <+> ppr w_dying $$ text (show freeregs) $$ ppr assig) $ do
441 return (new_instrs, [])
443 _ -> genRaInsn block_live new_instrs instr
444 (uniqSetToList $ liveDieRead live)
445 (uniqSetToList $ liveDieWrite live)
449 = pprPanic "raInsn" (text "no match for:" <> ppr li)
452 genRaInsn block_live new_instrs instr r_dying w_dying =
453 case regUsage instr of { RU read written ->
454 case partition isRealReg written of { (real_written1,virt_written) ->
457 real_written = [ r | RealReg r <- real_written1 ]
459 -- we don't need to do anything with real registers that are
460 -- only read by this instr. (the list is typically ~2 elements,
461 -- so using nub isn't a problem).
462 virt_read = nub (filter isVirtualReg read)
465 -- (a) save any temporaries which will be clobbered by this instruction
466 clobber_saves <- saveClobberedTemps real_written r_dying
469 freeregs <- getFreeRegsR
471 pprTrace "raInsn" (docToSDoc (pprInstr instr) $$ ppr r_dying <+> ppr w_dying $$ ppr virt_read <+> ppr virt_written $$ text (show freeregs) $$ ppr assig) $ do
474 -- (b), (c) allocate real regs for all regs read by this instruction.
475 (r_spills, r_allocd) <-
476 allocateRegsAndSpill True{-reading-} virt_read [] [] virt_read
478 -- (d) Update block map for new destinations
479 -- NB. do this before removing dead regs from the assignment, because
480 -- these dead regs might in fact be live in the jump targets (they're
481 -- only dead in the code that follows in the current basic block).
482 (fixup_blocks, adjusted_instr)
483 <- joinToTargets block_live [] instr (jumpDests instr [])
485 -- (e) Delete all register assignments for temps which are read
486 -- (only) and die here. Update the free register list.
489 -- (f) Mark regs which are clobbered as unallocatable
490 clobberRegs real_written
492 -- (g) Allocate registers for temporaries *written* (only)
493 (w_spills, w_allocd) <-
494 allocateRegsAndSpill False{-writing-} virt_written [] [] virt_written
496 -- (h) Release registers for temps which are written here and not
501 -- (i) Patch the instruction
502 patch_map = listToUFM [ (t,RealReg r) |
503 (t,r) <- zip virt_read r_allocd
504 ++ zip virt_written w_allocd ]
506 patched_instr = patchRegs adjusted_instr patchLookup
507 patchLookup x = case lookupUFM patch_map x of
512 -- pprTrace "patched" (docToSDoc (pprInstr patched_instr)) $ do
514 -- (j) free up stack slots for dead spilled regs
515 -- TODO (can't be bothered right now)
517 -- erase reg->reg moves where the source and destination are the same.
518 -- If the src temp didn't die in this instr but happened to be allocated
519 -- to the same real reg as the destination, then we can erase the move anyway.
520 squashed_instr = case isRegRegMove patched_instr of
525 return (squashed_instr ++ w_spills ++ reverse r_spills
526 ++ clobber_saves ++ new_instrs,
530 -- -----------------------------------------------------------------------------
533 releaseRegs regs = do
538 loop _ free _ | free `seq` False = undefined
539 loop assig free [] = do setAssigR assig; setFreeRegsR free; return ()
540 loop assig free (RealReg r : rs) = loop assig (releaseReg r free) rs
541 loop assig free (r:rs) =
542 case lookupUFM assig r of
543 Just (InBoth real _) -> loop (delFromUFM assig r) (releaseReg real free) rs
544 Just (InReg real) -> loop (delFromUFM assig r) (releaseReg real free) rs
545 _other -> loop (delFromUFM assig r) free rs
547 -- -----------------------------------------------------------------------------
548 -- Clobber real registers
551 For each temp in a register that is going to be clobbered:
552 - if the temp dies after this instruction, do nothing
553 - otherwise, put it somewhere safe (another reg if possible,
554 otherwise spill and record InBoth in the assignment).
556 for allocateRegs on the temps *read*,
557 - clobbered regs are allocatable.
559 for allocateRegs on the temps *written*,
560 - clobbered regs are not allocatable.
564 :: [RegNo] -- real registers clobbered by this instruction
565 -> [Reg] -- registers which are no longer live after this insn
566 -> RegM [Instr] -- return: instructions to spill any temps that will
569 saveClobberedTemps [] _ = return [] -- common case
570 saveClobberedTemps clobbered dying = do
573 to_spill = [ (temp,reg) | (temp, InReg reg) <- ufmToList assig,
574 reg `elem` clobbered,
575 temp `notElem` map getUnique dying ]
577 (instrs,assig') <- clobber assig [] to_spill
581 clobber assig instrs [] = return (instrs,assig)
582 clobber assig instrs ((temp,reg):rest)
584 --ToDo: copy it to another register if possible
585 (spill,slot) <- spillR (RealReg reg) temp
586 recordSpill (SpillClobber temp)
588 let new_assign = addToUFM assig temp (InBoth reg slot)
589 clobber new_assign (spill : COMMENT (fsLit "spill clobber") : instrs) rest
591 clobberRegs :: [RegNo] -> RegM ()
592 clobberRegs [] = return () -- common case
593 clobberRegs clobbered = do
594 freeregs <- getFreeRegsR
595 setFreeRegsR $! foldr allocateReg freeregs clobbered
597 setAssigR $! clobber assig (ufmToList assig)
599 -- if the temp was InReg and clobbered, then we will have
600 -- saved it in saveClobberedTemps above. So the only case
601 -- we have to worry about here is InBoth. Note that this
602 -- also catches temps which were loaded up during allocation
603 -- of read registers, not just those saved in saveClobberedTemps.
604 clobber assig [] = assig
605 clobber assig ((temp, InBoth reg slot) : rest)
606 | reg `elem` clobbered
607 = clobber (addToUFM assig temp (InMem slot)) rest
608 clobber assig (_:rest)
611 -- -----------------------------------------------------------------------------
612 -- allocateRegsAndSpill
614 -- This function does several things:
615 -- For each temporary referred to by this instruction,
616 -- we allocate a real register (spilling another temporary if necessary).
617 -- We load the temporary up from memory if necessary.
618 -- We also update the register assignment in the process, and
619 -- the list of free registers and free stack slots.
622 :: Bool -- True <=> reading (load up spilled regs)
623 -> [Reg] -- don't push these out
624 -> [Instr] -- spill insns
625 -> [RegNo] -- real registers allocated (accum.)
626 -> [Reg] -- temps to allocate
627 -> RegM ([Instr], [RegNo])
629 allocateRegsAndSpill _ _ spills alloc []
630 = return (spills,reverse alloc)
632 allocateRegsAndSpill reading keep spills alloc (r:rs) = do
634 case lookupUFM assig r of
635 -- case (1a): already in a register
636 Just (InReg my_reg) ->
637 allocateRegsAndSpill reading keep spills (my_reg:alloc) rs
639 -- case (1b): already in a register (and memory)
640 -- NB1. if we're writing this register, update its assignemnt to be
641 -- InReg, because the memory value is no longer valid.
642 -- NB2. This is why we must process written registers here, even if they
643 -- are also read by the same instruction.
644 Just (InBoth my_reg _) -> do
645 when (not reading) (setAssigR (addToUFM assig r (InReg my_reg)))
646 allocateRegsAndSpill reading keep spills (my_reg:alloc) rs
648 -- Not already in a register, so we need to find a free one...
650 freeregs <- getFreeRegsR
652 case getFreeRegs (regClass r) freeregs of
654 -- case (2): we have a free register
656 spills' <- loadTemp reading r loc my_reg spills
658 | Just (InMem slot) <- loc, reading = InBoth my_reg slot
659 | otherwise = InReg my_reg
660 setAssigR (addToUFM assig r $! new_loc)
661 setFreeRegsR (allocateReg my_reg freeregs)
662 allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs
664 -- case (3): we need to push something out to free up a register
667 keep' = map getUnique keep
668 candidates1 = [ (temp,reg,mem)
669 | (temp, InBoth reg mem) <- ufmToList assig,
670 temp `notElem` keep', regClass (RealReg reg) == regClass r ]
671 candidates2 = [ (temp,reg)
672 | (temp, InReg reg) <- ufmToList assig,
673 temp `notElem` keep', regClass (RealReg reg) == regClass r ]
675 ASSERT2(not (null candidates1 && null candidates2),
676 text (show freeregs) <+> ppr r <+> ppr assig) do
680 -- we have a temporary that is in both register and mem,
681 -- just free up its register for use.
683 (temp,my_reg,slot):_ -> do
684 spills' <- loadTemp reading r loc my_reg spills
686 assig1 = addToUFM assig temp (InMem slot)
687 assig2 = addToUFM assig1 r (InReg my_reg)
690 allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs
692 -- otherwise, we need to spill a temporary that currently
693 -- resides in a register.
698 -- TODO: plenty of room for optimisation in choosing which temp
699 -- to spill. We just pick the first one that isn't used in
700 -- the current instruction for now.
702 let (temp_to_push_out, my_reg) = myHead "regalloc" candidates2
704 (spill_insn, slot) <- spillR (RealReg my_reg) temp_to_push_out
705 let spill_store = (if reading then id else reverse)
706 [ COMMENT (fsLit "spill alloc")
709 -- record that this temp was spilled
710 recordSpill (SpillAlloc temp_to_push_out)
712 -- update the register assignment
713 let assig1 = addToUFM assig temp_to_push_out (InMem slot)
714 let assig2 = addToUFM assig1 r (InReg my_reg)
717 -- if need be, load up a spilled temp into the reg we've just freed up.
718 spills' <- loadTemp reading r loc my_reg spills
720 allocateRegsAndSpill reading keep
721 (spill_store ++ spills')
725 -- | Load up a spilled temporary if we need to.
728 -> Reg -- the temp being loaded
729 -> Maybe Loc -- the current location of this temp
730 -> RegNo -- the hreg to load the temp into
734 loadTemp True vreg (Just (InMem slot)) hreg spills
736 insn <- loadR (RealReg hreg) slot
737 recordSpill (SpillLoad $ getUnique vreg)
738 return $ COMMENT (fsLit "spill load") : insn : spills
740 loadTemp _ _ _ _ spills =
744 myHead s [] = panic s
747 -- -----------------------------------------------------------------------------
748 -- Joining a jump instruction to its targets
750 -- The first time we encounter a jump to a particular basic block, we
751 -- record the assignment of temporaries. The next time we encounter a
752 -- jump to the same block, we compare our current assignment to the
753 -- stored one. They might be different if spilling has occrred in one
754 -- branch; so some fixup code will be required to match up the
762 -> RegM ([NatBasicBlock], Instr)
764 joinToTargets _ new_blocks instr []
765 = return (new_blocks, instr)
767 joinToTargets block_live new_blocks instr (dest:dests) = do
768 block_assig <- getBlockAssigR
771 -- adjust the assignment to remove any registers which are not
772 -- live on entry to the destination block.
773 adjusted_assig = filterUFM_Directly still_live assig
775 live_set = lookItUp "joinToTargets" block_live dest
776 still_live uniq _ = uniq `elemUniqSet_Directly` live_set
778 -- and free up those registers which are now free.
780 [ r | (reg, loc) <- ufmToList assig,
781 not (elemUniqSet_Directly reg live_set),
784 regsOfLoc (InReg r) = [r]
785 regsOfLoc (InBoth r _) = [r]
786 regsOfLoc (InMem _) = []
788 case lookupBlockEnv block_assig dest of
789 -- Nothing <=> this is the first time we jumped to this
792 freeregs <- getFreeRegsR
793 let freeregs' = foldr releaseReg freeregs to_free
794 setBlockAssigR (extendBlockEnv block_assig dest
795 (freeregs',adjusted_assig))
796 joinToTargets block_live new_blocks instr dests
800 -- the assignments match
801 | ufmToList dest_assig == ufmToList adjusted_assig
802 -> joinToTargets block_live new_blocks instr dests
809 let graph = makeRegMovementGraph adjusted_assig dest_assig
810 let sccs = stronglyConnCompFromEdgedVerticesR graph
811 fixUpInstrs <- mapM (handleComponent delta instr) sccs
813 block_id <- getUniqueR
814 let block = BasicBlock (BlockId block_id) $
815 concat fixUpInstrs ++ mkBranchInstr dest
817 let instr' = patchJump instr dest (BlockId block_id)
819 joinToTargets block_live (block : new_blocks) instr' dests
822 -- | Construct a graph of register\/spill movements.
824 -- We cut some corners by
825 -- a) not handling cyclic components
826 -- b) not handling memory-to-memory moves.
828 -- Cyclic components seem to occur only very rarely,
829 -- and we don't need memory-to-memory moves because we
830 -- make sure that every temporary always gets its own
833 makeRegMovementGraph :: RegMap Loc -> RegMap Loc -> [(Unique, Loc, [Loc])]
834 makeRegMovementGraph adjusted_assig dest_assig
837 = expandNode vreg src
838 $ lookupWithDefaultUFM_Directly
840 (panic "RegAllocLinear.makeRegMovementGraph")
843 in [ node | (vreg, src) <- ufmToList adjusted_assig
844 , node <- mkNodes src vreg ]
846 -- The InBoth handling is a little tricky here. If
847 -- the destination is InBoth, then we must ensure that
848 -- the value ends up in both locations. An InBoth
849 -- destination must conflict with an InReg or InMem
850 -- source, so we expand an InBoth destination as
851 -- necessary. An InBoth source is slightly different:
852 -- we only care about the register that the source value
853 -- is in, so that we can move it to the destinations.
855 expandNode vreg loc@(InReg src) (InBoth dst mem)
856 | src == dst = [(vreg, loc, [InMem mem])]
857 | otherwise = [(vreg, loc, [InReg dst, InMem mem])]
859 expandNode vreg loc@(InMem src) (InBoth dst mem)
860 | src == mem = [(vreg, loc, [InReg dst])]
861 | otherwise = [(vreg, loc, [InReg dst, InMem mem])]
863 expandNode _ (InBoth _ src) (InMem dst)
864 | src == dst = [] -- guaranteed to be true
866 expandNode _ (InBoth src _) (InReg dst)
869 expandNode vreg (InBoth src _) dst
870 = expandNode vreg (InReg src) dst
872 expandNode vreg src dst
874 | otherwise = [(vreg, src, [dst])]
877 -- | Make a move instruction between these two locations so we
878 -- can join together allocations for different basic blocks.
880 makeMove :: Int -> Unique -> Loc -> Loc -> RegM Instr
881 makeMove _ vreg (InReg src) (InReg dst)
882 = do recordSpill (SpillJoinRR vreg)
883 return $ mkRegRegMoveInstr (RealReg src) (RealReg dst)
885 makeMove delta vreg (InMem src) (InReg dst)
886 = do recordSpill (SpillJoinRM vreg)
887 return $ mkLoadInstr (RealReg dst) delta src
889 makeMove delta vreg (InReg src) (InMem dst)
890 = do recordSpill (SpillJoinRM vreg)
891 return $ mkSpillInstr (RealReg src) delta dst
893 makeMove _ vreg src dst
894 = panic $ "makeMove " ++ show vreg ++ " (" ++ show src ++ ") ("
896 ++ " (workaround: use -fviaC)"
899 -- we have eliminated any possibility of single-node cylces
900 -- in expandNode above.
901 handleComponent :: Int -> Instr -> SCC (Unique, Loc, [Loc]) -> RegM [Instr]
902 handleComponent delta _ (AcyclicSCC (vreg,src,dsts))
903 = mapM (makeMove delta vreg src) dsts
905 -- we can not have cycles that involve memory
906 -- locations as source nor as single destination
907 -- because memory locations (stack slots) are
908 -- allocated exclusively for a virtual register and
909 -- therefore can not require a fixup
910 handleComponent delta instr (CyclicSCC ((vreg, (InReg sreg),dsts):rest))
912 spill_id <- getUniqueR
913 (_, slot) <- spillR (RealReg sreg) spill_id
914 remainingFixUps <- mapM (handleComponent delta instr) (stronglyConnCompFromEdgedVerticesR rest)
915 restoreAndFixInstr <- getRestoreMoves dsts slot
916 return ([instr] ++ concat remainingFixUps ++ restoreAndFixInstr)
919 getRestoreMoves [r@(InReg reg), mem@(InMem _)] slot
921 restoreToReg <- loadR (RealReg reg) slot
922 moveInstr <- makeMove delta vreg r mem
923 return $ [COMMENT (fsLit "spill join move"), restoreToReg, moveInstr]
925 getRestoreMoves [InReg reg] slot
926 = loadR (RealReg reg) slot >>= return . (:[])
928 getRestoreMoves [InMem _] _ = panic "getRestoreMoves can not handle memory only restores"
929 getRestoreMoves _ _ = panic "getRestoreMoves unknown case"
932 handleComponent _ _ (CyclicSCC _)
933 = panic "Register Allocator: handleComponent cyclic"
937 -- -----------------------------------------------------------------------------
938 -- The register allocator's monad.
940 -- Here we keep all the state that the register allocator keeps track
941 -- of as it walks the instructions in a basic block.
945 ra_blockassig :: BlockAssignment,
946 -- The current mapping from basic blocks to
947 -- the register assignments at the beginning of that block.
948 ra_freeregs :: {-#UNPACK#-}!FreeRegs, -- free machine registers
949 ra_assig :: RegMap Loc, -- assignment of temps to locations
950 ra_delta :: Int, -- current stack delta
951 ra_stack :: StackMap, -- free stack slots for spilling
952 ra_us :: UniqSupply, -- unique supply for generating names
955 -- Record why things were spilled, for -ddrop-asm-stats.
956 -- Just keep a list here instead of a map of regs -> reasons.
957 -- We don't want to slow down the allocator if we're not going to emit the stats.
958 ra_spills :: [SpillReason]
961 newtype RegM a = RegM { unReg :: RA_State -> (# RA_State, a #) }
964 instance Monad RegM where
965 m >>= k = RegM $ \s -> case unReg m s of { (# s, a #) -> unReg (k a) s }
966 return a = RegM $ \s -> (# s, a #)
968 runR :: BlockAssignment -> FreeRegs -> RegMap Loc -> StackMap -> UniqSupply
969 -> RegM a -> (BlockAssignment, StackMap, RegAllocStats, a)
970 runR block_assig freeregs assig stack us thing =
971 case unReg thing (RA_State{ ra_blockassig=block_assig, ra_freeregs=freeregs,
972 ra_assig=assig, ra_delta=0{-???-}, ra_stack=stack,
973 ra_us = us, ra_spills = [] }) of
974 (# state'@RA_State{ ra_blockassig=block_assig, ra_stack=stack' }, returned_thing #)
975 -> (block_assig, stack', makeRAStats state', returned_thing)
977 spillR :: Reg -> Unique -> RegM (Instr, Int)
978 spillR reg temp = RegM $ \ s@RA_State{ra_delta=delta, ra_stack=stack} ->
979 let (stack',slot) = getStackSlotFor stack temp
980 instr = mkSpillInstr reg delta slot
982 (# s{ra_stack=stack'}, (instr,slot) #)
984 loadR :: Reg -> Int -> RegM Instr
985 loadR reg slot = RegM $ \ s@RA_State{ra_delta=delta} ->
986 (# s, mkLoadInstr reg delta slot #)
988 getFreeRegsR :: RegM FreeRegs
989 getFreeRegsR = RegM $ \ s@RA_State{ra_freeregs = freeregs} ->
992 setFreeRegsR :: FreeRegs -> RegM ()
993 setFreeRegsR regs = RegM $ \ s ->
994 (# s{ra_freeregs = regs}, () #)
996 getAssigR :: RegM (RegMap Loc)
997 getAssigR = RegM $ \ s@RA_State{ra_assig = assig} ->
1000 setAssigR :: RegMap Loc -> RegM ()
1001 setAssigR assig = RegM $ \ s ->
1002 (# s{ra_assig=assig}, () #)
1004 getBlockAssigR :: RegM BlockAssignment
1005 getBlockAssigR = RegM $ \ s@RA_State{ra_blockassig = assig} ->
1008 setBlockAssigR :: BlockAssignment -> RegM ()
1009 setBlockAssigR assig = RegM $ \ s ->
1010 (# s{ra_blockassig = assig}, () #)
1012 setDeltaR :: Int -> RegM ()
1013 setDeltaR n = RegM $ \ s ->
1014 (# s{ra_delta = n}, () #)
1016 getDeltaR :: RegM Int
1017 getDeltaR = RegM $ \s -> (# s, ra_delta s #)
1019 getUniqueR :: RegM Unique
1020 getUniqueR = RegM $ \s ->
1021 case splitUniqSupply (ra_us s) of
1022 (us1, us2) -> (# s{ra_us = us2}, uniqFromSupply us1 #)
1024 -- | Record that a spill instruction was inserted, for profiling.
1025 recordSpill :: SpillReason -> RegM ()
1027 = RegM $ \s -> (# s { ra_spills = spill : ra_spills s}, () #)
1029 -- -----------------------------------------------------------------------------
1031 -- | Reasons why instructions might be inserted by the spiller.
1032 -- Used when generating stats for -ddrop-asm-stats.
1035 = SpillAlloc !Unique -- ^ vreg was spilled to a slot so we could use its
1036 -- current hreg for another vreg
1037 | SpillClobber !Unique -- ^ vreg was moved because its hreg was clobbered
1038 | SpillLoad !Unique -- ^ vreg was loaded from a spill slot
1040 | SpillJoinRR !Unique -- ^ reg-reg move inserted during join to targets
1041 | SpillJoinRM !Unique -- ^ reg-mem move inserted during join to targets
1044 -- | Used to carry interesting stats out of the register allocator.
1047 { ra_spillInstrs :: UniqFM [Int] }
1050 -- | Make register allocator stats from its final state.
1051 makeRAStats :: RA_State -> RegAllocStats
1054 { ra_spillInstrs = binSpillReasons (ra_spills state) }
1057 -- | Build a map of how many times each reg was alloced, clobbered, loaded etc.
1059 :: [SpillReason] -> UniqFM [Int]
1061 binSpillReasons reasons
1065 (map (\reason -> case reason of
1066 SpillAlloc r -> (r, [1, 0, 0, 0, 0])
1067 SpillClobber r -> (r, [0, 1, 0, 0, 0])
1068 SpillLoad r -> (r, [0, 0, 1, 0, 0])
1069 SpillJoinRR r -> (r, [0, 0, 0, 1, 0])
1070 SpillJoinRM r -> (r, [0, 0, 0, 0, 1])) reasons)
1073 -- | Count reg-reg moves remaining in this code.
1074 countRegRegMovesNat :: NatCmmTop -> Int
1075 countRegRegMovesNat cmm
1076 = execState (mapGenBlockTopM countBlock cmm) 0
1078 countBlock b@(BasicBlock _ instrs)
1079 = do mapM_ countInstr instrs
1083 | Just _ <- isRegRegMove instr
1091 -- | Pretty print some RegAllocStats
1092 pprStats :: [NatCmmTop] -> [RegAllocStats] -> SDoc
1093 pprStats code statss
1094 = let -- sum up all the instrs inserted by the spiller
1095 spills = foldl' (plusUFM_C (zipWith (+)))
1097 $ map ra_spillInstrs statss
1099 spillTotals = foldl' (zipWith (+))
1103 -- count how many reg-reg-moves remain in the code
1104 moves = sum $ map countRegRegMovesNat code
1106 pprSpill (reg, spills)
1107 = parens $ (hcat $ punctuate (text ", ") (doubleQuotes (ppr reg) : map ppr spills))
1109 in ( text "-- spills-added-total"
1110 $$ text "-- (allocs, clobbers, loads, joinRR, joinRM, reg_reg_moves_remaining)"
1111 $$ (parens $ (hcat $ punctuate (text ", ") (map ppr spillTotals ++ [ppr moves])))
1113 $$ text "-- spills-added"
1114 $$ text "-- (reg_name, allocs, clobbers, loads, joinRR, joinRM)"
1115 $$ (vcat $ map pprSpill
1120 -- -----------------------------------------------------------------------------
1123 my_fromJust :: String -> SDoc -> Maybe a -> a
1124 my_fromJust _ _ (Just x) = x
1125 my_fromJust s p Nothing = pprPanic ("fromJust: " ++ s) p
1127 lookItUp :: String -> BlockMap a -> BlockId -> a
1128 lookItUp str fm x = my_fromJust str (ppr x) (lookupBlockEnv fm x)