1 -----------------------------------------------------------------------------
3 -- The register allocator
5 -- (c) The University of Glasgow 2004
7 -----------------------------------------------------------------------------
10 The algorithm is roughly:
12 1) Compute strongly connected components of the basic block list.
14 2) Compute liveness (mapping from pseudo register to
17 3) Walk instructions in each basic block. We keep track of
18 (a) Free real registers (a bitmap?)
19 (b) Current assignment of temporaries to machine registers and/or
20 spill slots (call this the "assignment").
21 (c) Partial mapping from basic block ids to a virt-to-loc mapping.
22 When we first encounter a branch to a basic block,
23 we fill in its entry in this table with the current mapping.
26 (a) For each real register clobbered by this instruction:
27 If a temporary resides in it,
28 If the temporary is live after this instruction,
29 Move the temporary to another (non-clobbered & free) reg,
30 or spill it to memory. Mark the temporary as residing
31 in both memory and a register if it was spilled (it might
32 need to be read by this instruction).
33 (ToDo: this is wrong for jump instructions?)
35 (b) For each temporary *read* by the instruction:
36 If the temporary does not have a real register allocation:
37 - Allocate a real register from the free list. If
39 - Find a temporary to spill. Pick one that is
40 not used in this instruction (ToDo: not
42 - generate a spill instruction
43 - If the temporary was previously spilled,
44 generate an instruction to read the temp from its spill loc.
45 (optimisation: if we can see that a real register is going to
46 be used soon, then don't use it for allocation).
48 (c) Update the current assignment
50 (d) If the intstruction is a branch:
51 if the destination block already has a register assignment,
52 Generate a new block with fixup code and redirect the
53 jump to the new block.
55 Update the block id->assignment mapping with the current
58 (e) Delete all register assignments for temps which are read
59 (only) and die here. Update the free register list.
61 (f) Mark all registers clobbered by this instruction as not free,
62 and mark temporaries which have been spilled due to clobbering
63 as in memory (step (a) marks then as in both mem & reg).
65 (g) For each temporary *written* by this instruction:
66 Allocate a real register as for (b), spilling something
68 - except when updating the assignment, drop any memory
69 locations that the temporary was previously in, since
70 they will be no longer valid after this instruction.
72 (h) Delete all register assignments for temps which are
73 written and die here (there should rarely be any). Update
74 the free register list.
76 (i) Rewrite the instruction with the new mapping.
78 (j) For each spilled reg known to be now dead, re-add its stack slot
83 module RegisterAlloc (
87 #include "HsVersions.h"
96 import Unique ( Uniquable(getUnique), Unique )
103 import Data.Maybe ( fromJust )
105 import Data.Maybe ( fromMaybe )
106 import Data.List ( nub, partition, mapAccumL, groupBy )
107 import Control.Monad ( when )
111 -- -----------------------------------------------------------------------------
114 type RegSet = UniqSet Reg
116 type RegMap a = UniqFM a
117 emptyRegMap = emptyUFM
119 type BlockMap a = UniqFM a
120 emptyBlockMap = emptyUFM
122 -- A basic block where the isntructions are annotated with the registers
123 -- which are no longer live in the *next* instruction in this sequence.
124 -- (NB. if the instruction is a jump, these registers might still be live
125 -- at the jump target(s) - you have to check the liveness at the destination
126 -- block to find out).
128 = GenBasicBlock (Instr,
129 [Reg], -- registers read (only) which die
130 [Reg]) -- registers written which die
132 -- -----------------------------------------------------------------------------
133 -- The free register set
135 -- This needs to be *efficient*
137 {- Here's an inefficient 'executable specification' of the FreeRegs data type:
138 type FreeRegs = [RegNo]
141 releaseReg n f = if n `elem` f then f else (n : f)
142 initFreeRegs = allocatableRegs
143 getFreeRegs cls f = filter ( (==cls) . regClass . RealReg ) f
144 allocateReg f r = filter (/= r) f
147 #if defined(powerpc_TARGET_ARCH)
149 -- The PowerPC has 32 integer and 32 floating point registers.
150 -- This is 32bit PowerPC, so Word64 is inefficient - two Word32s are much
152 -- Note that when getFreeRegs scans for free registers, it starts at register
153 -- 31 and counts down. This is a hack for the PowerPC - the higher-numbered
154 -- registers are callee-saves, while the lower regs are caller-saves, so it
155 -- makes sense to start at the high end.
156 -- Apart from that, the code does nothing PowerPC-specific, so feel free to
157 -- add your favourite platform to the #if (if you have 64 registers but only
160 data FreeRegs = FreeRegs !Word32 !Word32
161 deriving( Show ) -- The Show is used in an ASSERT
163 noFreeRegs :: FreeRegs
164 noFreeRegs = FreeRegs 0 0
166 releaseReg :: RegNo -> FreeRegs -> FreeRegs
167 releaseReg r (FreeRegs g f)
168 | r > 31 = FreeRegs g (f .|. (1 `shiftL` (fromIntegral r - 32)))
169 | otherwise = FreeRegs (g .|. (1 `shiftL` fromIntegral r)) f
171 initFreeRegs :: FreeRegs
172 initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
174 getFreeRegs :: RegClass -> FreeRegs -> [RegNo] -- lazilly
175 getFreeRegs cls (FreeRegs g f)
176 | RcDouble <- cls = go f (0x80000000) 63
177 | RcInteger <- cls = go g (0x80000000) 31
180 go x m i | x .&. m /= 0 = i : (go x (m `shiftR` 1) $! i-1)
181 | otherwise = go x (m `shiftR` 1) $! i-1
183 allocateReg :: RegNo -> FreeRegs -> FreeRegs
184 allocateReg r (FreeRegs g f)
185 | r > 31 = FreeRegs g (f .&. complement (1 `shiftL` (fromIntegral r - 32)))
186 | otherwise = FreeRegs (g .&. complement (1 `shiftL` fromIntegral r)) f
190 -- If we have less than 32 registers, or if we have efficient 64-bit words,
191 -- we will just use a single bitfield.
193 #if defined(alpha_TARGET_ARCH)
194 type FreeRegs = Word64
196 type FreeRegs = Word32
199 noFreeRegs :: FreeRegs
202 releaseReg :: RegNo -> FreeRegs -> FreeRegs
203 releaseReg n f = f .|. (1 `shiftL` n)
205 initFreeRegs :: FreeRegs
206 initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
208 getFreeRegs :: RegClass -> FreeRegs -> [RegNo] -- lazilly
209 getFreeRegs cls f = go f 0
212 | n .&. 1 /= 0 && regClass (RealReg m) == cls
213 = m : (go (n `shiftR` 1) $! (m+1))
215 = go (n `shiftR` 1) $! (m+1)
216 -- ToDo: there's no point looking through all the integer registers
217 -- in order to find a floating-point one.
219 allocateReg :: RegNo -> FreeRegs -> FreeRegs
220 allocateReg r f = f .&. complement (1 `shiftL` fromIntegral r)
224 -- -----------------------------------------------------------------------------
225 -- The assignment of virtual registers to stack slots
227 -- We have lots of stack slots. Memory-to-memory moves are a pain on most
228 -- architectures. Therefore, we avoid having to generate memory-to-memory moves
229 -- by simply giving every virtual register its own stack slot.
231 -- The StackMap stack map keeps track of virtual register - stack slot
232 -- associations and of which stack slots are still free. Once it has been
233 -- associated, a stack slot is never "freed" or removed from the StackMap again,
234 -- it remains associated until we are done with the current CmmProc.
237 data StackMap = StackMap [StackSlot] (UniqFM StackSlot)
239 emptyStackMap :: StackMap
240 emptyStackMap = StackMap [0..maxSpillSlots] emptyUFM
242 getStackSlotFor :: StackMap -> Unique -> (StackMap,Int)
243 getStackSlotFor fs@(StackMap (freeSlot:stack') reserved) reg =
244 case lookupUFM reserved reg of
245 Just slot -> (fs,slot)
246 Nothing -> (StackMap stack' (addToUFM reserved reg freeSlot), freeSlot)
248 -- -----------------------------------------------------------------------------
249 -- Top level of the register allocator
251 regAlloc :: NatCmmTop -> UniqSM NatCmmTop
252 regAlloc (CmmData sec d) = returnUs $ CmmData sec d
253 regAlloc (CmmProc info lbl params [])
254 = returnUs $ CmmProc info lbl params [] -- no blocks to run the regalloc on
255 regAlloc (CmmProc info lbl params blocks@(first:rest))
257 first_id = blockId first
258 sccs = sccBlocks blocks
259 (ann_sccs, block_live) = computeLiveness sccs
260 in linearRegAlloc block_live ann_sccs `thenUs` \final_blocks ->
261 let ((first':_),rest') = partition ((== first_id) . blockId) final_blocks
262 in returnUs $ -- pprTrace "Liveness" (ppr block_live) $
263 CmmProc info lbl params (first':rest')
265 sccBlocks :: [NatBasicBlock] -> [SCC NatBasicBlock]
266 sccBlocks blocks = stronglyConnComp graph
268 getOutEdges :: [Instr] -> [BlockId]
269 getOutEdges instrs = foldr jumpDests [] instrs
271 graph = [ (block, getUnique id, map getUnique (getOutEdges instrs))
272 | block@(BasicBlock id instrs) <- blocks ]
275 -- -----------------------------------------------------------------------------
276 -- Computing liveness
279 :: [SCC NatBasicBlock]
280 -> ([SCC AnnBasicBlock], -- instructions annotated with list of registers
281 -- which are "dead after this instruction".
282 BlockMap RegSet) -- blocks annontated with set of live registers
283 -- on entry to the block.
285 -- NOTE: on entry, the SCCs are in "reverse" order: later blocks may transfer
286 -- control to earlier ones only. The SCCs returned are in the *opposite*
287 -- order, which is exactly what we want for the next pass.
290 = livenessSCCs emptyBlockMap [] sccs
294 -> [SCC AnnBasicBlock] -- accum
295 -> [SCC NatBasicBlock]
296 -> ([SCC AnnBasicBlock], BlockMap RegSet)
298 livenessSCCs blockmap done [] = (done, blockmap)
299 livenessSCCs blockmap done
300 (AcyclicSCC (BasicBlock block_id instrs) : sccs) =
301 {- pprTrace "live instrs" (ppr (getUnique block_id) $$
302 vcat (map (\(instr,regs) -> docToSDoc (pprInstr instr) $$ ppr regs) instrs')) $
304 livenessSCCs blockmap'
305 (AcyclicSCC (BasicBlock block_id instrs'):done) sccs
306 where (live,instrs') = liveness emptyUniqSet blockmap []
308 blockmap' = addToUFM blockmap block_id live
310 livenessSCCs blockmap done
311 (CyclicSCC blocks : sccs) =
312 livenessSCCs blockmap' (CyclicSCC blocks':done) sccs
313 where (blockmap', blocks')
314 = iterateUntilUnchanged linearLiveness equalBlockMaps
317 iterateUntilUnchanged
318 :: (a -> b -> (a,c)) -> (a -> a -> Bool)
322 iterateUntilUnchanged f eq a b
325 groupBy (\(a1, _) (a2, _) -> eq a1 a2) $
326 iterate (\(a, _) -> f a b) $
327 (a, error "RegisterAlloc.livenessSCCs")
330 linearLiveness :: BlockMap RegSet -> [NatBasicBlock]
331 -> (BlockMap RegSet, [AnnBasicBlock])
332 linearLiveness = mapAccumL processBlock
334 processBlock blockmap input@(BasicBlock block_id instrs)
335 = (blockmap', BasicBlock block_id instrs')
336 where (live,instrs') = liveness emptyUniqSet blockmap []
338 blockmap' = addToUFM blockmap block_id live
340 -- probably the least efficient way to compare two
341 -- BlockMaps for equality.
344 where a' = map f $ ufmToList a
345 b' = map f $ ufmToList b
346 f (key,elt) = (key, uniqSetToList elt)
348 liveness :: RegSet -- live regs
349 -> BlockMap RegSet -- live regs on entry to other BBs
350 -> [(Instr,[Reg],[Reg])] -- instructions (accum)
351 -> [Instr] -- instructions
352 -> (RegSet, [(Instr,[Reg],[Reg])])
354 liveness liveregs blockmap done [] = (liveregs, done)
355 liveness liveregs blockmap done (instr:instrs)
356 | not_a_branch = liveness liveregs1 blockmap
357 ((instr,r_dying,w_dying):done) instrs
358 | otherwise = liveness liveregs_br blockmap
359 ((instr,r_dying_br,w_dying):done) instrs
361 RU read written = regUsage instr
363 -- registers that were written here are dead going backwards.
364 -- registers that were read here are live going backwards.
365 liveregs1 = (liveregs `delListFromUniqSet` written)
366 `addListToUniqSet` read
368 -- registers that are not live beyond this point, are recorded
370 r_dying = [ reg | reg <- read, reg `notElem` written,
371 not (elementOfUniqSet reg liveregs) ]
373 w_dying = [ reg | reg <- written,
374 not (elementOfUniqSet reg liveregs) ]
376 -- union in the live regs from all the jump destinations of this
378 targets = jumpDests instr [] -- where we go from here
379 not_a_branch = null targets
381 targetLiveRegs target = case lookupUFM blockmap target of
383 Nothing -> emptyBlockMap
385 live_from_branch = unionManyUniqSets (map targetLiveRegs targets)
387 liveregs_br = liveregs1 `unionUniqSets` live_from_branch
389 -- registers that are live only in the branch targets should
390 -- be listed as dying here.
391 live_branch_only = live_from_branch `minusUniqSet` liveregs
392 r_dying_br = uniqSetToList (mkUniqSet r_dying `unionUniqSets`
395 -- -----------------------------------------------------------------------------
396 -- Linear sweep to allocate registers
398 data Loc = InReg {-# UNPACK #-} !RegNo
399 | InMem {-# UNPACK #-} !Int -- stack slot
400 | InBoth {-# UNPACK #-} !RegNo
401 {-# UNPACK #-} !Int -- stack slot
402 deriving (Eq, Show, Ord)
405 A temporary can be marked as living in both a register and memory
406 (InBoth), for example if it was recently loaded from a spill location.
407 This makes it cheap to spill (no save instruction required), but we
408 have to be careful to turn this into InReg if the value in the
411 This is also useful when a temporary is about to be clobbered. We
412 save it in a spill location, but mark it as InBoth because the current
413 instruction might still want to read it.
417 instance Outputable Loc where
418 ppr l = text (show l)
422 :: BlockMap RegSet -- live regs on entry to each basic block
423 -> [SCC AnnBasicBlock] -- instructions annotated with "deaths"
424 -> UniqSM [NatBasicBlock]
425 linearRegAlloc block_live sccs = linearRA_SCCs emptyBlockMap emptyStackMap sccs
430 -> [SCC AnnBasicBlock]
431 -> UniqSM [NatBasicBlock]
432 linearRA_SCCs block_assig stack [] = returnUs []
433 linearRA_SCCs block_assig stack
434 (AcyclicSCC (BasicBlock id instrs) : sccs)
435 = getUs `thenUs` \us ->
437 (block_assig',stack',(instrs',fixups)) =
438 case lookupUFM block_assig id of
439 -- no prior info about this block: assume everything is
440 -- free and the assignment is empty.
442 runR block_assig initFreeRegs
443 emptyRegMap stack us $
444 linearRA [] [] instrs
445 Just (freeregs,assig) ->
446 runR block_assig freeregs assig stack us $
447 linearRA [] [] instrs
449 linearRA_SCCs block_assig' stack' sccs `thenUs` \moreBlocks ->
450 returnUs $ BasicBlock id instrs' : fixups ++ moreBlocks
452 linearRA_SCCs block_assig stack
453 (CyclicSCC blocks : sccs)
454 = getUs `thenUs` \us ->
456 ((block_assig', stack', us'), blocks') = mapAccumL processBlock
457 (block_assig, stack, us)
460 linearRA_SCCs block_assig' stack' sccs `thenUs` \moreBlocks ->
461 returnUs $ concat blocks' ++ moreBlocks
463 processBlock (block_assig, stack, us0) (BasicBlock id instrs)
464 = ((block_assig', stack', us'), BasicBlock id instrs' : fixups)
466 (us, us') = splitUniqSupply us0
467 (block_assig',stack',(instrs',fixups)) =
468 case lookupUFM block_assig id of
469 -- no prior info about this block: assume everything is
470 -- free and the assignment is empty.
472 runR block_assig initFreeRegs
473 emptyRegMap stack us $
474 linearRA [] [] instrs
475 Just (freeregs,assig) ->
476 runR block_assig freeregs assig stack us $
477 linearRA [] [] instrs
479 linearRA :: [Instr] -> [NatBasicBlock] -> [(Instr,[Reg],[Reg])]
480 -> RegM ([Instr], [NatBasicBlock])
481 linearRA instr_acc fixups [] =
482 return (reverse instr_acc, fixups)
483 linearRA instr_acc fixups (instr:instrs) = do
484 (instr_acc', new_fixups) <- raInsn block_live instr_acc instr
485 linearRA instr_acc' (new_fixups++fixups) instrs
487 -- -----------------------------------------------------------------------------
488 -- Register allocation for a single instruction
490 type BlockAssignment = BlockMap (FreeRegs, RegMap Loc)
492 raInsn :: BlockMap RegSet -- Live temporaries at each basic block
493 -> [Instr] -- new instructions (accum.)
494 -> (Instr,[Reg],[Reg]) -- the instruction (with "deaths")
496 [Instr], -- new instructions
497 [NatBasicBlock] -- extra fixup blocks
500 raInsn block_live new_instrs (instr@(DELTA n), _, _) = do
502 return (new_instrs, [])
504 raInsn block_live new_instrs (instr, r_dying, w_dying) = do
507 -- If we have a reg->reg move between virtual registers, where the
508 -- src register is not live after this instruction, and the dst
509 -- register does not already have an assignment,
510 -- and the source register is assigned to a register, not to a spill slot,
511 -- then we can eliminate the instruction.
512 -- (we can't eliminitate it if the source register is on the stack, because
513 -- we do not want to use one spill slot for different virtual registers)
514 case isRegRegMove instr of
515 Just (src,dst) | src `elem` r_dying,
517 not (dst `elemUFM` assig),
518 Just (InReg _) <- (lookupUFM assig src) -> do
520 RealReg i -> setAssigR (addToUFM assig dst (InReg i))
521 -- if src is a fixed reg, then we just map dest to this
522 -- reg in the assignment. src must be an allocatable reg,
523 -- otherwise it wouldn't be in r_dying.
524 _virt -> case lookupUFM assig src of
525 Nothing -> panic "raInsn"
527 setAssigR (addToUFM (delFromUFM assig src) dst loc)
529 -- we have elimianted this instruction
531 freeregs <- getFreeRegsR
533 pprTrace "raInsn" (text "ELIMINATED: " <> docToSDoc (pprInstr instr) $$ ppr r_dying <+> ppr w_dying $$ text (show freeregs) $$ ppr assig) $ do
535 return (new_instrs, [])
537 other -> genRaInsn block_live new_instrs instr r_dying w_dying
540 genRaInsn block_live new_instrs instr r_dying w_dying =
541 case regUsage instr of { RU read written ->
542 case partition isRealReg written of { (real_written1,virt_written) ->
545 real_written = [ r | RealReg r <- real_written1 ]
547 -- we don't need to do anything with real registers that are
548 -- only read by this instr. (the list is typically ~2 elements,
549 -- so using nub isn't a problem).
550 virt_read = nub (filter isVirtualReg read)
553 -- (a) save any temporaries which will be clobbered by this instruction
554 clobber_saves <- saveClobberedTemps real_written r_dying
557 freeregs <- getFreeRegsR
559 pprTrace "raInsn" (docToSDoc (pprInstr instr) $$ ppr r_dying <+> ppr w_dying $$ ppr virt_read <+> ppr virt_written $$ text (show freeregs) $$ ppr assig) $ do
562 -- (b), (c) allocate real regs for all regs read by this instruction.
563 (r_spills, r_allocd) <-
564 allocateRegsAndSpill True{-reading-} virt_read [] [] virt_read
566 -- (d) Update block map for new destinations
567 -- NB. do this before removing dead regs from the assignment, because
568 -- these dead regs might in fact be live in the jump targets (they're
569 -- only dead in the code that follows in the current basic block).
570 (fixup_blocks, adjusted_instr)
571 <- joinToTargets block_live [] instr (jumpDests instr [])
573 -- (e) Delete all register assignments for temps which are read
574 -- (only) and die here. Update the free register list.
577 -- (f) Mark regs which are clobbered as unallocatable
578 clobberRegs real_written
580 -- (g) Allocate registers for temporaries *written* (only)
581 (w_spills, w_allocd) <-
582 allocateRegsAndSpill False{-writing-} virt_written [] [] virt_written
584 -- (h) Release registers for temps which are written here and not
589 -- (i) Patch the instruction
590 patch_map = listToUFM [ (t,RealReg r) |
591 (t,r) <- zip virt_read r_allocd
592 ++ zip virt_written w_allocd ]
594 patched_instr = patchRegs adjusted_instr patchLookup
595 patchLookup x = case lookupUFM patch_map x of
600 -- pprTrace "patched" (docToSDoc (pprInstr patched_instr)) $ do
602 -- (j) free up stack slots for dead spilled regs
603 -- TODO (can't be bothered right now)
605 return (patched_instr : w_spills ++ reverse r_spills
606 ++ clobber_saves ++ new_instrs,
610 -- -----------------------------------------------------------------------------
613 releaseRegs regs = do
618 loop assig free _ | free `seq` False = undefined
619 loop assig free [] = do setAssigR assig; setFreeRegsR free; return ()
620 loop assig free (RealReg r : rs) = loop assig (releaseReg r free) rs
621 loop assig free (r:rs) =
622 case lookupUFM assig r of
623 Just (InBoth real _) -> loop (delFromUFM assig r) (releaseReg real free) rs
624 Just (InReg real) -> loop (delFromUFM assig r) (releaseReg real free) rs
625 _other -> loop (delFromUFM assig r) free rs
627 -- -----------------------------------------------------------------------------
628 -- Clobber real registers
631 For each temp in a register that is going to be clobbered:
632 - if the temp dies after this instruction, do nothing
633 - otherwise, put it somewhere safe (another reg if possible,
634 otherwise spill and record InBoth in the assignment).
636 for allocateRegs on the temps *read*,
637 - clobbered regs are allocatable.
639 for allocateRegs on the temps *written*,
640 - clobbered regs are not allocatable.
644 :: [RegNo] -- real registers clobbered by this instruction
645 -> [Reg] -- registers which are no longer live after this insn
646 -> RegM [Instr] -- return: instructions to spill any temps that will
649 saveClobberedTemps [] _ = return [] -- common case
650 saveClobberedTemps clobbered dying = do
653 to_spill = [ (temp,reg) | (temp, InReg reg) <- ufmToList assig,
654 reg `elem` clobbered,
655 temp `notElem` map getUnique dying ]
657 (instrs,assig') <- clobber assig [] to_spill
661 clobber assig instrs [] = return (instrs,assig)
662 clobber assig instrs ((temp,reg):rest)
664 --ToDo: copy it to another register if possible
665 (spill,slot) <- spillR (RealReg reg) temp
666 clobber (addToUFM assig temp (InBoth reg slot)) (spill:instrs) rest
668 clobberRegs :: [RegNo] -> RegM ()
669 clobberRegs [] = return () -- common case
670 clobberRegs clobbered = do
671 freeregs <- getFreeRegsR
672 setFreeRegsR $! foldr allocateReg freeregs clobbered
674 setAssigR $! clobber assig (ufmToList assig)
676 -- if the temp was InReg and clobbered, then we will have
677 -- saved it in saveClobberedTemps above. So the only case
678 -- we have to worry about here is InBoth. Note that this
679 -- also catches temps which were loaded up during allocation
680 -- of read registers, not just those saved in saveClobberedTemps.
681 clobber assig [] = assig
682 clobber assig ((temp, InBoth reg slot) : rest)
683 | reg `elem` clobbered
684 = clobber (addToUFM assig temp (InMem slot)) rest
685 clobber assig (entry:rest)
688 -- -----------------------------------------------------------------------------
689 -- allocateRegsAndSpill
691 -- This function does several things:
692 -- For each temporary referred to by this instruction,
693 -- we allocate a real register (spilling another temporary if necessary).
694 -- We load the temporary up from memory if necessary.
695 -- We also update the register assignment in the process, and
696 -- the list of free registers and free stack slots.
699 :: Bool -- True <=> reading (load up spilled regs)
700 -> [Reg] -- don't push these out
701 -> [Instr] -- spill insns
702 -> [RegNo] -- real registers allocated (accum.)
703 -> [Reg] -- temps to allocate
704 -> RegM ([Instr], [RegNo])
706 allocateRegsAndSpill reading keep spills alloc []
707 = return (spills,reverse alloc)
709 allocateRegsAndSpill reading keep spills alloc (r:rs) = do
711 case lookupUFM assig r of
712 -- case (1a): already in a register
713 Just (InReg my_reg) ->
714 allocateRegsAndSpill reading keep spills (my_reg:alloc) rs
716 -- case (1b): already in a register (and memory)
717 -- NB1. if we're writing this register, update its assignemnt to be
718 -- InReg, because the memory value is no longer valid.
719 -- NB2. This is why we must process written registers here, even if they
720 -- are also read by the same instruction.
721 Just (InBoth my_reg mem) -> do
722 when (not reading) (setAssigR (addToUFM assig r (InReg my_reg)))
723 allocateRegsAndSpill reading keep spills (my_reg:alloc) rs
725 -- Not already in a register, so we need to find a free one...
727 freeregs <- getFreeRegsR
729 case getFreeRegs (regClass r) freeregs of
731 -- case (2): we have a free register
733 spills' <- do_load reading loc my_reg spills
735 | Just (InMem slot) <- loc, reading = InBoth my_reg slot
736 | otherwise = InReg my_reg
737 setAssigR (addToUFM assig r $! new_loc)
738 setFreeRegsR (allocateReg my_reg freeregs)
739 allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs
741 -- case (3): we need to push something out to free up a register
744 keep' = map getUnique keep
745 candidates1 = [ (temp,reg,mem)
746 | (temp, InBoth reg mem) <- ufmToList assig,
747 temp `notElem` keep', regClass (RealReg reg) == regClass r ]
748 candidates2 = [ (temp,reg)
749 | (temp, InReg reg) <- ufmToList assig,
750 temp `notElem` keep', regClass (RealReg reg) == regClass r ]
752 ASSERT2(not (null candidates1 && null candidates2),
753 text (show freeregs) <+> ppr r <+> ppr assig) do
757 -- we have a temporary that is in both register and mem,
758 -- just free up its register for use.
760 (temp,my_reg,slot):_ -> do
761 spills' <- do_load reading loc my_reg spills
763 assig1 = addToUFM assig temp (InMem slot)
764 assig2 = addToUFM assig1 r (InReg my_reg)
767 allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs
769 -- otherwise, we need to spill a temporary that currently
770 -- resides in a register.
773 (temp_to_push_out, my_reg) = myHead "regalloc" candidates2
774 -- TODO: plenty of room for optimisation in choosing which temp
775 -- to spill. We just pick the first one that isn't used in
776 -- the current instruction for now.
778 (spill_insn,slot) <- spillR (RealReg my_reg) temp_to_push_out
780 assig1 = addToUFM assig temp_to_push_out (InMem slot)
781 assig2 = addToUFM assig1 r (InReg my_reg)
784 spills' <- do_load reading loc my_reg spills
785 allocateRegsAndSpill reading keep (spill_insn:spills')
788 -- load up a spilled temporary if we need to
789 do_load True (Just (InMem slot)) reg spills = do
790 insn <- loadR (RealReg reg) slot
791 return (insn : spills)
792 do_load _ _ _ spills =
795 myHead s [] = panic s
798 -- -----------------------------------------------------------------------------
799 -- Joining a jump instruction to its targets
801 -- The first time we encounter a jump to a particular basic block, we
802 -- record the assignment of temporaries. The next time we encounter a
803 -- jump to the same block, we compare our current assignment to the
804 -- stored one. They might be different if spilling has occrred in one
805 -- branch; so some fixup code will be required to match up the
813 -> RegM ([NatBasicBlock], Instr)
815 joinToTargets block_live new_blocks instr []
816 = return (new_blocks, instr)
817 joinToTargets block_live new_blocks instr (dest:dests) = do
818 block_assig <- getBlockAssigR
821 -- adjust the assignment to remove any registers which are not
822 -- live on entry to the destination block.
823 adjusted_assig = filterUFM_Directly still_live assig
824 still_live uniq _ = uniq `elemUniqSet_Directly` live_set
826 -- and free up those registers which are now free.
828 [ r | (reg, loc) <- ufmToList assig,
829 not (elemUniqSet_Directly reg live_set),
832 regsOfLoc (InReg r) = [r]
833 regsOfLoc (InBoth r _) = [r]
834 regsOfLoc (InMem _) = []
836 case lookupUFM block_assig dest of
837 -- Nothing <=> this is the first time we jumped to this
840 freeregs <- getFreeRegsR
841 let freeregs' = foldr releaseReg freeregs to_free
842 setBlockAssigR (addToUFM block_assig dest
843 (freeregs',adjusted_assig))
844 joinToTargets block_live new_blocks instr dests
846 Just (freeregs,dest_assig)
847 | ufmToList dest_assig == ufmToList adjusted_assig
848 -> -- ok, the assignments match
849 joinToTargets block_live new_blocks instr dests
851 -> -- need fixup code
854 -- Construct a graph of register/spill movements and
855 -- untangle it component by component.
857 -- We cut some corners by
858 -- a) not handling cyclic components
859 -- b) not handling memory-to-memory moves.
861 -- Cyclic components seem to occur only very rarely,
862 -- and we don't need memory-to-memory moves because we
863 -- make sure that every temporary always gets its own
866 let graph = [ node | (vreg, src) <- ufmToList adjusted_assig,
867 node <- mkNodes src vreg ]
869 sccs = stronglyConnCompR graph
872 expandNode vreg src (lookupWithDefaultUFM_Directly
874 (panic "RegisterAlloc.joinToTargets")
877 -- The InBoth handling is a little tricky here. If
878 -- the destination is InBoth, then we must ensure that
879 -- the value ends up in both locations. An InBoth
880 -- destination must conflict with an InReg or InMem
881 -- source, so we expand an InBoth destination as
882 -- necessary. An InBoth source is slightly different:
883 -- we only care about the register that the source value
884 -- is in, so that we can move it to the destinations.
886 expandNode vreg loc@(InReg src) (InBoth dst mem)
887 | src == dst = [(vreg, loc, [InMem mem])]
888 | otherwise = [(vreg, loc, [InReg dst, InMem mem])]
889 expandNode vreg loc@(InMem src) (InBoth dst mem)
890 | src == mem = [(vreg, loc, [InReg dst])]
891 | otherwise = [(vreg, loc, [InReg dst, InMem mem])]
892 expandNode vreg loc@(InBoth _ src) (InMem dst)
893 | src == dst = [] -- guaranteed to be true
894 expandNode vreg loc@(InBoth src _) (InReg dst)
896 expandNode vreg loc@(InBoth src _) dst
897 = expandNode vreg (InReg src) dst
898 expandNode vreg src dst
900 | otherwise = [(vreg, src, [dst])]
902 -- we have eliminated any possibility of single-node cylces
903 -- in expandNode above.
904 handleComponent (AcyclicSCC (vreg,src,dsts))
905 = map (makeMove vreg src) dsts
906 handleComponent (CyclicSCC things)
907 = panic $ "Register Allocator: handleComponent: cyclic"
908 ++ " (workaround: use -fviaC)"
910 makeMove vreg (InReg src) (InReg dst)
911 = mkRegRegMoveInstr (RealReg src) (RealReg dst)
912 makeMove vreg (InMem src) (InReg dst)
913 = mkLoadInstr (RealReg dst) delta src
914 makeMove vreg (InReg src) (InMem dst)
915 = mkSpillInstr (RealReg src) delta dst
916 makeMove vreg src dst
917 = panic $ "makeMove " ++ show vreg ++ " (" ++ show src ++ ") ("
919 ++ " (workaround: use -fviaC)"
921 block_id <- getUniqueR
922 let block = BasicBlock (BlockId block_id) $
923 concatMap handleComponent sccs ++ mkBranchInstr dest
924 let instr' = patchJump instr dest (BlockId block_id)
925 joinToTargets block_live (block : new_blocks) instr' dests
927 live_set = lookItUp "joinToTargets" block_live dest
929 -- -----------------------------------------------------------------------------
930 -- The register allocator's monad.
932 -- Here we keep all the state that the register allocator keeps track
933 -- of as it walks the instructions in a basic block.
937 ra_blockassig :: BlockAssignment,
938 -- The current mapping from basic blocks to
939 -- the register assignments at the beginning of that block.
940 ra_freeregs :: {-#UNPACK#-}!FreeRegs, -- free machine registers
941 ra_assig :: RegMap Loc, -- assignment of temps to locations
942 ra_delta :: Int, -- current stack delta
943 ra_stack :: StackMap, -- free stack slots for spilling
944 ra_us :: UniqSupply -- unique supply for generating names
948 newtype RegM a = RegM { unReg :: RA_State -> (# RA_State, a #) }
950 instance Monad RegM where
951 m >>= k = RegM $ \s -> case unReg m s of { (# s, a #) -> unReg (k a) s }
952 return a = RegM $ \s -> (# s, a #)
954 runR :: BlockAssignment -> FreeRegs -> RegMap Loc -> StackMap -> UniqSupply
955 -> RegM a -> (BlockAssignment, StackMap, a)
956 runR block_assig freeregs assig stack us thing =
957 case unReg thing (RA_State{ ra_blockassig=block_assig, ra_freeregs=freeregs,
958 ra_assig=assig, ra_delta=0{-???-}, ra_stack=stack,
960 (# RA_State{ ra_blockassig=block_assig, ra_stack=stack' }, returned_thing #)
961 -> (block_assig, stack', returned_thing)
963 spillR :: Reg -> Unique -> RegM (Instr, Int)
964 spillR reg temp = RegM $ \ s@RA_State{ra_delta=delta, ra_stack=stack} ->
965 let (stack',slot) = getStackSlotFor stack temp
966 instr = mkSpillInstr reg delta slot
968 (# s{ra_stack=stack'}, (instr,slot) #)
970 loadR :: Reg -> Int -> RegM Instr
971 loadR reg slot = RegM $ \ s@RA_State{ra_delta=delta, ra_stack=stack} ->
972 (# s, mkLoadInstr reg delta slot #)
974 getFreeRegsR :: RegM FreeRegs
975 getFreeRegsR = RegM $ \ s@RA_State{ra_freeregs = freeregs} ->
978 setFreeRegsR :: FreeRegs -> RegM ()
979 setFreeRegsR regs = RegM $ \ s ->
980 (# s{ra_freeregs = regs}, () #)
982 getAssigR :: RegM (RegMap Loc)
983 getAssigR = RegM $ \ s@RA_State{ra_assig = assig} ->
986 setAssigR :: RegMap Loc -> RegM ()
987 setAssigR assig = RegM $ \ s ->
988 (# s{ra_assig=assig}, () #)
990 getStackR :: RegM StackMap
991 getStackR = RegM $ \ s@RA_State{ra_stack = stack} ->
994 setStackR :: StackMap -> RegM ()
995 setStackR stack = RegM $ \ s ->
996 (# s{ra_stack=stack}, () #)
998 getBlockAssigR :: RegM BlockAssignment
999 getBlockAssigR = RegM $ \ s@RA_State{ra_blockassig = assig} ->
1002 setBlockAssigR :: BlockAssignment -> RegM ()
1003 setBlockAssigR assig = RegM $ \ s ->
1004 (# s{ra_blockassig = assig}, () #)
1006 setDeltaR :: Int -> RegM ()
1007 setDeltaR n = RegM $ \ s ->
1008 (# s{ra_delta = n}, () #)
1010 getDeltaR :: RegM Int
1011 getDeltaR = RegM $ \s -> (# s, ra_delta s #)
1013 getUniqueR :: RegM Unique
1014 getUniqueR = RegM $ \s ->
1015 case splitUniqSupply (ra_us s) of
1016 (us1, us2) -> (# s{ra_us = us2}, uniqFromSupply us1 #)
1018 -- -----------------------------------------------------------------------------
1022 my_fromJust s p Nothing = pprPanic ("fromJust: " ++ s) p
1023 my_fromJust s p (Just x) = x
1025 my_fromJust _ _ = fromJust
1028 lookItUp :: Uniquable b => String -> UniqFM a -> b -> a
1029 lookItUp str fm x = my_fromJust str (ppr (getUnique x)) (lookupUFM fm x)