1 -----------------------------------------------------------------------------
3 -- Machine-dependent assembly language
5 -- (c) The University of Glasgow 1993-2004
7 -----------------------------------------------------------------------------
9 #include "HsVersions.h"
10 #include "nativeGen/NCG.h"
47 -- | Register or immediate
52 -- | Check if a RI represents a zero value.
54 -- - register %g0, which is always zero.
57 riZero (RIImm (ImmInt 0)) = True
58 riZero (RIImm (ImmInteger 0)) = True
59 riZero (RIReg (RealReg 0)) = True
63 -- | Calculate the effective address which would be used by the
64 -- corresponding fpRel sequence.
65 fpRelEA :: Int -> Reg -> Instr
67 = ADD False False fp (RIImm (ImmInt (n * wordLength))) dst
70 -- | Code to shift the stack pointer by n words.
71 moveSp :: Int -> Instr
73 = ADD False False sp (RIImm (ImmInt (n * wordLength))) sp
75 -- | An instruction that will cause the one after it never to be exectuted
76 isUnconditionalJump :: Instr -> Bool
77 isUnconditionalJump ii
87 -- | instance for sparc instruction set
88 instance Instruction Instr where
89 regUsageOfInstr = sparc_regUsageOfInstr
90 patchRegsOfInstr = sparc_patchRegsOfInstr
91 isJumpishInstr = sparc_isJumpishInstr
92 jumpDestsOfInstr = sparc_jumpDestsOfInstr
93 patchJumpInstr = sparc_patchJumpInstr
94 mkSpillInstr = sparc_mkSpillInstr
95 mkLoadInstr = sparc_mkLoadInstr
96 takeDeltaInstr = sparc_takeDeltaInstr
97 isMetaInstr = sparc_isMetaInstr
98 mkRegRegMoveInstr = sparc_mkRegRegMoveInstr
99 takeRegRegMoveInstr = sparc_takeRegRegMoveInstr
100 mkJumpInstr = sparc_mkJumpInstr
103 -- | SPARC instruction set.
104 -- Not complete. This is only the ones we need.
108 -- meta ops --------------------------------------------------
112 -- some static data spat out during code generation.
113 -- Will be extracted before pretty-printing.
114 | LDATA Section [CmmStatic]
116 -- Start a new basic block. Useful during codegen, removed later.
117 -- Preceding instruction should be a jump, as per the invariants
118 -- for a BasicBlock (see Cmm).
121 -- specify current stack offset for benefit of subsequent passes.
124 -- real instrs -----------------------------------------------
126 | LD Size AddrMode Reg -- size, src, dst
127 | ST Size Reg AddrMode -- size, src, dst
130 -- x: add/sub with carry bit.
131 -- In SPARC V9 addx and friends were renamed addc.
133 -- cc: modify condition codes
135 | ADD Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
136 | SUB Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
138 | UMUL Bool Reg RI Reg -- cc?, src1, src2, dst
139 | SMUL Bool Reg RI Reg -- cc?, src1, src2, dst
142 -- The SPARC divide instructions perform 64bit by 32bit division
143 -- The Y register is xored into the first operand.
145 -- On _some implementations_ the Y register is overwritten by
146 -- the remainder, so we have to make sure it is 0 each time.
148 -- dst <- ((Y `shiftL` 32) `or` src1) `div` src2
149 | UDIV Bool Reg RI Reg -- cc?, src1, src2, dst
150 | SDIV Bool Reg RI Reg -- cc?, src1, src2, dst
152 | RDY Reg -- move contents of Y register to reg
153 | WRY Reg Reg -- Y <- src1 `xor` src2
156 | AND Bool Reg RI Reg -- cc?, src1, src2, dst
157 | ANDN Bool Reg RI Reg -- cc?, src1, src2, dst
158 | OR Bool Reg RI Reg -- cc?, src1, src2, dst
159 | ORN Bool Reg RI Reg -- cc?, src1, src2, dst
160 | XOR Bool Reg RI Reg -- cc?, src1, src2, dst
161 | XNOR Bool Reg RI Reg -- cc?, src1, src2, dst
162 | SLL Reg RI Reg -- src1, src2, dst
163 | SRL Reg RI Reg -- src1, src2, dst
164 | SRA Reg RI Reg -- src1, src2, dst
167 | SETHI Imm Reg -- src, dst
170 -- Implemented by the assembler as SETHI 0, %g0, but worth an alias
174 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single
175 -- instructions right up until we spit them out.
177 | FABS Size Reg Reg -- src dst
178 | FADD Size Reg Reg Reg -- src1, src2, dst
179 | FCMP Bool Size Reg Reg -- exception?, src1, src2, dst
180 | FDIV Size Reg Reg Reg -- src1, src2, dst
181 | FMOV Size Reg Reg -- src, dst
182 | FMUL Size Reg Reg Reg -- src1, src2, dst
183 | FNEG Size Reg Reg -- src, dst
184 | FSQRT Size Reg Reg -- src, dst
185 | FSUB Size Reg Reg Reg -- src1, src2, dst
186 | FxTOy Size Size Reg Reg -- src, dst
189 | BI Cond Bool BlockId -- cond, annul?, target
190 | BF Cond Bool BlockId -- cond, annul?, target
192 | JMP AddrMode -- target
194 -- With a tabled jump we know all the possible destinations.
195 -- We also need this info so we can work out what regs are live across the jump.
197 | JMP_TBL AddrMode [BlockId]
199 | CALL (Either Imm Reg) Int Bool -- target, args, terminal
202 -- | regUsage returns the sets of src and destination registers used
203 -- by a particular instruction. Machine registers that are
204 -- pre-allocated to stgRegs are filtered out, because they are
205 -- uninteresting from a register allocation standpoint. (We wouldn't
206 -- want them to end up on the free list!) As far as we are concerned,
207 -- the fixed registers simply don't exist (for allocation purposes,
210 -- regUsage doesn't need to do any trickery for jumps and such. Just
211 -- state precisely the regs read and written by that insn. The
212 -- consequences of control flow transfers, as far as register
213 -- allocation goes, are taken care of by the register allocator.
215 sparc_regUsageOfInstr :: Instr -> RegUsage
216 sparc_regUsageOfInstr instr
218 LD _ addr reg -> usage (regAddr addr, [reg])
219 ST _ reg addr -> usage (reg : regAddr addr, [])
220 ADD _ _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
221 SUB _ _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
222 UMUL _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
223 SMUL _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
224 UDIV _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
225 SDIV _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
226 RDY rd -> usage ([], [rd])
227 WRY r1 r2 -> usage ([r1, r2], [])
228 AND _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
229 ANDN _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
230 OR _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
231 ORN _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
232 XOR _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
233 XNOR _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
234 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
235 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
236 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
237 SETHI _ reg -> usage ([], [reg])
238 FABS _ r1 r2 -> usage ([r1], [r2])
239 FADD _ r1 r2 r3 -> usage ([r1, r2], [r3])
240 FCMP _ _ r1 r2 -> usage ([r1, r2], [])
241 FDIV _ r1 r2 r3 -> usage ([r1, r2], [r3])
242 FMOV _ r1 r2 -> usage ([r1], [r2])
243 FMUL _ r1 r2 r3 -> usage ([r1, r2], [r3])
244 FNEG _ r1 r2 -> usage ([r1], [r2])
245 FSQRT _ r1 r2 -> usage ([r1], [r2])
246 FSUB _ r1 r2 r3 -> usage ([r1, r2], [r3])
247 FxTOy _ _ r1 r2 -> usage ([r1], [r2])
249 JMP addr -> usage (regAddr addr, [])
250 JMP_TBL addr _ -> usage (regAddr addr, [])
252 CALL (Left _ ) _ True -> noUsage
253 CALL (Left _ ) n False -> usage (argRegs n, callClobberedRegs)
254 CALL (Right reg) _ True -> usage ([reg], [])
255 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
260 = RU (filter interesting src) (filter interesting dst)
262 regAddr (AddrRegReg r1 r2) = [r1, r2]
263 regAddr (AddrRegImm r1 _) = [r1]
265 regRI (RIReg r) = [r]
269 -- | Interesting regs are virtuals, or ones that are allocatable
270 -- by the register allocator.
271 interesting :: Reg -> Bool
274 VirtualRegI _ -> True
275 VirtualRegHi _ -> True
276 VirtualRegF _ -> True
277 VirtualRegD _ -> True
278 RealReg i -> isFastTrue (freeReg i)
282 -- | Apply a given mapping to tall the register references in this instruction.
283 sparc_patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr
284 sparc_patchRegsOfInstr instr env = case instr of
285 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
286 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
288 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
289 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
290 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
291 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
292 UDIV cc r1 ar r2 -> UDIV cc (env r1) (fixRI ar) (env r2)
293 SDIV cc r1 ar r2 -> SDIV cc (env r1) (fixRI ar) (env r2)
294 RDY rd -> RDY (env rd)
295 WRY r1 r2 -> WRY (env r1) (env r2)
296 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
297 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
298 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
299 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
300 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
301 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
302 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
303 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
304 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
306 SETHI imm reg -> SETHI imm (env reg)
308 FABS s r1 r2 -> FABS s (env r1) (env r2)
309 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
310 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
311 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
312 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
313 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
314 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
315 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
316 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
317 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
319 JMP addr -> JMP (fixAddr addr)
320 JMP_TBL addr ids -> JMP_TBL (fixAddr addr) ids
322 CALL (Left i) n t -> CALL (Left i) n t
323 CALL (Right r) n t -> CALL (Right (env r)) n t
327 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
328 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
330 fixRI (RIReg r) = RIReg (env r)
334 --------------------------------------------------------------------------------
335 sparc_isJumpishInstr :: Instr -> Bool
336 sparc_isJumpishInstr instr
345 sparc_jumpDestsOfInstr :: Instr -> [BlockId]
346 sparc_jumpDestsOfInstr insn
354 sparc_patchJumpInstr :: Instr -> (BlockId -> BlockId) -> Instr
355 sparc_patchJumpInstr insn patchF
357 BI cc annul id -> BI cc annul (patchF id)
358 BF cc annul id -> BF cc annul (patchF id)
362 --------------------------------------------------------------------------------
363 -- | Make a spill instruction.
364 -- On SPARC we spill below frame pointer leaving 2 words/spill
366 :: Reg -- ^ register to spill
367 -> Int -- ^ current stack delta
368 -> Int -- ^ spill slot to use
371 sparc_mkSpillInstr reg _ slot
372 = let off = spillSlotToOffset slot
373 off_w = 1 + (off `div` 4)
374 sz = case regClass reg of
379 in ST sz reg (fpRel (negate off_w))
382 -- | Make a spill reload instruction.
384 :: Reg -- ^ register to load
385 -> Int -- ^ current stack delta
386 -> Int -- ^ spill slot to use
389 sparc_mkLoadInstr reg _ slot
390 = let off = spillSlotToOffset slot
391 off_w = 1 + (off `div` 4)
392 sz = case regClass reg of
397 in LD sz (fpRel (- off_w)) reg
400 --------------------------------------------------------------------------------
401 -- | See if this instruction is telling us the current C stack delta
406 sparc_takeDeltaInstr instr
416 sparc_isMetaInstr instr
425 -- | Make a reg-reg move instruction.
426 -- On SPARC v8 there are no instructions to move directly between
427 -- floating point and integer regs. If we need to do that then we
428 -- have to go via memory.
430 sparc_mkRegRegMoveInstr
435 sparc_mkRegRegMoveInstr src dst
436 = case regClass src of
437 RcInteger -> ADD False False src (RIReg g0) dst
438 RcDouble -> FMOV FF64 src dst
439 RcFloat -> FMOV FF32 src dst
442 -- | Check whether an instruction represents a reg-reg move.
443 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
444 -- by assigning the src and dest temporaries to the same real register.
446 sparc_takeRegRegMoveInstr :: Instr -> Maybe (Reg,Reg)
447 sparc_takeRegRegMoveInstr instr
449 ADD False False src (RIReg src2) dst
450 | g0 == src2 -> Just (src, dst)
452 FMOV FF64 src dst -> Just (src, dst)
453 FMOV FF32 src dst -> Just (src, dst)
457 -- | Make an unconditional branch instruction.
463 = [BI ALWAYS False id
464 , NOP] -- fill the branch delay slot.