1 -----------------------------------------------------------------------------
3 -- Machine-dependent assembly language
5 -- (c) The University of Glasgow 1993-2004
7 -----------------------------------------------------------------------------
9 #include "HsVersions.h"
10 #include "nativeGen/NCG.h"
46 -- | Register or immediate
51 -- | Check if a RI represents a zero value.
53 -- - register %g0, which is always zero.
56 riZero (RIImm (ImmInt 0)) = True
57 riZero (RIImm (ImmInteger 0)) = True
58 riZero (RIReg (RealReg 0)) = True
62 -- | Calculate the effective address which would be used by the
63 -- corresponding fpRel sequence.
64 fpRelEA :: Int -> Reg -> Instr
66 = ADD False False fp (RIImm (ImmInt (n * wordLength))) dst
69 -- | Code to shift the stack pointer by n words.
70 moveSp :: Int -> Instr
72 = ADD False False sp (RIImm (ImmInt (n * wordLength))) sp
74 -- | An instruction that will cause the one after it never to be exectuted
75 isUnconditionalJump :: Instr -> Bool
76 isUnconditionalJump ii
86 -- | instance for sparc instruction set
87 instance Instruction Instr where
88 regUsageOfInstr = sparc_regUsageOfInstr
89 patchRegsOfInstr = sparc_patchRegsOfInstr
90 isJumpishInstr = sparc_isJumpishInstr
91 jumpDestsOfInstr = sparc_jumpDestsOfInstr
92 patchJumpInstr = sparc_patchJumpInstr
93 mkSpillInstr = sparc_mkSpillInstr
94 mkLoadInstr = sparc_mkLoadInstr
95 takeDeltaInstr = sparc_takeDeltaInstr
96 isMetaInstr = sparc_isMetaInstr
97 mkRegRegMoveInstr = sparc_mkRegRegMoveInstr
98 takeRegRegMoveInstr = sparc_takeRegRegMoveInstr
99 mkJumpInstr = sparc_mkJumpInstr
102 -- | SPARC instruction set.
103 -- Not complete. This is only the ones we need.
107 -- meta ops --------------------------------------------------
111 -- some static data spat out during code generation.
112 -- Will be extracted before pretty-printing.
113 | LDATA Section [CmmStatic]
115 -- Start a new basic block. Useful during codegen, removed later.
116 -- Preceding instruction should be a jump, as per the invariants
117 -- for a BasicBlock (see Cmm).
120 -- specify current stack offset for benefit of subsequent passes.
123 -- real instrs -----------------------------------------------
125 | LD Size AddrMode Reg -- size, src, dst
126 | ST Size Reg AddrMode -- size, src, dst
129 -- x: add/sub with carry bit.
130 -- In SPARC V9 addx and friends were renamed addc.
132 -- cc: modify condition codes
134 | ADD Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
135 | SUB Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
137 | UMUL Bool Reg RI Reg -- cc?, src1, src2, dst
138 | SMUL Bool Reg RI Reg -- cc?, src1, src2, dst
141 -- The SPARC divide instructions perform 64bit by 32bit division
142 -- The Y register is xored into the first operand.
144 -- On _some implementations_ the Y register is overwritten by
145 -- the remainder, so we have to make sure it is 0 each time.
147 -- dst <- ((Y `shiftL` 32) `or` src1) `div` src2
148 | UDIV Bool Reg RI Reg -- cc?, src1, src2, dst
149 | SDIV Bool Reg RI Reg -- cc?, src1, src2, dst
151 | RDY Reg -- move contents of Y register to reg
152 | WRY Reg Reg -- Y <- src1 `xor` src2
155 | AND Bool Reg RI Reg -- cc?, src1, src2, dst
156 | ANDN Bool Reg RI Reg -- cc?, src1, src2, dst
157 | OR Bool Reg RI Reg -- cc?, src1, src2, dst
158 | ORN Bool Reg RI Reg -- cc?, src1, src2, dst
159 | XOR Bool Reg RI Reg -- cc?, src1, src2, dst
160 | XNOR Bool Reg RI Reg -- cc?, src1, src2, dst
161 | SLL Reg RI Reg -- src1, src2, dst
162 | SRL Reg RI Reg -- src1, src2, dst
163 | SRA Reg RI Reg -- src1, src2, dst
166 | SETHI Imm Reg -- src, dst
169 -- Implemented by the assembler as SETHI 0, %g0, but worth an alias
173 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single
174 -- instructions right up until we spit them out.
176 | FABS Size Reg Reg -- src dst
177 | FADD Size Reg Reg Reg -- src1, src2, dst
178 | FCMP Bool Size Reg Reg -- exception?, src1, src2, dst
179 | FDIV Size Reg Reg Reg -- src1, src2, dst
180 | FMOV Size Reg Reg -- src, dst
181 | FMUL Size Reg Reg Reg -- src1, src2, dst
182 | FNEG Size Reg Reg -- src, dst
183 | FSQRT Size Reg Reg -- src, dst
184 | FSUB Size Reg Reg Reg -- src1, src2, dst
185 | FxTOy Size Size Reg Reg -- src, dst
188 | BI Cond Bool BlockId -- cond, annul?, target
189 | BF Cond Bool BlockId -- cond, annul?, target
191 | JMP AddrMode -- target
193 -- With a tabled jump we know all the possible destinations.
194 -- We also need this info so we can work out what regs are live across the jump.
196 | JMP_TBL AddrMode [BlockId]
198 | CALL (Either Imm Reg) Int Bool -- target, args, terminal
201 -- | regUsage returns the sets of src and destination registers used
202 -- by a particular instruction. Machine registers that are
203 -- pre-allocated to stgRegs are filtered out, because they are
204 -- uninteresting from a register allocation standpoint. (We wouldn't
205 -- want them to end up on the free list!) As far as we are concerned,
206 -- the fixed registers simply don't exist (for allocation purposes,
209 -- regUsage doesn't need to do any trickery for jumps and such. Just
210 -- state precisely the regs read and written by that insn. The
211 -- consequences of control flow transfers, as far as register
212 -- allocation goes, are taken care of by the register allocator.
214 sparc_regUsageOfInstr :: Instr -> RegUsage
215 sparc_regUsageOfInstr instr
217 LD _ addr reg -> usage (regAddr addr, [reg])
218 ST _ reg addr -> usage (reg : regAddr addr, [])
219 ADD _ _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
220 SUB _ _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
221 UMUL _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
222 SMUL _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
223 UDIV _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
224 SDIV _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
225 RDY rd -> usage ([], [rd])
226 WRY r1 r2 -> usage ([r1, r2], [])
227 AND _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
228 ANDN _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
229 OR _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
230 ORN _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
231 XOR _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
232 XNOR _ r1 ar r2 -> usage (r1 : regRI ar, [r2])
233 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
234 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
235 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
236 SETHI _ reg -> usage ([], [reg])
237 FABS _ r1 r2 -> usage ([r1], [r2])
238 FADD _ r1 r2 r3 -> usage ([r1, r2], [r3])
239 FCMP _ _ r1 r2 -> usage ([r1, r2], [])
240 FDIV _ r1 r2 r3 -> usage ([r1, r2], [r3])
241 FMOV _ r1 r2 -> usage ([r1], [r2])
242 FMUL _ r1 r2 r3 -> usage ([r1, r2], [r3])
243 FNEG _ r1 r2 -> usage ([r1], [r2])
244 FSQRT _ r1 r2 -> usage ([r1], [r2])
245 FSUB _ r1 r2 r3 -> usage ([r1, r2], [r3])
246 FxTOy _ _ r1 r2 -> usage ([r1], [r2])
248 JMP addr -> usage (regAddr addr, [])
249 JMP_TBL addr _ -> usage (regAddr addr, [])
251 CALL (Left _ ) _ True -> noUsage
252 CALL (Left _ ) n False -> usage (argRegs n, callClobberedRegs)
253 CALL (Right reg) _ True -> usage ([reg], [])
254 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
259 = RU (filter interesting src) (filter interesting dst)
261 regAddr (AddrRegReg r1 r2) = [r1, r2]
262 regAddr (AddrRegImm r1 _) = [r1]
264 regRI (RIReg r) = [r]
268 -- | Interesting regs are virtuals, or ones that are allocatable
269 -- by the register allocator.
270 interesting :: Reg -> Bool
273 VirtualRegI _ -> True
274 VirtualRegHi _ -> True
275 VirtualRegF _ -> True
276 VirtualRegD _ -> True
277 RealReg i -> isFastTrue (freeReg i)
281 -- | Apply a given mapping to tall the register references in this instruction.
282 sparc_patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr
283 sparc_patchRegsOfInstr instr env = case instr of
284 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
285 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
287 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
288 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
289 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
290 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
291 UDIV cc r1 ar r2 -> UDIV cc (env r1) (fixRI ar) (env r2)
292 SDIV cc r1 ar r2 -> SDIV cc (env r1) (fixRI ar) (env r2)
293 RDY rd -> RDY (env rd)
294 WRY r1 r2 -> WRY (env r1) (env r2)
295 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
296 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
297 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
298 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
299 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
300 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
301 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
302 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
303 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
305 SETHI imm reg -> SETHI imm (env reg)
307 FABS s r1 r2 -> FABS s (env r1) (env r2)
308 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
309 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
310 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
311 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
312 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
313 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
314 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
315 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
316 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
318 JMP addr -> JMP (fixAddr addr)
319 JMP_TBL addr ids -> JMP_TBL (fixAddr addr) ids
321 CALL (Left i) n t -> CALL (Left i) n t
322 CALL (Right r) n t -> CALL (Right (env r)) n t
326 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
327 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
329 fixRI (RIReg r) = RIReg (env r)
333 --------------------------------------------------------------------------------
334 sparc_isJumpishInstr :: Instr -> Bool
335 sparc_isJumpishInstr instr
344 sparc_jumpDestsOfInstr :: Instr -> [BlockId]
345 sparc_jumpDestsOfInstr insn
353 sparc_patchJumpInstr :: Instr -> (BlockId -> BlockId) -> Instr
354 sparc_patchJumpInstr insn patchF
356 BI cc annul id -> BI cc annul (patchF id)
357 BF cc annul id -> BF cc annul (patchF id)
361 --------------------------------------------------------------------------------
362 -- | Make a spill instruction.
363 -- On SPARC we spill below frame pointer leaving 2 words/spill
365 :: Reg -- ^ register to spill
366 -> Int -- ^ current stack delta
367 -> Int -- ^ spill slot to use
370 sparc_mkSpillInstr reg _ slot
371 = let off = spillSlotToOffset slot
372 off_w = 1 + (off `div` 4)
373 sz = case regClass reg of
378 in ST sz reg (fpRel (negate off_w))
381 -- | Make a spill reload instruction.
383 :: Reg -- ^ register to load
384 -> Int -- ^ current stack delta
385 -> Int -- ^ spill slot to use
388 sparc_mkLoadInstr reg _ slot
389 = let off = spillSlotToOffset slot
390 off_w = 1 + (off `div` 4)
391 sz = case regClass reg of
396 in LD sz (fpRel (- off_w)) reg
399 --------------------------------------------------------------------------------
400 -- | See if this instruction is telling us the current C stack delta
405 sparc_takeDeltaInstr instr
415 sparc_isMetaInstr instr
424 -- | Make a reg-reg move instruction.
425 -- On SPARC v8 there are no instructions to move directly between
426 -- floating point and integer regs. If we need to do that then we
427 -- have to go via memory.
429 sparc_mkRegRegMoveInstr
434 sparc_mkRegRegMoveInstr src dst
435 = case regClass src of
436 RcInteger -> ADD False False src (RIReg g0) dst
437 RcDouble -> FMOV FF64 src dst
438 RcFloat -> FMOV FF32 src dst
441 -- | Check whether an instruction represents a reg-reg move.
442 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
443 -- by assigning the src and dest temporaries to the same real register.
445 sparc_takeRegRegMoveInstr :: Instr -> Maybe (Reg,Reg)
446 sparc_takeRegRegMoveInstr instr
448 ADD False False src (RIReg src2) dst
449 | g0 == src2 -> Just (src, dst)
451 FMOV FF64 src dst -> Just (src, dst)
452 FMOV FF32 src dst -> Just (src, dst)
456 -- | Make an unconditional branch instruction.
462 = [BI ALWAYS False id
463 , NOP] -- fill the branch delay slot.