3 This document describes the correlation between publicly documented
4 logic, I/O, and routing resources within the Atmel AT40k/94k family
5 of chips and bits in the bitstreams needed to program them.
7 Our goal is to make this information available to the public without
8 restriction on its use, for the purpose of creating automated tools
9 which generate bitstreams.
12 Statement of Public Knowledge
14 The Knowledge encapsulated in this document was derived by formal
15 scientific experimentation, using only information generally
16 available to the public. Extreme care which has been taken to
17 ensure that the process did not violate any copyright, trademark,
18 trade secret, or patent statutes. No licensing contracts or
19 non-disclosure agreements were entered into by the parties involved
20 in this endeavor, nor did they have access to any confidential
23 This document is part of the Public Domain; its authors surrender
24 claim to copyright on it.
29 If you find errors in this document, please correct them and add the
30 date and a short description of the correction to the table below.
31 This will assist in merging changes made in disjoint derivitaves.
33 2005.08.12 [gosset] Initial revision
34 2006.03.12 [megacz] Swapped {L1,L0}->W, FB->{L0,L1}, {H0->L0,H1->L1}
38 The Atmel AT40k Datasheet describes in great detail the resources
39 available in the AT40k as well as the FPGA portion of the AT94k
40 (which is functionally identical and uses the same binary
41 configuration format).
43 The configuration space used to control these resources consists of
44 a collection of independent octets arranged in a sparse 24-bit
45 address space. This document correlates those bits with the
46 resources described in the Datasheet.
48 The process of configuring the device consists of writing these
49 octets into the configuration memory. Once the desired
50 configuration octets are known, the procedures for loading them into
51 configuration memory are well documented in Atmel Documents 1009 and
54 Each data octet "D" has a 24-bit address, divided into three address
55 octets "X", "Y", and "Z". In general, the X and Y address octets
56 are related to the physical position of the resource, while the Z
57 octet is related to the type of resource being addressed.
61 We will use the notation A->B to indicate that setting the
62 corresponding configuration bit high causes source A to drive wire
63 B, and the notation A<>B to indicate that a pass gate between A and
64 B is enabled. The notation ~A or ~A->B indicates a configuration
65 bit controlling A or causing A to drive B is *active low*
68 We will use the following terms to describe routing resources.
69 They vary slightly from Atmel's documentation, but are less
72 X, Y, W, Z The cell's inputs
73 XO, YO The X and Y outputs from the cell (to its neighbors)
74 N, S, E, W Orthogonal lines: connections to neighboring cells
75 NE,SE,NW,SW Diagonal lines: connections to neighboring cells
76 S0..S4 Quad lines: four-cell long routing lines
77 H0..H4 Horizontal quad lines
78 V0..V4 Vertical quad lines
79 L0..L4 Switchbox ports: the wires joining FB,H0..H4,V0..V4,X,Y,Z,W
80 G0a..G4b Global lines: eight-cell long routing lines, in two sets (a+b)
81 FB The cell's internal feedback line
82 R The cell's internal register
83 C The cell's "center" output; can drive the X or Y outputs
84 ZM The "Z-mux"; the mux which drives the cell's register input
85 WM The "W-mux"; the mux which drives the third input to the LUTs
86 XL, YL The output of the X,Y-LUTs
87 IA The "internal and" gate (W & Z)
92 Although the exact interpretation of the X and Y octets depends on
93 the resource type (Z octet), in most cases the X and Y octets are
94 the cartesian coordinates of the logic cell nearest to the desired
95 resource (0,0 is the lower-left hand logic cell). This section
96 describes the significance of the Z and D octets for such resources.
99 - The most significant four bits of the Z octet are 0000 for these bits
100 - If WZ->WM and FB->WM are both low, then W->WM.
101 - If ZM->R and YL->R are both low, then the XL->R
102 - The ZM->C and ZM->FB bits are used to bypass the register (when high).
103 - ~SET bit controls the set/reset behavior of the register; 0=set, 1=reset
105 +----+--------+--------+--------+--------+--------+--------+--------+--------+
107 +----+--------+--------+--------+--------+--------+--------+--------+--------+
108 |0000| V4->L4 | H4->L4 | FB->L2 | FB->L3 | FB->L0 | FB->L1 | FB->L4 | 0 |
109 +----+--------+--------+--------+--------+--------+--------+--------+--------+
110 |0001| ZM->R | YL->R | WZ->WM | FB->WM | ZM->C | ZM->FB | C->XO | C->YO |
111 +----+--------+--------+--------+--------+--------+--------+--------+--------+
112 |0010| L4->Z | L4->Y | L3->Z | L2->Z | L1->Z | L0->Z | V4->OE | H4->OE |
113 +----+--------+--------+--------+--------+--------+--------+--------+--------+
114 |0011| L2->W | L3->W | L4->W | L4->X | L0->W | L1->W |H2a<>V2a|H3b<>V3b|
115 +----+--------+--------+--------+--------+--------+--------+--------+--------+
116 |0100| N->Y | S->Y | W->Y | E->Y | L3->Y | L2->Y | L1->Y | L0->Y |
117 +----+--------+--------+--------+--------+--------+--------+--------+--------+
118 |0101| SW->X | NE->X | SE->X | NW->X | L3->X | L2->X | L1->X | L0->X |
119 +----+--------+--------+--------+--------+--------+--------+--------+--------+
120 |0110| X-LUT truth table, inverted |
121 +----+--------+--------+--------+--------+--------+--------+--------+--------+
122 |0111| Y-LUT truth table, inverted |
123 +----+--------+--------+--------+--------+--------+--------+--------+--------+
124 |1000| V3->L3 | H3->L3 | H2->L2 | V2->L2 | V1->L1 | H0->L0 | V0->L0 | H1->L1 |
125 +----+--------+--------+--------+--------+--------+--------+--------+--------+
126 |1001|H1a<>V1a|H0a<>V0a|H0b<>V0b|H4a<>V4a|H4b<>V4b|H1b<>V1b|H3a<>V3a|H2b<>V2b|
127 +----+--------+--------+--------+--------+--------+--------+--------+--------+
129 +----+--------+--------+--------+--------+--------+--------+--------+--------+
130 |0001| 1 | 1 | 1 | 1 | ~SET | 1 | 1 | 1 |
131 +----+--------+--------+--------+--------+--------+--------+--------+--------+
136 Clocking, reset, and inter-sector repeaters are resources which are
137 not specific to a particular cell. As such, their X,Y addressing is
138 slightly different. These resources are addressed by the cartesian
139 coordinates of the cell above or to the right of the resource, with
140 an additional twist: for resources in vertical channels, the
141 X-coordinate is shifted right by two bits (divided by four); for
142 resources in horizontal channels, the Y-coordinate is shifted right
143 by two bits (divided by four).
145 The most significant three bits of the Z-octet for a sector resource
146 are set to 001; the next bit (fourth most significant) is set to 0
147 for horizontal channels and 1 for vertical channels.
149 One sector wire and one global wire enter each side of each
150 repeater, for a total of four connections. Each connection has an
151 associated four-bit code which indicates if that connection is
152 driven by the repeater, and if so, which connection to the repeater
155 000 - driver disabled
156 100 - source is global wire on the other side of the repeater
157 010 - source is sector wire on the other side of the repeater
158 001 - source is other connection on the same side of the repeater
160 Example: a code of 001 for the left-hand side sector wire driver
161 means that the source of the driver should be the left hand side
162 global wire. A code of 010 for the top sector wire driver means that
163 the source of the driver should be the bottom sector wire.
168 CC+ = sector clock of the sector below this one
169 InvSC = invert the clock source (CC or S4) before driving SC
171 +----------+--------+--------+-----+-----+------+-----+-----+------+
172 | Z octet | D octet |
173 +----------+--------+--------+-----+-----+------+-----+-----+------+
174 | 001_0000 | 1 | 0 | Left/Top G4 | Left/Top S4 |
175 +----------+--------+--------+-----+-----+------+-----+-----+------+
176 | 001_0001 | 0 | S4->CR | Right/Bottom G4 | Right/Bottom S4 |
177 +----------+--------+--------+-----+-----+------+-----+-----+------+
178 | 001_0010 | 1 | 0 | Left/Top G3 | Left/Top S3 |
179 +----------+--------+--------+-----+-----+------+-----+-----+------+
180 | 001_0011 | 1 | 1 | Right/Bottom G3 | Right/Bottom S3 |
181 +----------+--------+--------+-----+-----+------+-----+-----+------+
182 | 001_0100 | 1 | 0 | Left/Top G2 | Left/Top S2 |
183 +----------+--------+--------+-----+-----+------+-----+-----+------+
184 | 001_0101 | SC->CC+| S3->SC | Right/Bottom G2 | Right/Bottom S2 |
185 +----------+--------+--------+-----+-----+------+-----+-----+------+
186 | 001_0110 | 1 | 0 | Left/Top G1 | Left/Top S1 |
187 +----------+--------+--------+-----+-----+------+-----+-----+------+
188 | 001_0111 | 1 | 1 | Right/Bottom G1 | Right/Bottom S1 |
189 +----------+--------+--------+-----+-----+------+-----+-----+------+
190 | 001_1000 | 1 | 0 | Left/Top G0 | Left/Top S0 |
191 +----------+--------+--------+-----+-----+------+-----+-----+------+
192 | 001_1001 | InvSC |~SC->CC+| Right/Bottom G0 | Right/Bottom S0 |
193 +----------+--------+--------+----+--------+----+-----+--------+---+
198 Although block memories are shown in the lower right hand corner of
199 each sector in the Atmel Datasheets, they are conceptually addressed
200 by the cartesian coordinate of the cell in the lower *left* hand
201 corner of the sector. Furthermore, both coordinates are shifted
202 right two bits (divided by four).
204 The significance of the "D" octet for a given block memory depends
205 on its position; if it falls in an odd sector-column (4-7, 12-15,
206 etc), use the first chart; otherwise, use the second chart.
208 USECLK = the memory is synchronous
209 ENABLE = the memory is enabled
210 DUAL = enable both ports on a dual-ported memory
214 +--------+------+------+------+------+--------+--------+--------+---------+
216 +--------+------+------+------+------+--------+---------+--------+--------+
217 |01000000| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
218 +--------+------+------+------+------+--------+---------+--------+--------+
219 |01000001| 1 | 1 | 1 | 1 | USECLK | ~ENABLE | ENABLE | ENABLE |
220 +--------+------+------+------+------+--------+---------+--------+--------+
224 +--------+------+------+------+------+--------+--------+--------+--------+
226 +--------+------+------+------+------+--------+--------+--------+--------+
227 |01000000| 1 | 1 | 1 | 1 | USECLK | DUAL | ~DUAL | ENABLE |
228 +--------+------+------+------+------+--------+--------+--------+--------+
229 |01000001| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
230 +--------+------+------+------+------+--------+--------+--------+--------+
235 The Z octet for I/O resources always its most significant three bits
236 set to 011. The next two bits are either 01 for a primary IOB or 10
239 S = Sector wires of this cell
240 S+ = Sector wires of next cell
241 S- = Sector wires of previous cell
242 G = Global wires of this cell
243 G+ = Global wires of next cell
244 Output = Allow output from this IOB
245 OE = when low, output is always enabled
246 OEM = 7 bits, one-hot encoded, chooses input to output-enable mux
247 USEOEM = when low, ignore the output enable mux
248 Delay = amount of delay to add; can be 0, 1, 3, or 5
249 Slew = slew time: 11=fast, 10=med, 01=slow
250 Pull = 00=pullup, 11=pulldown, 01=none
252 +--------+--------+--------+------+-------+-------+--------+--------+--------+
254 +--------+--------+--------+------+-------+-------+--------+--------+--------+
255 |011__000| Schmit | Slew |~G2->CR| | Pull | |
256 +--------+--------+--------+------+-------+-------+--------+--------+--------+
257 |011__001|REG->OUT| | OE | Output Mux |
258 +--------+--------+--------+------+-------+-------+--------+--------+--------+
259 |011_0010| Added Delay (primary) |PRI->S-| PRI->G+| PRI->G | PRI->S |
260 +--------+--------+--------+------+-------+-------+--------+--------+--------+
261 |011_1010| Added Delay (secondary) |SND->S | SND->S+|PRI->REG|SND->REG|
262 +--------+--------+--------+------+-------+-------+--------+--------+--------+
263 |011__011| OEM | USEOEM | OEM |
264 +--------+--------+--------+------+-------+-------+--------+--------+--------+
267 Global Clock/Reset Networks
269 To drive a column clock from one of the eight global clock/reset
270 networks, set the corresponding bit in the desired column:
272 +--------+--------+--------+
273 |Z octet |X octet |Y octet |
274 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
275 |10100000| column |00000000| CK1 | CK2 | CK3 | CK4 | CK5 | CK6 | CK7 | CK8 |
276 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
280 The following configuration resources are not fully understood, but
281 the values below appear to work.
283 +--------+--------+--------+
284 |Z octet |X octet |Y octet |
285 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
286 | |00000000|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
287 |10100001|00010111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
288 | |00101111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
289 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
290 |11010000|00000000|00000000| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
291 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
292 |11010011|00000000|00000000| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
293 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+