electric/tinyCounter.jelib

   1 # header information:
   2 HtinyCounter|8.08k
   3
   4 # Views:
   5 Vicon|ic
   6 Vschematic|sch
   7
   8 # External Libraries:
   9
  10 LcentersJ|centersJ
  11
  12 LdriversM|driversM
  13
  14 LorangeTSMC090nm|orangeTSMC090nm
  15
  16 LredFive|redFive
  17
  18 # Tools:
  19 Ouser|DefaultTechnology()Scmos90|SchematicTechnology()Scmos90
  20 Oio|GDSOutputConvertsBracketsInExports()BF|GDSWritesExportPins()BT
  21
  22 # Technologies:
  23 Tcmos90|"GDS(ST)LayerForPad-FrameINcmos90"()S43|"GDS(TSMC)LayerForPad-FrameINcmos90"()S43
  24 Tmocmos|SelectedFoundryFormocmos()STSMC
  25
  26 # Cell counterTopLevel;1{sch}
  27 CcounterTopLevel;1{sch}||schematic|1246318914852|1246318917028|
  28 Ngeneric:Facet-Center|art@0||0|0||||AV
  29 Ngeneric:Invisible-Pin|pin@0||-5|9.5|||||ART_message(D5G3;)S["A complete counter consists of \"n\" copies of this cell","plus an \"end cap\" at the MSB end and a different \"end cap\" at the LSB end.",.,The MSB end cap ties DoneOrTwo HI and OneOrTwo LO.,.,The LSB end cap responds to decrement requests from the,"dock by draining both state wires.  It reports \"decrement succeeded\" to","the dock if the state of the LSB is \"One\" or \"Two\" and reports \"decrement","failed\" to the dock if the state of the LSB is \"Done\"."]
  30 X
  31
  32 # Cell nor2withInverter;2{ic}
  33 Cnor2withInverter;2{ic}||artwork|1021415734000|1246318194856|E|ATTR_Delay(D5G1;HNPX-2.5;Y5.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-2.5;Y6.5;)S1|ATTR_drive0(D5G1;HNPTX-2.5;Y4.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-2.5;Y3.5;)Sstrong1|prototype_center()I[6000,0]
  34 Ngeneric:Facet-Center|art@0||0|0||||AV
  35 NThick-Circle|art@1||-1|1|1|1|||ART_color()I10
  36 NThick-Circle|art@2||0.5|0|4|4|RRR||ART_color()I10|ART_degrees()F[0.0,3.1415927]
  37 NThick-Circle|art@4||-3|-1|1|1|||ART_color()I10
  38 NPin|pin@0||-0.5|-0.75|1|1||
  39 NPin|pin@1||0.75|-2|1|1||
  40 NPin|pin@2||0.5|-2|1|1||
  41 NPin|pin@3||-0.5|-2|1|1||
  42 NPin|pin@4||-0.5|2|1|1||
  43 NPin|pin@5||0.5|2|1|1||
  44 NPin|pin@6||-1.5|1|1|1||
  45 NPin|pin@7||-2.5|1||||
  46 Nschematic:Bus_Pin|pin@8||3.5|0|-2|-2||
  47 Nschematic:Bus_Pin|pin@9||-2.5|1|-2|-2||
  48 Nschematic:Bus_Pin|pin@12||-7|-1|-2|-2||
  49 NPin|pin@13||-3.5|-1|1|1||
  50 Nschematic:Bus_Pin|pin@14||-7|-1|-2|-2||
  51 NPin|pin@15||-6|-1|1|1||
  52 NPin|pin@16||-7|-1||||
  53 Nschematic:Bus_Pin|pin@17||-2.5|-1|-2|-2||
  54 NPin|pin@18||-6|0.5|1|1||
  55 NPin|pin@19||-6|-2.5|1|1||
  56 NPin|pin@20||-2.5|-1|1|1||
  57 NPin|pin@21||-0.5|-1|1|1||
  58 NPin|pin@22||-1.5|-3|1|1|R|
  59 NPin|pin@23||-1.5|-1|1|1|R|
  60 Nschematic:Wire_Pin|pin@24||-1.5|-3||||
  61 NPin|pin@25||3.5|0|1|1||
  62 NPin|pin@26||2.5|0||||
  63 AThicker|net@0|||FS3150|pin@1||0.75|-2|pin@0||-0.5|-0.75|ART_color()I10
  64 AThicker|net@1|||FS0|pin@2||0.5|-2|pin@3||-0.5|-2|ART_color()I10
  65 AThicker|net@2|||FS2700|pin@3||-0.5|-2|pin@4||-0.5|2|ART_color()I10
  66 AThicker|net@3|||FS0|pin@5||0.5|2|pin@4||-0.5|2|ART_color()I10
  67 AThicker|net@4|||FS0|pin@6||-1.5|1|pin@7||-2.5|1|ART_color()I10
  68 AThicker|net@6|||FS3290|pin@13||-3.5|-1|pin@18||-6|0.5|ART_color()I10
  69 AThicker|net@7|||FS310|pin@13||-3.5|-1|pin@19||-6|-2.5|ART_color()I10
  70 AThicker|net@8|||FS0|pin@15||-6|-1|pin@16||-7|-1|ART_color()I10
  71 AThicker|net@9|||FS2700|pin@19||-6|-2.5|pin@18||-6|0.5|ART_color()I10
  72 AThicker|net@10|||FS1800|pin@20||-2.5|-1|pin@21||-0.5|-1|ART_color()I-16777215
  73 AThicker|net@11|||FS2700|pin@22||-1.5|-3|pin@23||-1.5|-1|ART_color()I-16777215
  74 AThicker|net@12|||FS0|pin@25||3.5|0|pin@26||2.5|0|ART_color()I10
  75 Eina||D5G1;X1.5;|pin@12||I
  76 Einb||D5G1;|pin@9||I
  77 Eout||D5G1;|pin@8||O
  78 EoutaBar||D5G1;Y-0.5;|pin@24||U
  79 X
  80
  81 # Cell nor2withInverter;1{sch}
  82 Cnor2withInverter;1{sch}||schematic|1021415734000|1246318014836||ATTR_Delay(D5G1;HNPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-7;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-8;)Sstrong1|ATTR_verilog_template(D5G1;NTX5.5;Y-18.5;)SFIXME!!! nor ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
  83 IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||-4|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  84 IorangeTSMC090nm:NMOSx;1{ic}|NMOS@1||4|-8|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  85 IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@0||-3|11.5|Y||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  86 IredFive:PMOS;1{ic}|PMOS@0||0|20.5|||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
  87 IredFive:PMOS;1{ic}|PMOS@1||0|4|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
  88 Ngeneric:Facet-Center|art@0||0|0||||AV
  89 NOff-Page|conn@0||-15.5|0||||
  90 NOff-Page|conn@1||14|-8|||RR|
  91 NOff-Page|conn@2||14|0||||
  92 NOff-Page|conn@3||14|15||||
  93 NGround|gnd@0||0|-15||||
  94 NGround|gnd@1||-3|5.5||||
  95 Inor2withInverter;2{ic}|nor2with@0||33.5|16|||D5G4;|ATTR_Delay(D5G1;NPX-5.25;Y-4;)I100|ATTR_X(D5FLeave alone;G1;NOLPX-5.25;Y-3;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  96 NWire_Pin|pin@0||0|-11.5||||
  97 NWire_Pin|pin@1||-4|-11.5||||
  98 NWire_Pin|pin@2||4|-11.5||||
  99 NWire_Pin|pin@3||-9|-8||||
 100 NWire_Pin|pin@5||-9|0||||
 101 NWire_Pin|pin@6||9|4||||
 102 NWire_Pin|pin@7||9|-8||||
 103 Ngeneric:Invisible-Pin|pin@8||3|28.5|||||ART_message(D5G6;)Snor2withInverters
 104 NWire_Pin|pin@9||-9|20.5||||
 105 NWire_Pin|pin@10||0|0||||
 106 NWire_Pin|pin@11||4|0||||
 107 NWire_Pin|pin@12||-4|0||||
 108 Ngeneric:Invisible-Pin|pin@13||27|-14|||||ART_message(D5G2;)S[X is drive strength,One pull-down is as strong,as the pull-up]
 109 NWire_Pin|pin@14||-3|20.5||||
 110 NWire_Pin|pin@15||3|4||||
 111 NWire_Pin|pin@16||0|2||||
 112 NWire_Pin|pin@17||-9|11.5||||
 113 NWire_Pin|pin@18||-3|15||||
 114 NWire_Pin|pin@19||0|15||||
 115 NPower|pwr@0||0|25||||
 116 Awire|net@0|||0|pin@7||9|-8|NMOS@1|g|7|-8
 117 Awire|net@1|||900|pin@0||0|-11.5|gnd@0||0|-13
 118 Awire|net@2|||0|pin@2||4|-11.5|pin@0||0|-11.5
 119 Awire|net@3|||0|pin@0||0|-11.5|pin@1||-4|-11.5
 120 Awire|net@4|||900|NMOS@0|s|-4|-10|pin@1||-4|-11.5
 121 Awire|net@5|||2700|pin@2||4|-11.5|NMOS@1|s|4|-10
 122 Awire|net@6|||900|pin@12||-4|0|NMOS@0|d|-4|-6
 123 Awire|net@7|||0|NMOS@0|g|-7|-8|pin@3||-9|-8
 124 Awire|net@8|||900|pin@11||4|0|NMOS@1|d|4|-6
 125 Awire|net@9|||2700|pin@3||-9|-8|pin@5||-9|0
 126 Awire|net@10|||0|pin@5||-9|0|conn@0|y|-13.5|0
 127 Awire|net@11|||2700|pin@7||9|-8|pin@6||9|4
 128 Awire|net@12|||1800|pin@7||9|-8|conn@1|y|12|-8
 129 Awire|net@16|||0|pin@11||4|0|pin@10||0|0
 130 Awire|net@17|||0|pin@10||0|0|pin@12||-4|0
 131 Awire|net@18|||2700|pin@5||-9|0|pin@17||-9|11.5
 132 Awire|net@19|||1800|pin@11||4|0|conn@2|a|12|0
 133 Awire|net@20|||1800|pin@9||-9|20.5|pin@14||-3|20.5
 134 Awire|net@21|||0|pin@6||9|4|pin@15||3|4
 135 Awire|net@22|||2700|pin@10||0|0|pin@16||0|2
 136 Awire|net@23|||0|PMOS@0|g|-3|20.5|pin@14||-3|20.5
 137 Awire|net@24|||900|pwr@0||0|25|PMOS@0|s|0|22.5
 138 Awire|net@25|||2700|PMOS@1|s|0|2|pin@16||0|2
 139 Awire|net@26|||1800|PMOS@1|g|3|4|pin@15||3|4
 140 Awire|net@27|||2700|PMOS@1|d|0|6|pin@19||0|15
 141 Awire|net@28|||2700|pin@17||-9|11.5|pin@9||-9|20.5
 142 Awire|net@29|||0|NMOSx@0|g|-6|11.5|pin@17||-9|11.5
 143 Awire|net@30|||2700|NMOSx@0|s|-3|13.5|pin@18||-3|15
 144 Awire|net@31|||2700|pin@19||0|15|PMOS@0|d|0|18.5
 145 Awire|net@32|||1800|pin@18||-3|15|pin@19||0|15
 146 Awire|net@33|||0|conn@3|a|12|15|pin@19||0|15
 147 Awire|net@34|||2700|gnd@1||-3|7.5|NMOSx@0|d|-3|9.5
 148 Eina||D5G2;|conn@0|a|I
 149 Einb||D5G2;|conn@1|a|I
 150 Eout||D5G2;|conn@2|y|O
 151 EoutaBar||D5G2;X7.5;|conn@3|a|U
 152 X
 153
 154 # Cell oneBit;1{ic}
 155 ConeBit;1{ic}||artwork|1242937501096|1246320313399|E
 156 Ngeneric:Facet-Center|art@0||0|0||||AV
 157 NTriangle|art@2||-5|2|3|2|RRR|
 158 NTriangle|art@3||3|-8|3|2|R|
 159 NTriangle|art@4||3|2|3|2|R|
 160 NPin|pin@0||-6|4|1|1||
 161 NPin|pin@1||-6|-10|1|1||
 162 NPin|pin@2||4|-10|1|1||
 163 NPin|pin@3||4|4|1|1||
 164 Nschematic:Wire_Pin|pin@9||-6|2||||
 165 Nschematic:Wire_Pin|pin@16||4|2||||
 166 Nschematic:Wire_Pin|pin@17||4|-8||||
 167 Nschematic:Wire_Pin|pin@18||-6|-8||||
 168 Nschematic:Wire_Pin|pin@19||-1|-10||||
 169 NPin|pin@20||-6|-8|1|1||
 170 Nschematic:Bus_Pin|pin@21||-6|-3||||
 171 Nschematic:Wire_Pin|pin@22||-4|-3||||
 172 Nschematic:Bus_Pin|pin@23||5|-7||||
 173 Nschematic:Wire_Pin|pin@24||3|-7||||
 174 Nschematic:Bus_Pin|pin@25||6|-6||||
 175 Nschematic:Wire_Pin|pin@26||4|-6||||
 176 Nschematic:Bus_Pin|pin@27||7|-8||||
 177 Nschematic:Wire_Pin|pin@28||5|-8||||
 178 ASolid|net@0|||FS900|pin@0||-6|4|pin@1||-6|-10
 179 ASolid|net@1|||FS1800|pin@1||-6|-10|pin@2||4|-10
 180 ASolid|net@2|||FS2700|pin@2||4|-10|pin@3||4|4
 181 ASolid|net@3|||FS0|pin@3||4|4|pin@0||-6|4
 182 Aschematic:wire|net@4|||0|pin@22||-4|-3|pin@21||-6|-3
 183 Aschematic:wire|net@5|||1800|pin@24||3|-7|pin@23||5|-7
 184 Aschematic:wire|net@6|||1800|pin@26||4|-6|pin@25||6|-6
 185 Aschematic:wire|net@7|||1800|pin@28||5|-8|pin@27||7|-8
 186 Eload||D5G2;|pin@27||U
 187 EloadBar||D5G2;|pin@25||U
 188 EloadVal|loadValBar|D5G2;|pin@23||U
 189 Eload_or_master_clear||D5G2;|pin@21||U
 190 Emc||D5G1;Y-1;|pin@19||I
 191 Epred[TwoOrEmpty]|pred[DoneOrTwo]|D4G1;X-1;|pin@9||B
 192 Epred[OneOrTwo]||D4G1;X-1;|pin@18||B
 193 Esucc[TwoOrEmpty]|succ[DoneOrTwo]|D6G1;X1;|pin@16||B
 194 Esucc[OneOrTwo]||D5G1;X2;|pin@17||B
 195 X
 196
 197 # Cell oneBit;1{sch}
 198 ConeBit;1{sch}||schematic|1242942044308|1246321007881|
 199 IredFive:NMOS;1{ic}|NMOS@1||68.5|31|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
 200 IredFive:NMOS;1{ic}|NMOS@2||68.5|25.5|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
 201 IredFive:PMOS;1{ic}|PMOS@0||68.5|38|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
 202 IredFive:PMOS;1{ic}|PMOS@1||68.5|43|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
 203 Ngeneric:Facet-Center|art@0||0|0||||AV
 204 NOff-Page|conn@0||33.5|3||||
 205 NOff-Page|conn@1||-48|1|||RR|
 206 NOff-Page|conn@2||-48|69||||
 207 NOff-Page|conn@3||34|68||||
 208 NOff-Page|conn@6||-48|76||||
 209 NOff-Page|conn@7||82|34.5|||RR|
 210 NOff-Page|conn@8||82|43|||RR|
 211 NOff-Page|conn@9||82|25.5|||RR|
 212 IcentersJ:ctrAND4in30;2{ic}|ctrAND4i@0||-1.5|58.5|R||D5G4;
 213 NGround|gnd@0||68.5|21||||
 214 Inor2withInverter;2{ic}|nor2with@0||-13.5|35.5|||D5G4;|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 215 Ngeneric:Invisible-Pin|pin@6||-74|129.5|||||ART_message(D5G15;)SoneBit
 216 NWire_Pin|pin@115||-42|1||||
 217 NWire_Pin|pin@120||-40.5|69||||
 218 NWire_Pin|pin@127||29|34.5||||
 219 NWire_Pin|pin@128||29|3||||
 220 NWire_Pin|pin@129||29|68||||
 221 NWire_Pin|pin@130||29|36.5||||
 222 Ngeneric:Invisible-Pin|pin@149||-74.5|119|||||ART_message(D5G2;)Sam 29 Jun 2009
 223 Ngeneric:Invisible-Pin|pin@162||-10.5|110.5|||||ART_message(D5G3;)S[Each bit of the counter has four states:,"Zero, One, Two, Done",.,These states are encoded by two state wires:,"DoneOrTwo is HI if the state is \"Done\" or \"Two\"","OneOrTwo is HI if the state is \"One\" or \"Two\""]
 224 NWire_Pin|pin@163||5|68||||
 225 NWire_Pin|pin@165||18.5|36.5||||
 226 NWire_Pin|pin@167||18|34.5||||
 227 NWire_Pin|pin@178||-3.5|35.5||||
 228 NWire_Pin|pin@179||-40.5|34.5||||
 229 NWire_Pin|pin@180||-42|36.5||||
 230 NWire_Pin|pin@181||0.5|34.5||||
 231 NWire_Pin|pin@182||2.5|36.5||||
 232 Ngeneric:Invisible-Pin|pin@194||-69|55|||||ART_message(D5G4;)SMSB to the Left
 233 Ngeneric:Invisible-Pin|pin@195||53|53.5|||||ART_message(D5G4;)SLSB to the Right
 234 Ngeneric:Invisible-Pin|pin@196||-73.5|121.5|||||ART_message(D5G2;)S"this GasP module sits \"between\" two bits"
 235 NWire_Pin|pin@206||-5.5|48.5||||
 236 NWire_Pin|pin@214||-5|35.5||||
 237 NWire_Pin|pin@218||-15|28.5||||
 238 NWire_Pin|pin@219||-23|28.5||||
 239 NWire_Pin|pin@220||-23|4||||
 240 NWire_Pin|pin@224||-7|28.5||||
 241 NWire_Pin|pin@225||-7|4||||
 242 Ngeneric:Invisible-Pin|pin@226||-78|91|||||ART_message(D6FMonospaced;G3;)S[Ye Olde Firing Rules:,* Fire when there is a non-Zero on the left and a Zero on the right,"-   If there was a Two  on the left, we want to leave One  on the left and Two  on the right","-   If there was a One  on the left, we want to leave Zero on the left and Two  on the right","-   If there was a Done on the left, we want to leave Done on the left and Done on the right"]
 243 Ngeneric:Invisible-Pin|pin@227||-52|65.5|||||ART_message(D4G1.5;)S[drained unless there was a Done on the left,"(equivalently: if pred[OneOrTwo] was HI before firing)"]
 244 Ngeneric:Invisible-Pin|pin@228||-51.5|4.5|||||ART_message(D4G1.5;)S[Drained if there was a One on the left before firing.,"(equivalently: if pred[DoneOrTwo] was LO before firing)"]
 245 Ngeneric:Invisible-Pin|pin@229||36.5|6|||||ART_message(D6G1.5;)S[filled if there wasn't a Done on the left before firing,(equivalently: if there wasn't a Done on the left AFTER firing)]
 246 Ngeneric:Invisible-Pin|pin@230||37.5|64.5|||||ART_message(D6G1.5;)S[filled unconditionally,(we only leave Done's and Two's on the right)]
 247 NWire_Pin|pin@234||-22|66||||
 248 NWire_Pin|pin@235||-22|36.5||||
 249 NWire_Pin|pin@236||-28|70.5||||
 250 NWire_Pin|pin@237||-15|48.5||||
 251 NWire_Pin|pin@238||-15|70.5||||
 252 NWire_Pin|pin@239||-15|76||||
 253 NWire_Pin|pin@240||-1.5|68||||
 254 NWire_Pin|pin@242||29|34.5||||
 255 NWire_Pin|pin@243||68.5|34.5||||
 256 NWire_Pin|pin@244||74|38||||
 257 NWire_Pin|pin@245||74|31||||
 258 NWire_Pin|pin@246||74|34.5||||
 259 Ngeneric:Invisible-Pin|pin@247||105|34|||||ART_message(D5G3;)S[load,"\"with",extreme,"prejudice\""]
 260 IdriversM:predCond20wMC;1{ic}|predCond@0||-32|1|RR||D5G4;
 261 IdriversM:predCond20wMC;1{ic}|predCond@1||-32|69|YRR||D5G4;
 262 NPower|pwr@0||68.5|48||||
 263 IdriversM:sucANDdri10;1{ic}|sucANDdr@0||19.5|3|Y||D5G4;
 264 IdriversM:sucDri10;1{ic}|sucDri10@0||21|68|||D5G4;
 265 Awire|fire|D5G2;||1800|predCond@0|in|-26|2|sucANDdr@0|inB|14.5|2
 266 Awire|fire|D5G2;||2700|ctrAND4i@0|out|-1.5|64.5|pin@240||-1.5|68
 267 Awire|net@319|||0|pin@120||-40.5|69|conn@2|y|-46|69
 268 Awire|net@322|||0|pin@115||-42|1|conn@1|a|-46|1
 269 Awire|net@324|||1800|pin@129||29|68|conn@3|a|32|68
 270 Awire|net@345|||1800|pin@128||29|3|conn@0|a|31.5|3
 271 Awire|net@346|||900|pin@242||29|34.5|pin@128||29|3
 272 Awire|net@348|||900|pin@129||29|68|pin@130||29|36.5
 273 Awire|net@369|||0|predCond@0|pred|-35|1|pin@115||-42|1
 274 Awire|net@375|||0|sucDri10@0|in|17|68|pin@163||5|68
 275 Awire|net@376|||1800|sucDri10@0|succ|25|68|pin@129||29|68
 276 Awire|net@379|||0|pin@130||29|36.5|pin@165||18.5|36.5
 277 Awire|net@383|||0|pin@127||29|34.5|pin@167||18|34.5
 278 Awire|net@394|||2700|pin@178||-3.5|35.5|ctrAND4i@0|inC|-3.5|52.5
 279 Awire|net@399|||900|ctrAND4i@0|inB|0.5|52.5|pin@181||0.5|34.5
 280 Awire|net@400|||1800|pin@181||0.5|34.5|pin@167||18|34.5
 281 Awire|net@401|||900|ctrAND4i@0|inA|2.5|52.5|pin@182||2.5|36.5
 282 Awire|net@402|||1800|pin@182||2.5|36.5|pin@165||18.5|36.5
 283 Awire|net@406|||2700|pin@115||-42|1|pin@180||-42|36.5
 284 Awire|net@436|||2700|pin@206||-5.5|48.5|ctrAND4i@0|inD|-5.5|52.5
 285 Awire|net@437|||900|pin@120||-40.5|69|pin@179||-40.5|34.5
 286 Awire|net@442|||1800|sucANDdr@0|succ|24.5|3|pin@128||29|3
 287 Awire|net@455|||0|pin@178||-3.5|35.5|pin@214||-5|35.5
 288 Awire|net@459|||1800|pin@179||-40.5|34.5|nor2with@0|ina|-20.5|34.5
 289 Awire|net@460|||1800|pin@180||-42|36.5|pin@235||-22|36.5
 290 Awire|net@461|||1800|nor2with@0|out|-10|35.5|pin@214||-5|35.5
 291 Awire|net@462|||900|nor2with@0|outaBar|-15|32.5|pin@218||-15|28.5
 292 Awire|net@463|||0|pin@218||-15|28.5|pin@219||-23|28.5
 293 Awire|net@466|||1800|predCond@0|cond|-26|4|pin@220||-23|4
 294 Awire|net@475|||1800|pin@218||-15|28.5|pin@224||-7|28.5
 295 Awire|net@477|||1800|pin@225||-7|4|sucANDdr@0|inA|14.5|4
 296 Awire|net@482|||0|predCond@1|pred|-35|69|pin@120||-40.5|69
 297 Awire|net@484|||1800|predCond@1|cond|-26|66|pin@234||-22|66
 298 Awire|net@485|||1800|pin@235||-22|36.5|nor2with@0|inb|-16|36.5
 299 Awire|net@486|||900|pin@234||-22|66|pin@235||-22|36.5
 300 Awire|net@487|||0|pin@238||-15|70.5|pin@236||-28|70.5
 301 Awire|net@488|||2700|pin@236||-28|70.5|predCond@1|mc|-28|71
 302 Awire|net@489|||0|pin@206||-5.5|48.5|pin@237||-15|48.5
 303 Awire|net@491|||2700|pin@237||-15|48.5|pin@238||-15|70.5
 304 Awire|net@493|||1800|conn@6|y|-46|76|pin@239||-15|76
 305 Awire|net@494|||900|pin@239||-15|76|pin@238||-15|70.5
 306 Awire|net@496|||0|pin@163||5|68|predCond@1|in|-26|68
 307 Awire|net@501|||900|pin@127||29|34.5|pin@242||29|34.5
 308 Awire|net@503|||1800|pin@242||29|34.5|pin@243||68.5|34.5
 309 Awire|net@507|||900|NMOS@1|d|68.5|29|NMOS@2|s|68.5|27.5
 310 Awire|net@508|||2700|NMOS@1|s|68.5|33|pin@243||68.5|34.5
 311 Awire|net@509|||900|PMOS@0|s|68.5|36|pin@243||68.5|34.5
 312 Awire|net@510|||900|PMOS@1|s|68.5|41|PMOS@0|d|68.5|40
 313 Awire|net@511|||2700|PMOS@1|d|68.5|45|pwr@0||68.5|48
 314 Awire|net@512|||1800|PMOS@0|g|71.5|38|pin@244||74|38
 315 Awire|net@513|||900|pin@246||74|34.5|pin@245||74|31
 316 Awire|net@514|||0|pin@245||74|31|NMOS@1|g|71.5|31
 317 Awire|net@515|||900|pin@244||74|38|pin@246||74|34.5
 318 Awire|net@516|||0|conn@7|y|80|34.5|pin@246||74|34.5
 319 Awire|net@517|||0|conn@8|y|80|43|PMOS@1|g|71.5|43
 320 Awire|net@518|||0|conn@9|y|80|25.5|NMOS@2|g|71.5|25.5
 321 Awire|predWasNotDoneAfterFiring|D5G1.5;RRR||900|pin@224||-7|28.5|pin@225||-7|4
 322 Awire|predWasOneBeforeFiring|D5G1.5;RRRY0.5;||900|pin@219||-23|28.5|pin@220||-23|4
 323 Eload||D5G2;X-3;|conn@9|a|U
 324 EloadBar||D5G2;X-4.5;|conn@8|a|U
 325 EloadVal|loadValBar|D5G2;X-6;|conn@7|a|U
 326 Eload_or_master_clear||D5G2;X-11;|conn@6|a|U
 327 Epred[TwoOrEmpty]|pred[DoneOrTwo]|D5G2;X-10.5;|conn@2|a|B
 328 Epred[OneOrTwo]||D5G2;X13;|conn@1|a|B
 329 Esucc[TwoOrEmpty]|succ[DoneOrTwo]|D5G2;X13.5;|conn@3|a|B
 330 Esucc[OneOrTwo]||D5G2;X12.5;|conn@0|a|B
 331 X