2 % (c) The AQUA Project, Glasgow University, 1993-2000
4 \section[AsmRegAlloc]{Register allocator}
7 module AsmRegAlloc ( runRegAllocate ) where
9 #include "HsVersions.h"
11 import MachCode ( InstrBlock )
12 import MachMisc ( Instr(..) )
13 import PprMach ( pprUserReg, pprInstr ) -- debugging
17 import FiniteMap ( FiniteMap, emptyFM, addListToFM, delListFromFM,
18 lookupFM, keysFM, eltsFM, mapFM, addToFM_C, addToFM,
19 listToFM, fmToList, lookupWithDefaultFM )
20 import Maybes ( maybeToBool )
21 import Unique ( mkBuiltinUnique )
22 import Util ( mapAccumB )
23 import OrdList ( unitOL, appOL, fromOL, concatOL )
25 import Unique ( Unique, Uniquable(..), mkPseudoUnique3 )
26 import CLabel ( CLabel, pprCLabel )
28 import List ( mapAccumL, nub, sort )
29 import Array ( Array, array, (!), bounds )
32 This is the generic register allocator. It does allocation for all
33 architectures. Details for specific architectures are given in
34 RegAllocInfo.lhs. In practice the allocator needs to know next to
35 nothing about an architecture to do its job:
37 * It needs to be given a list of the registers it can allocate to.
39 * It needs to be able to find out which registers each insn reads and
42 * It needs be able to change registers in instructions into other
45 * It needs to be able to find out where execution could go after an
48 * It needs to be able to discover sets of registers which can be
49 used to attempt spilling.
51 First we try something extremely simple. If that fails, we have to do
57 -> ([Instr] -> [[Reg]])
61 runRegAllocate regs find_reserve_regs instrs
62 = --trace ("runRegAllocate: " ++ show regs) (
64 Just simple -> --trace "SIMPLE"
66 Nothing -> --trace "GENERAL"
71 = error "nativeGen: spilling failed. Workaround: compile with -fvia-C.\n"
72 tryGeneral (resv:resvs)
73 = case generalAlloc resv of
74 Just success -> success
75 Nothing -> tryGeneral resvs
77 reserves = find_reserve_regs flatInstrs
78 flatInstrs = fromOL instrs
79 simpleAlloc = doSimpleAlloc regs flatInstrs
80 generalAlloc resvd = doGeneralAlloc regs resvd flatInstrs
83 Rather than invoke the heavyweight machinery in @doGeneralAlloc@ for
84 each and every code block, we first try using this simple, fast and
85 utterly braindead allocator. In practice it handles about 60\% of the
86 code blocks really fast, even with only 3 integer registers available.
87 Since we can always give up and fall back to @doGeneralAlloc@,
88 @doSimpleAlloc@ is geared to handling the common case as fast as
89 possible. It will succeed only if:
91 * The code mentions registers only of integer class, not floating
94 * The code doesn't mention any real registers, so we don't have to
95 think about dodging and weaving to work around fixed register uses.
97 * The code mentions at most N virtual registers, where N is the number
98 of real registers for allocation.
100 If those conditions are satisfied, we simply trundle along the code,
101 doling out a real register every time we see mention of a new virtual
102 register. We either succeed at this, or give up when one of the above
103 three conditions is no longer satisfied.
106 doSimpleAlloc :: [Reg] -> [Instr] -> Maybe [Instr]
107 doSimpleAlloc available_real_regs instrs
108 = let available_iregs
109 = filter ((== RcInteger).regClass) available_real_regs
111 trundle :: [( {-Virtual-}Reg, {-Real-}Reg )]
116 trundle vreg_map uncommitted_rregs ris_done []
117 = Just (reverse ris_done)
118 trundle vreg_map uncommitted_rregs ris_done (i:is)
122 -- Mentions no regs? Move on quickly
123 | null rds_l && null wrs_l
124 -> trundle vreg_map uncommitted_rregs (i:ris_done) is
126 -- A case we can't be bothered to handle?
127 | any isFloatingOrReal rds_l || any isFloatingOrReal wrs_l
130 -- Update the rreg commitments, and map the insn
132 -> case upd_commitment (wrs_l++rds_l)
133 vreg_map uncommitted_rregs of
134 Nothing -- out of rregs; give up
136 Just (vreg_map2, uncommitted_rregs2)
137 -> let i2 = patchRegs i (subst_reg vreg_map2)
138 in trundle vreg_map2 uncommitted_rregs2
142 = isRealReg reg || regClass reg == RcFloat
143 || regClass reg == RcDouble
145 rds_l = regSetToList rds
146 wrs_l = regSetToList wrs
148 upd_commitment [] vr_map uncomm
149 = Just (vr_map, uncomm)
150 upd_commitment (reg:regs) vr_map uncomm
152 = upd_commitment regs vr_map uncomm
153 | reg `elem` (map fst vr_map)
154 = upd_commitment regs vr_map uncomm
158 = upd_commitment regs ((reg, head uncomm):vr_map)
162 -- If it's a RealReg, it must be STG-specific one
163 -- (Hp,Sp,BaseReg,etc), since regUsage filters them out,
164 -- so isFloatingOrReal would not have objected to it.
168 = case [rr | (vr,rr) <- vreg_map, vr == r] of
171 "doSimpleAlloc: unmapped VirtualReg"
174 trundle [] available_iregs [] instrs
177 From here onwards is the general register allocator and spiller. For
178 each flow edge (possible transition between instructions), we compute
179 which virtual and real registers are live on that edge. Then the
180 mapping is inverted, to give a mapping from register (virtual+real) to
181 sets of flow edges on which the register is live. Finally, we can use
182 those sets to decide whether a virtual reg v can be assigned to a real
183 reg r, by checking that v's live-edge-set does not intersect with r's
184 current live-edge-set. Having made that assignment, we then augment
185 r's current live-edge-set (its current commitment, you could say) with
188 doGeneralAlloc takes reserve_regs as the regs to use as spill
189 temporaries. First it tries to allocate using all regs except
190 reserve_regs. If that fails, it inserts spill code and tries again to
191 allocate regs, but this time with the spill temporaries available.
192 Even this might not work if there are insufficient spill temporaries:
193 in the worst case on x86, we'd need 3 of them, for insns like addl
194 (%reg1,%reg2,4) %reg3, since this insn uses all 3 regs as input.
198 :: [Reg] -- all allocatable regs
199 -> [Reg] -- the reserve regs
200 -> [Instr] -- instrs in
201 -> Maybe [Instr] -- instrs out
203 doGeneralAlloc all_regs reserve_regs instrs
204 -- succeeded without spilling
205 | prespill_ok = Just prespill_insns
206 -- failed, and no spill regs avail, so pointless to attempt spilling
207 | null reserve_regs = Nothing
208 -- success after spilling
209 | postspill_ok = maybetrace (spillMsg True) (Just postspill_insns)
210 -- still not enough reserves after spilling; we have to give up
211 | otherwise = maybetrace (spillMsg False) Nothing
214 = filter (`notElem` reserve_regs) all_regs
215 (prespill_ok, prespill_insns)
216 = allocUsingTheseRegs instrs prespill_regs
217 instrs_with_spill_code
218 = insertSpillCode prespill_insns
219 (postspill_ok, postspill_insns)
220 = allocUsingTheseRegs instrs_with_spill_code all_regs
223 = "nativeGen: spilling "
224 ++ (if success then "succeeded" else "failed ")
226 ++ showSDoc (hsep (map ppr reserve_regs))
228 # if 1 /* ifdef DEBUG */
229 maybetrace msg x = trace msg x
235 Here we patch instructions that reference ``registers'' which are
236 really in memory somewhere (the mapping is under the control of the
237 machine-specific code generator). We place the appropriate load
238 sequences before any instructions that use memory registers as
239 sources, and we place the appropriate spill sequences after any
240 instructions that use memory registers as destinations. The offending
241 instructions are rewritten with new dynamic registers, so generalAlloc
242 has to run register allocation again after all of this is said and
245 On some architectures (x86, currently), we do without a frame-pointer,
246 and instead spill relative to the stack pointer (%esp on x86).
247 Because the stack pointer may move, the patcher needs to keep track of
248 the current stack pointer "delta". That's easy, because all it needs
249 to do is spot the DELTA bogus-insns which will have been inserted by
250 the relevant insn selector precisely so as to notify the spiller of
251 stack-pointer movement. The delta is passed to loadReg and spillReg,
252 since they generate the actual spill code. We expect the final delta
253 to be the same as the starting one (zero), reflecting the fact that
254 changes to the stack pointer should not extend beyond a basic block.
256 Finally, there is the issue of mapping an arbitrary set of unallocated
257 VirtualRegs into a contiguous sequence of spill slots. The failed
258 allocation will have left the code peppered with references to
259 VirtualRegs, each of which contains a unique. So we make an env which
260 maps these VirtualRegs to integers, starting from zero, and pass that
261 env through to loadReg and spillReg. There, they are used to look up
262 spill slot numbers for the uniques.
265 insertSpillCode :: [Instr] -> [Instr]
266 insertSpillCode insns
267 = let uniques_in_insns
270 (foldl unionRegSets emptyRegSet
271 (map vregs_in_insn insns)))
274 RU rds wrs -> filterRegSet isVirtualReg
275 (rds `unionRegSets` wrs)
276 vreg_to_slot_map :: FiniteMap Unique Int
278 = listToFM (zip uniques_in_insns [0..])
280 ((final_stack_delta, final_ctr), insnss)
281 = mapAccumL (patchInstr vreg_to_slot_map) (0,0) insns
283 if final_stack_delta == 0
285 else pprPanic "patchMem: non-zero final delta"
286 (int final_stack_delta)
289 -- patchInstr has as a running state two Ints, one the current stack delta,
290 -- needed to figure out offsets to stack slots on archs where we spill relative
291 -- to the stack pointer, as opposed to the frame pointer. The other is a
292 -- counter, used to manufacture new temporary register names.
294 patchInstr :: FiniteMap Unique Int -> (Int,Int) -> Instr -> ((Int,Int), [Instr])
295 patchInstr vreg_to_slot_map (delta,ctr) instr
297 | null memSrcs && null memDsts
298 = ((delta',ctr), [instr])
301 = ((delta',ctr'), loadSrcs ++ [instr'] ++ spillDsts)
303 delta' = case instr of DELTA d -> d ; _ -> delta
305 (RU srcs dsts) = regUsage instr
307 -- The instr being patched may mention several vregs -- those which
308 -- could not be assigned real registers. For each such vreg, we
309 -- invent a new vreg, used only around this instruction and nowhere
310 -- else. These new vregs replace the unallocatable vregs; they are
311 -- loaded from the spill area, the instruction is done with them,
312 -- and results if any are then written back to the spill area.
314 = nub (filter isVirtualReg
315 (regSetToList srcs ++ regSetToList dsts))
317 = length vregs_in_instr
319 = ctr + n_vregs_in_instr
321 = zip vregs_in_instr [ctr, ctr+1 ..]
325 = case [vi | (vreg', vi) <- vreg_env, vreg' == vreg] of
326 [i] -> if regClass vreg == RcInteger
327 then VirtualRegI (mkPseudoUnique3 i)
328 else VirtualRegF (mkPseudoUnique3 i)
329 _ -> pprPanic "patchInstr: unmapped VReg" (ppr vreg)
333 memSrcs = filter isVirtualReg (regSetToList srcs)
334 memDsts = filter isVirtualReg (regSetToList dsts)
336 loadSrcs = map load memSrcs
337 spillDsts = map spill memDsts
339 load mem = loadReg vreg_to_slot_map delta mem (mkTmpReg mem)
340 spill mem = spillReg vreg_to_slot_map delta' (mkTmpReg mem) mem
342 instr' = patchRegs instr mkTmpReg
345 allocUsingTheseRegs is the register allocator proper. It attempts
346 to allocate dynamic regs to real regs, given a list of real regs
347 which it may use. If it fails due to lack of real regs, the returned
348 instructions use what real regs there are, but will retain uses of
349 dynamic regs for which a real reg could not be found. It is these
350 leftover dynamic reg references which insertSpillCode will later
351 assign to spill slots.
353 Some implementation notes.
354 ~~~~~~~~~~~~~~~~~~~~~~~~~~
355 Instructions are numbered sequentially, starting at zero.
357 A flow edge (FE) is a pair of insn numbers (MkFE Int Int) denoting
358 a possible flow of control from the first insn to the second.
360 The input to the register allocator is a list of instructions, which
361 mention Regs. A Reg can be a RealReg -- a real machine reg -- or a
362 VirtualReg, which carries a unique. After allocation, all the
363 VirtualReg references will have been converted into RealRegs, and
364 possible some spill code will have been inserted.
366 The heart of the register allocator works in four phases.
368 1. (find_flow_edges) Calculate all the FEs for the code list.
369 Return them not as a [FE], but implicitly, as a pair of
370 Array Int [Int], being the successor and predecessor maps
373 2. (calc_liveness) Returns a FiniteMap FE RegSet. For each
374 FE, indicates the set of registers live on that FE. Note
375 that the set includes both RealRegs and VirtualRegs. The
376 former appear because the code could mention fixed register
377 usages, and we need to take them into account from the start.
379 3. (calc_live_range_sets) Invert the above mapping, giving a
380 FiniteMap Reg FeSet, indicating, for each virtual and real
381 reg mentioned in the code, which FEs it is live on.
383 4. (calc_vreg_to_rreg_mapping) For virtual reg, try and find
384 an allocatable real register for it. Each real register has
385 a "current commitment", indicating the set of FEs it is
386 currently live on. A virtual reg v can be assigned to
387 real reg r iff v's live-fe-set does not intersect with r's
388 current commitment fe-set. If the assignment is made,
389 v's live-fe-set is union'd into r's current commitment fe-set.
390 There is also the minor restriction that v and r must be of
391 the same register class (integer or floating).
393 Once this mapping is established, we simply apply it to the
394 input insns, and that's it.
396 If no suitable real register can be found, the vreg is mapped
397 to itself, and we deem allocation to have failed. The partially
398 allocated code is returned. The higher echelons of the allocator
399 (doGeneralAlloc and runRegAlloc) then cooperate to insert spill
400 code and re-run allocation, until a successful allocation is found.
403 allocUsingTheseRegs :: [Instr] -> [Reg] -> (Bool, [Instr])
404 allocUsingTheseRegs instrs available_real_regs
405 = let (all_vregs_mapped, v_to_r_mapping)
406 = calc_vreg_to_rreg_mapping instrs available_real_regs
408 = map (flip patchRegs sr) instrs
413 = case lookupFM v_to_r_mapping reg of
415 Nothing -> pprPanic "allocateUsingTheseRegs: unmapped vreg: "
418 --trace ("allocUsingTheseRegs: " ++ show available_real_regs) (
419 (all_vregs_mapped, new_insns)
423 -- the heart of the matter.
424 calc_vreg_to_rreg_mapping :: [Instr] -> [Reg] -> (Bool, FiniteMap Reg Reg)
425 calc_vreg_to_rreg_mapping insns available_real_regs
427 lr_sets :: FiniteMap Reg FeSet
428 lr_sets = calc_live_range_sets insns
430 -- lr_sets maps: vregs mentioned in insns to sets of live FEs
431 -- and also: rregs mentioned in insns to sets of live FEs
432 -- We need to extract the rreg mapping, and use it as the
433 -- initial real-register-commitment. Also, add to the initial
434 -- commitment, empty commitments for any real regs not
437 -- which real regs do we want to keep track of in the running
438 -- commitment mapping? Precisely the available_real_regs.
439 -- We don't care about real regs mentioned by insns which are
440 -- not in this list, since we're not allocating to them.
441 initial_rr_commitment :: FiniteMap Reg FeSet
442 initial_rr_commitment
444 case lookupFM lr_sets rreg of
445 Nothing -> emptyFeSet
446 Just fixed_use_fes -> fixed_use_fes
448 | rreg <- available_real_regs]
450 -- These are the vregs for which we actually have to (try to)
451 -- assign a real register. (ie, the whole reason we're here at all :)
452 vreg_liveness_list :: [(Reg, FeSet)]
453 vreg_liveness_list = filter (not.isRealReg.fst)
456 -- A loop, which attempts to assign each vreg to a rreg.
457 loop rr_commitment v_to_r_map []
459 loop rr_commitment v_to_r_map ((vreg,vreg_live_fes):not_yet_done)
461 -- find a real reg which is not live for any of vreg_live_fes
464 | (rreg,rreg_live_FEs) <- fmToList rr_commitment,
465 regClass vreg == regClass rreg,
466 isEmptyFeSet (intersectionFeSets rreg_live_FEs
471 [] -> -- bummer. No register is available. Just go on to
472 -- the next vreg, mapping the vreg to itself.
473 loop rr_commitment (addToFM v_to_r_map vreg vreg)
476 -> -- Hurrah! Found a free reg of the right class.
477 -- Now we need to update the RR commitment.
478 loop rr_commitment2 (addToFM v_to_r_map vreg r)
482 = addToFM_C unionFeSets rr_commitment r
485 -- the final vreg to rreg mapping
487 = loop initial_rr_commitment emptyFM vreg_liveness_list
488 -- did we succeed in mapping everyone to a real reg?
490 = all isRealReg (eltsFM vreg_assignment)
492 (allocation_succeeded, vreg_assignment)
496 -- calculate liveness, then produce the live range info
497 -- as a mapping of VRegs to the set of FEs on which they are live.
498 -- The difficult part is inverting the mapping of Reg -> FeSet
499 -- to produce a mapping FE -> RegSet.
501 calc_live_range_sets :: [Instr] -> FiniteMap Reg FeSet
502 calc_live_range_sets insns
504 -- this is the "original" (old) mapping
505 lis :: FiniteMap FE RegSet
506 lis = calc_liveness insns
508 -- establish the totality of reg names mentioned by the
509 -- insns, by scanning over the insns.
510 all_mentioned_regs :: RegSet
512 = foldl unionRegSets emptyRegSet
513 (map (\i -> case regUsage i of
514 RU rds wrs -> unionRegSets rds wrs)
517 -- Initial inverted mapping, from Reg to sets of FEs
518 initial_imap :: FiniteMap Reg FeSet
520 = listToFM [(reg, emptyFeSet)
521 | reg <- regSetToList all_mentioned_regs]
523 -- Update the new map with one element of the old map
524 upd_imap :: FiniteMap Reg FeSet -> (FE, RegSet)
525 -> FiniteMap Reg FeSet
526 upd_imap imap (fe, regset)
527 = foldl upd_1_imap imap (regSetToList regset)
530 = addToFM_C unionFeSets curr reg (unitFeSet fe)
532 -- the complete inverse mapping
533 final_imap :: FiniteMap Reg FeSet
535 = foldl upd_imap initial_imap (fmToList lis)
541 -- Given the insns, calculate the FEs, and then doing fixpointing to
542 -- figure out the set of live regs (virtual regs AND real regs) live
545 calc_liveness :: [Instr] -> FiniteMap FE RegSet
547 = let (pred_map, succ_map)
548 = find_flow_edges insns
550 -- We use the convention that if the current approximation
551 -- doesn't give a mapping for some FE, that FE maps to the
553 initial_approx, fixpoint :: FiniteMap FE RegSet
555 = mk_initial_approx 0 insns succ_map emptyFM
557 = fix_set initial_approx 1
558 -- If you want to live dangerously, and promise that the code
559 -- doesn't contain any loops (ie, there are no back edges in
560 -- the flow graph), you should be able to get away with this:
561 -- = upd_liveness_info pred_map succ_map insn_array initial_approx
562 -- But since I'm paranoid, and since it hardly makes any difference
563 -- to the compiler run-time (about 0.1%), I prefer to do the
564 -- the full fixpointing game.
567 = let n = length insns
568 in array (0, n-1) (zip [0..] insns)
570 sameSets [] [] = True
571 sameSets (c:cs) (n:ns) = eqRegSets c n && sameSets cs ns
574 fix_set curr_approx iter_number
576 = upd_liveness_info pred_map succ_map insn_array curr_approx
582 = sameSets curr_sets next_sets
584 = if same then curr_approx
585 else fix_set next_approx (iter_number+1)
587 --trace (let qqq (fe, regset)
588 -- = show fe ++ " " ++ show (regSetToList regset)
590 -- "\n::iteration " ++ show iter_number ++ "\n"
591 -- ++ (unlines . map qqq . fmToList)
592 -- next_approx ++"\n"
599 -- Create a correct initial approximation. For each instruction that
600 -- writes a register, we deem that the register is live on the
601 -- flow edges leaving the instruction. Subsequent iterations of
602 -- the liveness AbI augment this based purely on reads of regs, not
603 -- writes. We need to start off with at least this minimal write-
604 -- based information in order that writes to vregs which are never
605 -- used have non-empty live ranges. If we don't do that, we eventually
606 -- wind up assigning such vregs to any old real reg, since they don't
607 -- apparently conflict -- you can't conflict with an empty live range.
608 -- This kludge is unfortunate, but we need to do it to cover not only
609 -- writes to vregs which are never used, but also to deal correctly
610 -- with the fact that calls to C will trash the callee saves registers.
612 mk_initial_approx :: Int -> [Instr] -> Array Int [Int]
613 -> FiniteMap FE RegSet
614 -> FiniteMap FE RegSet
615 mk_initial_approx ino [] succ_map ia_so_far
617 mk_initial_approx ino (i:is) succ_map ia_so_far
619 = case regUsage i of RU rrr www -> www
621 = [case ino of { I# inoh ->
622 case ino_succ of { I# ino_succh ->
625 | ino_succ <- succ_map ! ino]
629 = loop fes (addToFM_C unionRegSets ia fe wrs)
632 = loop new_fes ia_so_far
634 mk_initial_approx (ino+1) is succ_map next_ia
637 -- Do one step in the liveness info calculation (AbI :). Given the
638 -- prior approximation (which tells you a subset of live VRegs+RRegs
639 -- for each flow edge), calculate new information for all FEs.
640 -- Rather than do this by iterating over FEs, it's easier to iterate
641 -- over insns, and update their incoming FEs.
643 upd_liveness_info :: Array Int [Int] -- instruction pred map
644 -> Array Int [Int] -- instruction succ map
645 -> Array Int Instr -- array of instructions
646 -> FiniteMap FE RegSet -- previous approx
647 -> FiniteMap FE RegSet -- improved approx
649 upd_liveness_info pred_map succ_map insn_array prev_approx
650 = do_insns hi prev_approx
652 (lo, hi) = bounds insn_array
654 enquireMapFE :: FiniteMap FE RegSet -> FE
657 = case lookupFM fm fe of
659 Nothing -> emptyRegSet
661 -- Work backwards, from the highest numbered insn to the lowest.
662 -- This is a heuristic which causes faster convergence to the
663 -- fixed point. In particular, for straight-line code with no
664 -- branches at all, arrives at the fixpoint in one iteration.
670 = [case ino of { I# inoh ->
671 case future_ino of { I# future_inoh ->
672 MkFE inoh future_inoh
674 | future_ino <- succ_map ! ino]
676 = map (enquireMapFE approx) fes_to_futures
678 = foldr unionRegSets emptyRegSet future_lives
681 = [case history_ino of { I# history_inoh ->
682 case ino of { I# inoh ->
683 MkFE history_inoh inoh
685 | history_ino <- pred_map ! ino]
687 = foldl update_one_history approx fes_from_histories
691 history_independent_component
692 = case regUsage insn of
695 (minusRegSets future_live wrs)
697 update_one_history :: FiniteMap FE RegSet
699 -> FiniteMap FE RegSet
700 update_one_history approx0 fe
701 = addToFM_C unionRegSets approx0 fe
702 history_independent_component
705 = do_insns (ino-1) new_approx
711 -- Extract the flow edges from a list of insns. Express the information
712 -- as two mappings, from insn number to insn numbers of predecessors,
713 -- and from insn number to insn numbers of successors. (Since that's
714 -- what we need to know when computing live ranges later). Instructions
715 -- are numbered starting at zero. This function is long and complex
716 -- in order to be efficient; it could equally well be shorter and slower.
718 find_flow_edges :: [Instr] -> (Array Int [Int],
720 find_flow_edges insns
722 -- First phase: make a temp env which maps labels
723 -- to insn numbers, so the second pass can know the insn
724 -- numbers for jump targets.
726 label_env :: FiniteMap CLabel Int
728 mk_label_env n env [] = env
729 mk_label_env n env ((LABEL clbl):is)
730 = mk_label_env (n+1) (addToFM env clbl n) is
731 mk_label_env n env (i:is)
732 = mk_label_env (n+1) env is
734 label_env = mk_label_env 0 emptyFM insns
736 find_label :: CLabel -> Int
738 = case lookupFM label_env jmptarget of
740 Nothing -> pprPanic "find_flow_edges: unmapped label"
741 (pprCLabel jmptarget)
743 -- Second phase: traverse the insns, and make up the successor map.
745 least_ino, greatest_ino :: Int
747 greatest_ino = length insns - 1
749 mk_succ_map :: Int -> [(Int, [Int])] -> [Instr] -> [(Int, [Int])]
751 mk_succ_map i_num rsucc_map []
754 mk_succ_map i_num rsucc_map (i:is)
755 = let i_num_1 = i_num + 1
760 -> -- A non-local jump. We can regard this insn as a terminal
761 -- insn in the graph, so we don't add any edges.
762 mk_succ_map i_num_1 ((i_num,[]):rsucc_map) is
765 | null is -- this is the last insn, and it doesn't go anywhere
766 -- (a meaningless scenario); handle it anyway
767 -> mk_succ_map i_num_1 ((i_num,[]):rsucc_map) is
769 | otherwise -- flows to next insn; add fe i_num -> i_num+1
770 -> mk_succ_map i_num_1 ((i_num, [i_num_1]): rsucc_map)
773 Branch lab -- jmps to lab; add fe i_num -> i_target
774 -> let i_target = find_label lab
776 mk_succ_map i_num_1 ((i_num, [i_target]): rsucc_map)
779 | null is -- jmps to label, or falls through, and this is
780 -- the last insn (a meaningless scenario);
782 -> error "find_flow_edges: NextOrBranch is last"
784 | otherwise -- add fes i_num -> i_num+1
785 -- and i_num -> i_target
786 -> let i_target = find_label lab
788 mk_succ_map i_num_1 ((i_num, [i_num_1, i_target]):rsucc_map)
791 -- Third phase: invert the successor map to get the predecessor
792 -- map, using an algorithm which is quadratic in the worst case,
793 -- but runs in almost-linear time, because of the nature of our
794 -- inputs: most insns have a single successor, the next insn.
796 invert :: [(Int, [Int])] -> [(Int, [Int])]
799 = concatMap ( \ (a, bs) -> [(b,a) | b <- bs] ) fmap
800 sorted_inverted_pairs
801 = isort inverted_pairs
803 grp :: Int -> [Int] -> [(Int,Int)] -> [(Int,[Int])]
804 grp k vs [] = [(k, vs)]
805 grp k vs ((kk,vv):rest)
806 | k == kk = grp k (vv:vs) rest
807 | otherwise = (k,vs) : grp kk [vv] rest
810 grp_start ((kk,vv):rest) = grp kk [vv] rest
813 = grp_start sorted_inverted_pairs
815 -- make sure that the reverse mapping maps all inos
817 | ino > greatest_ino = []
818 | otherwise = (ino,[]): add_empties (ino+1) []
819 add_empties ino ((k,vs):rest)
820 | ino < k = (ino,[]): add_empties (ino+1) ((k,vs):rest)
821 | ino == k = (k,vs) : add_empties (ino+1) rest
823 -- This is nearly linear provided that the fsts of the
824 -- list are nearly in order -- a critical assumption
826 isort :: [(Int,Int)] -> [(Int,Int)]
828 isort (x:xs) = insert x (isort xs)
830 insert :: (Int,Int) -> [(Int,Int)] -> [(Int,Int)]
833 -- specifically, this first test should almost always
834 -- be True in order for the near-linearity to happen
835 | fst y <= fst z = y:z:zs
836 | otherwise = z: insert y zs
838 add_empties least_ino grouped
843 = mk_succ_map 0 [] insns
845 = array (least_ino, greatest_ino) succ_list
849 = array (least_ino, greatest_ino) pred_list
854 -- That's all, folks! From here on is just some dull supporting stuff.
856 -- A data type for flow edges
858 = MkFE Int# Int# deriving (Eq, Ord)
860 -- deriving Show on types with unboxed fields doesn't work
861 instance Show FE where
862 showsPrec _ (MkFE s d)
863 = showString "MkFE" . shows (I# s) . shows ' ' . shows (I# d)
865 -- Blargh. Use ghc stuff soon! Or: perhaps that's not such a good
866 -- idea. Most of these sets are either empty or very small, and it
867 -- might be that the overheads of the FiniteMap based set implementation
868 -- is a net loss. The same might be true of RegSets.
870 newtype FeSet = MkFeSet [FE]
873 = MkFeSet (nukeDups (sort xs))
874 where nukeDups :: [FE] -> [FE]
878 = if x == y then nukeDups (y:xys)
879 else x : nukeDups (y:xys)
881 feSetToList (MkFeSet xs) = xs
882 isEmptyFeSet (MkFeSet xs) = null xs
883 emptyFeSet = MkFeSet []
884 eqFeSet (MkFeSet xs1) (MkFeSet xs2) = xs1 == xs2
885 unitFeSet x = MkFeSet [x]
887 elemFeSet x (MkFeSet xs)
891 f (y:ys) | x == y = True
895 unionFeSets (MkFeSet xs1) (MkFeSet xs2)
896 = MkFeSet (f xs1 xs2)
901 | a < b = a : f as (b:bs)
902 | a > b = b : f (a:as) bs
903 | otherwise = a : f as bs
905 minusFeSets (MkFeSet xs1) (MkFeSet xs2)
906 = MkFeSet (f xs1 xs2)
911 | a < b = a : f as (b:bs)
912 | a > b = f (a:as) bs
913 | otherwise = f as bs
915 intersectionFeSets (MkFeSet xs1) (MkFeSet xs2)
916 = MkFeSet (f xs1 xs2)
921 | a < b = f as (b:bs)
922 | a > b = f (a:as) bs
923 | otherwise = a : f as bs