2 % (c) The AQUA Project, Glasgow University, 1993-1998
4 \section[MachMisc]{Description of various machine-specific things}
7 #include "nativeGen/NCG.h"
11 sizeOf, primRepToSize,
15 volatileSaves, volatileRestores,
17 targetMaxDouble, targetMaxInt, targetMinDouble, targetMinInt,
23 Instr(..), IF_ARCH_i386(Operand(..) COMMA,)
26 IF_ARCH_i386(i386_insert_ffrees COMMA,)
34 RI(..), riZero, fpRelEA, moveSp, fPair
38 #include "HsVersions.h"
39 -- #include "config.h"
41 import AbsCSyn ( MagicId(..) )
42 import AbsCUtils ( magicIdPrimRep )
43 import CLabel ( CLabel, isAsmTemp )
44 import Literal ( mkMachInt, Literal(..) )
45 import MachRegs ( stgReg, callerSaves, RegLoc(..),
48 # if sparc_TARGET_ARCH
52 import PrimRep ( PrimRep(..) )
53 import Stix ( StixTree(..), StixReg(..), CodeSegment, DestInfo(..) )
54 import Panic ( panic )
55 import GlaExts ( word2Int#, int2Word#, shiftRL#, and#, (/=#) )
56 import Outputable ( pprPanic, ppr )
57 import IOExts ( trace )
62 underscorePrefix :: Bool -- leading underscore on assembler labels?
64 #ifdef LEADING_UNDERSCORE
65 underscorePrefix = True
67 underscorePrefix = False
70 ---------------------------
71 fmtAsmLbl :: String -> String -- for formatting labels
75 {- The alpha assembler likes temporary labels to look like $L123
76 instead of L123. (Don't toss the L, because then Lf28
85 % ----------------------------------------------------------------
87 We (allegedly) put the first six C-call arguments in registers;
88 where do we start putting the rest of them?
90 eXTRA_STK_ARGS_HERE :: Int
92 = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,???)))
95 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
97 Size of a @PrimRep@, in bytes.
100 sizeOf :: PrimRep -> Integer{-in bytes-}
101 -- the result is an Integer only because it's more convenient
103 sizeOf pr = case (primRepToSize pr) of
104 IF_ARCH_alpha({B -> 1; BU -> 1; {-W -> 2; WU -> 2;-} L -> 4; {-SF -> 4;-} _ -> 8},)
105 IF_ARCH_sparc({B -> 1; BU -> 1; W -> 4; F -> 4; DF -> 8},)
106 IF_ARCH_i386( {B -> 1; BU -> 1; L -> 4; F -> 4; DF -> 8 },)
109 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
111 Now the volatile saves and restores. We add the basic guys to the
112 list of ``user'' registers provided. Note that there are more basic
113 registers on the restore list, because some are reloaded from
116 (@volatileRestores@ used only for wrapper-hungry PrimOps.)
119 volatileSaves, volatileRestores :: [MagicId] -> [StixTree]
121 save_cands = [BaseReg,Sp,Su,SpLim,Hp,HpLim]
122 restore_cands = save_cands
125 = map save ((filter callerSaves) (save_cands ++ vols))
127 save x = StAssign (magicIdPrimRep x) loc reg
129 reg = StReg (StixMagicId x)
130 loc = case stgReg x of
132 Always _ -> panic "volatileSaves"
134 volatileRestores vols
135 = map restore ((filter callerSaves) (restore_cands ++ vols))
137 restore x = StAssign (magicIdPrimRep x) reg loc
139 reg = StReg (StixMagicId x)
140 loc = case stgReg x of
142 Always _ -> panic "volatileRestores"
145 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
147 Obviously slightly weedy
148 (Note that the floating point values aren't terribly important.)
151 targetMinDouble = MachDouble (-1.7976931348623157e+308)
152 targetMaxDouble = MachDouble (1.7976931348623157e+308)
153 targetMinInt = mkMachInt (-2147483648)
154 targetMaxInt = mkMachInt 2147483647
157 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
159 This algorithm for determining the $\log_2$ of exact powers of 2 comes
160 from GCC. It requires bit manipulation primitives, and we use GHC
167 exactLog2 :: Integer -> Maybe Integer
169 = if (x <= 0 || x >= 2147483648) then
172 case iUnbox (fromInteger x) of { x# ->
173 if (w2i ((i2w x#) `and#` (i2w (0# -# x#))) /=# x#) then
176 Just (toInteger (iBox (pow2 x#)))
179 shiftr x y = shiftRL# x y
181 pow2 x# | x# ==# 1# = 0#
182 | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` 1#))
185 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
189 #if alpha_TARGET_ARCH
190 = ALWAYS -- For BI (same as BR)
191 | EQQ -- For CMP and BI (NB: "EQ" is a 1.3 Prelude name)
193 | GTT -- For BI only (NB: "GT" is a 1.3 Prelude name)
194 | LE -- For CMP and BI
195 | LTT -- For CMP and BI (NB: "LT" is a 1.3 Prelude name)
197 | NEVER -- For BI (null instruction)
198 | ULE -- For CMP only
199 | ULT -- For CMP only
202 = ALWAYS -- What's really used? ToDo
216 #if sparc_TARGET_ARCH
217 = ALWAYS -- What's really used? ToDo
238 #if alpha_TARGET_ARCH
241 -- | W -- word (2 bytes): UNUSED
243 | L -- longword (4 bytes)
244 | Q -- quadword (8 bytes)
245 -- | FF -- VAX F-style floating pt: UNUSED
246 -- | GF -- VAX G-style floating pt: UNUSED
247 -- | DF -- VAX D-style floating pt: UNUSED
248 -- | SF -- IEEE single-precision floating pt: UNUSED
249 | TF -- IEEE double-precision floating pt
252 = B -- byte (signed, JRS:??lower??)
253 | BU -- byte, unsigned
255 | F -- IEEE single-precision floating pt
256 | DF -- IEEE single-precision floating pt
257 | F80 -- Intel 80-bit internal FP format; only used for spilling
259 #if sparc_TARGET_ARCH
261 | BU -- byte (unsigned)
263 | F -- IEEE single-precision floating pt
264 | DF -- IEEE single-precision floating pt
267 primRepToSize :: PrimRep -> Size
269 primRepToSize PtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
270 primRepToSize CodePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
271 primRepToSize DataPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
272 primRepToSize RetRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
273 primRepToSize CostCentreRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
274 primRepToSize CharRep = IF_ARCH_alpha( L, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
276 primRepToSize Int8Rep = IF_ARCH_alpha( B, IF_ARCH_i386( B, IF_ARCH_sparc( B ,)))
277 primRepToSize Word8Rep = IF_ARCH_alpha( BU, IF_ARCH_i386( BU, IF_ARCH_sparc( BU,)))
279 primRepToSize IntRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
280 primRepToSize WordRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
281 primRepToSize AddrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
282 primRepToSize FloatRep = IF_ARCH_alpha( TF, IF_ARCH_i386( F, IF_ARCH_sparc( F ,)))
283 primRepToSize DoubleRep = IF_ARCH_alpha( TF, IF_ARCH_i386( DF,IF_ARCH_sparc( DF,)))
284 primRepToSize ArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
285 primRepToSize ByteArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
286 primRepToSize PrimPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
287 primRepToSize WeakPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
288 primRepToSize ForeignObjRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
289 primRepToSize BCORep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
290 primRepToSize StablePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
291 primRepToSize ThreadIdRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
292 -- SUP: Wrong!!! Only for testing the rest of the NCG
293 primRepToSize Word64Rep = trace "primRepToSize: Word64Rep not handled" B
294 primRepToSize Int64Rep = trace "primRepToSize: Int64Rep not handled" B
297 %************************************************************************
299 \subsection{Machine's assembly language}
301 %************************************************************************
303 We have a few common ``instructions'' (nearly all the pseudo-ops) but
304 mostly all of @Instr@ is machine-specific.
308 = COMMENT FAST_STRING -- comment pseudo-op
309 | SEGMENT CodeSegment -- {data,text} segment pseudo-op
310 | LABEL CLabel -- global label pseudo-op
311 | ASCII Bool -- True <=> needs backslash conversion
312 String -- the literal string
315 | DELTA Int -- specify current stack offset for
316 -- benefit of subsequent passes
320 #if alpha_TARGET_ARCH
322 -- data Instr continues...
326 | LD Size Reg MachRegsAddr -- size, dst, src
327 | LDA Reg MachRegsAddr -- dst, src
328 | LDAH Reg MachRegsAddr -- dst, src
329 | LDGP Reg MachRegsAddr -- dst, src
330 | LDI Size Reg Imm -- size, dst, src
331 | ST Size Reg MachRegsAddr -- size, src, dst
336 | ABS Size RI Reg -- size, src, dst
337 | NEG Size Bool RI Reg -- size, overflow, src, dst
338 | ADD Size Bool Reg RI Reg -- size, overflow, src, src, dst
339 | SADD Size Size Reg RI Reg -- size, scale, src, src, dst
340 | SUB Size Bool Reg RI Reg -- size, overflow, src, src, dst
341 | SSUB Size Size Reg RI Reg -- size, scale, src, src, dst
342 | MUL Size Bool Reg RI Reg -- size, overflow, src, src, dst
343 | DIV Size Bool Reg RI Reg -- size, unsigned, src, src, dst
344 | REM Size Bool Reg RI Reg -- size, unsigned, src, src, dst
346 -- Simple bit-twiddling.
366 | CMP Cond Reg RI Reg
373 | FADD Size Reg Reg Reg
374 | FDIV Size Reg Reg Reg
375 | FMUL Size Reg Reg Reg
376 | FSUB Size Reg Reg Reg
377 | CVTxy Size Size Reg Reg
378 | FCMP Size Cond Reg Reg Reg
386 | JMP Reg MachRegsAddr Int
388 | JSR Reg MachRegsAddr Int
390 -- Alpha-specific pseudo-ops.
399 #endif {- alpha_TARGET_ARCH -}
402 Intel, in their infinite wisdom, selected a stack model for floating
403 point registers on x86. That might have made sense back in 1979 --
404 nowadays we can see it for the nonsense it really is. A stack model
405 fits poorly with the existing nativeGen infrastructure, which assumes
406 flat integer and FP register sets. Prior to this commit, nativeGen
407 could not generate correct x86 FP code -- to do so would have meant
408 somehow working the register-stack paradigm into the register
409 allocator and spiller, which sounds very difficult.
411 We have decided to cheat, and go for a simple fix which requires no
412 infrastructure modifications, at the expense of generating ropey but
413 correct FP code. All notions of the x86 FP stack and its insns have
414 been removed. Instead, we pretend (to the instruction selector and
415 register allocator) that x86 has six floating point registers, %fake0
416 .. %fake5, which can be used in the usual flat manner. We further
417 claim that x86 has floating point instructions very similar to SPARC
418 and Alpha, that is, a simple 3-operand register-register arrangement.
419 Code generation and register allocation proceed on this basis.
421 When we come to print out the final assembly, our convenient fiction
422 is converted to dismal reality. Each fake instruction is
423 independently converted to a series of real x86 instructions.
424 %fake0 .. %fake5 are mapped to %st(0) .. %st(5). To do reg-reg
425 arithmetic operations, the two operands are pushed onto the top of the
426 FP stack, the operation done, and the result copied back into the
427 relevant register. There are only six %fake registers because 2 are
428 needed for the translation, and x86 has 8 in total.
430 The translation is inefficient but is simple and it works. A cleverer
431 translation would handle a sequence of insns, simulating the FP stack
432 contents, would not impose a fixed mapping from %fake to %st regs, and
433 hopefully could avoid most of the redundant reg-reg moves of the
436 We might as well make use of whatever unique FP facilities Intel have
437 chosen to bless us with (let's not be churlish, after all).
438 Hence GLDZ and GLD1. Bwahahahahahahaha!
440 LATER (10 Nov 2000): idiv gives problems with the register spiller,
441 because the spiller is simpleminded and because idiv has fixed uses of
442 %eax and %edx. Rather than make the spiller cleverer, we do away with
443 idiv, and instead have iquot and irem fake (integer) insns, which have
444 no operand register constraints -- ie, they behave like add, sub, mul.
445 The printer-outer transforms them to a sequence of real insns which does
446 the Right Thing (tm). As with the FP stuff, this gives ropey code,
447 but we don't care, since it doesn't get used much. We hope.
452 -- data Instr continues...
456 | MOV Size Operand Operand
457 | MOVZxL Size Operand Operand -- size is the size of operand 1
458 | MOVSxL Size Operand Operand -- size is the size of operand 1
460 -- Load effective address (also a very useful three-operand add instruction :-)
462 | LEA Size Operand Operand
466 | ADD Size Operand Operand
467 | SUB Size Operand Operand
468 | IMUL Size Operand Operand
470 -- Quotient and remainder. SEE comment above -- these are not
471 -- real x86 insns; instead they are expanded when printed
472 -- into a sequence of real insns.
474 | IQUOT Size Operand Operand
475 | IREM Size Operand Operand
477 -- Simple bit-twiddling.
479 | AND Size Operand Operand
480 | OR Size Operand Operand
481 | XOR Size Operand Operand
483 | NEGI Size Operand -- NEG instruction (name clash with Cond)
484 | SHL Size Imm Operand -- Only immediate shifts allowed
485 | SAR Size Imm Operand -- Only immediate shifts allowed
486 | SHR Size Imm Operand -- Only immediate shifts allowed
487 | BT Size Imm Operand
492 -- Note that we cheat by treating G{ABS,MOV,NEG} of doubles
493 -- as single instructions right up until we spit them out.
495 -- all the 3-operand fake fp insns are src1 src2 dst
496 -- and furthermore are constrained to be fp regs only.
497 -- IMPORTANT: keep is_G_insn up to date with any changes here
498 | GMOV Reg Reg -- src(fpreg), dst(fpreg)
499 | GLD Size MachRegsAddr Reg -- src, dst(fpreg)
500 | GST Size Reg MachRegsAddr -- src(fpreg), dst
502 | GLDZ Reg -- dst(fpreg)
503 | GLD1 Reg -- dst(fpreg)
505 | GFTOD Reg Reg -- src(fpreg), dst(fpreg)
506 | GFTOI Reg Reg -- src(fpreg), dst(intreg)
508 | GDTOF Reg Reg -- src(fpreg), dst(fpreg)
509 | GDTOI Reg Reg -- src(fpreg), dst(intreg)
511 | GITOF Reg Reg -- src(intreg), dst(fpreg)
512 | GITOD Reg Reg -- src(intreg), dst(fpreg)
514 | GADD Size Reg Reg Reg -- src1, src2, dst
515 | GDIV Size Reg Reg Reg -- src1, src2, dst
516 | GSUB Size Reg Reg Reg -- src1, src2, dst
517 | GMUL Size Reg Reg Reg -- src1, src2, dst
519 | GCMP Size Reg Reg -- src1, src2
521 | GABS Size Reg Reg -- src, dst
522 | GNEG Size Reg Reg -- src, dst
523 | GSQRT Size Reg Reg -- src, dst
524 | GSIN Size Reg Reg -- src, dst
525 | GCOS Size Reg Reg -- src, dst
526 | GTAN Size Reg Reg -- src, dst
528 | GFREE -- do ffree on all x86 regs; an ugly hack
531 | TEST Size Operand Operand
532 | CMP Size Operand Operand
544 | JMP DestInfo Operand -- possible dests, target
545 | JXX Cond CLabel -- target
550 | CLTD -- sign extend %eax into %edx:%eax
553 = OpReg Reg -- register
554 | OpImm Imm -- immediate value
555 | OpAddr MachRegsAddr -- memory reference
558 i386_insert_ffrees :: [Instr] -> [Instr]
559 i386_insert_ffrees insns
560 | any is_G_instr insns
561 = concatMap ffree_before_nonlocal_transfers insns
565 ffree_before_nonlocal_transfers insn
567 CALL _ -> [GFREE, insn]
568 -- Jumps to immediate labels are local
569 JMP _ (OpImm (ImmCLbl clbl)) | isAsmTemp clbl -> [insn]
570 -- If a jump mentions dests, it is a local jump thru
572 JMP (DestInfo _) _ -> [insn]
573 JMP _ _ -> [GFREE, insn]
577 -- if you ever add a new FP insn to the fake x86 FP insn set,
578 -- you must update this too
579 is_G_instr :: Instr -> Bool
582 GMOV _ _ -> True; GLD _ _ _ -> True; GST _ _ _ -> True;
583 GLDZ _ -> True; GLD1 _ -> True;
584 GFTOD _ _ -> True; GFTOI _ _ -> True;
585 GDTOF _ _ -> True; GDTOI _ _ -> True;
586 GITOF _ _ -> True; GITOD _ _ -> True;
587 GADD _ _ _ _ -> True; GDIV _ _ _ _ -> True
588 GSUB _ _ _ _ -> True; GMUL _ _ _ _ -> True
589 GCMP _ _ _ -> True; GABS _ _ _ -> True
590 GNEG _ _ _ -> True; GSQRT _ _ _ -> True
591 GSIN _ _ _ -> True; GCOS _ _ _ -> True; GTAN _ _ _ -> True;
592 GFREE -> panic "is_G_instr: GFREE (!)"
595 #endif {- i386_TARGET_ARCH -}
599 #if sparc_TARGET_ARCH
601 -- data Instr continues...
605 | LD Size MachRegsAddr Reg -- size, src, dst
606 | ST Size Reg MachRegsAddr -- size, src, dst
610 | ADD Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
611 | SUB Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
613 -- Simple bit-twiddling.
615 | AND Bool Reg RI Reg -- cc?, src1, src2, dst
616 | ANDN Bool Reg RI Reg -- cc?, src1, src2, dst
617 | OR Bool Reg RI Reg -- cc?, src1, src2, dst
618 | ORN Bool Reg RI Reg -- cc?, src1, src2, dst
619 | XOR Bool Reg RI Reg -- cc?, src1, src2, dst
620 | XNOR Bool Reg RI Reg -- cc?, src1, src2, dst
621 | SLL Reg RI Reg -- src1, src2, dst
622 | SRL Reg RI Reg -- src1, src2, dst
623 | SRA Reg RI Reg -- src1, src2, dst
624 | SETHI Imm Reg -- src, dst
625 | NOP -- Really SETHI 0, %g0, but worth an alias
629 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
630 -- right up until we spit them out.
632 | FABS Size Reg Reg -- src dst
633 | FADD Size Reg Reg Reg -- src1, src2, dst
634 | FCMP Bool Size Reg Reg -- exception?, src1, src2, dst
635 | FDIV Size Reg Reg Reg -- src1, src2, dst
636 | FMOV Size Reg Reg -- src, dst
637 | FMUL Size Reg Reg Reg -- src1, src2, dst
638 | FNEG Size Reg Reg -- src, dst
639 | FSQRT Size Reg Reg -- src, dst
640 | FSUB Size Reg Reg Reg -- src1, src2, dst
641 | FxTOy Size Size Reg Reg -- src, dst
645 | BI Cond Bool Imm -- cond, annul?, target
646 | BF Cond Bool Imm -- cond, annul?, target
648 | JMP DestInfo MachRegsAddr -- target
649 | CALL Imm Int Bool -- target, args, terminal
656 riZero (RIImm (ImmInt 0)) = True
657 riZero (RIImm (ImmInteger 0)) = True
658 riZero (RIReg (RealReg 0)) = True
661 -- Calculate the effective address which would be used by the
662 -- corresponding fpRel sequence. fpRel is in MachRegs.lhs,
663 -- alas -- can't have fpRelEA here because of module dependencies.
664 fpRelEA :: Int -> Reg -> Instr
666 = ADD False False fp (RIImm (ImmInt (n * BYTES_PER_WORD))) dst
668 -- Code to shift the stack pointer by n words.
669 moveSp :: Int -> Instr
671 = ADD False False sp (RIImm (ImmInt (n * BYTES_PER_WORD))) sp
673 -- Produce the second-half-of-a-double register given the first half.
675 fPair (RealReg n) | n >= 32 && n `mod` 2 == 0 = RealReg (n+1)
676 fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
677 #endif {- sparc_TARGET_ARCH -}