2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "HsVersions.h"
14 #include "nativeGen/NCG.h"
47 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
50 , eax, ebx, ecx, edx, esi, esp
51 , st0, st1, st2, st3, st4, st5, st6, st7
56 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
62 #if __GLASGOW_HASKELL__ >= 202
69 import AbsCSyn ( MagicId(..) )
70 import AbsCUtils ( magicIdPrimRep )
71 import CLabel ( CLabel )
72 import Outputable ( Outputable(..) )
73 import Pretty ( Doc, text, rational )
74 import PrimOp ( PrimOp(..) )
75 import PrimRep ( PrimRep(..) )
76 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
79 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
80 Unique{-instance Ord3-}, Uniquable(..)
82 import UniqSupply ( getUnique, returnUs, thenUs, SYN_IE(UniqSM) )
83 import Util ( panic, Ord3(..) )
86 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
91 | ImmInteger Integer -- Sigh.
92 | ImmCLbl CLabel -- AbstractC Label (with baggage)
93 | ImmLab Doc -- Simple string label (underscore-able)
94 | ImmLit Doc -- Simple string
96 | LO Imm -- Possible restrictions...
99 strImmLit s = ImmLit (text s)
102 IF_ARCH_alpha({-prepend nothing-}
103 ,IF_ARCH_i386( '0' : 'd' :
104 ,IF_ARCH_sparc('0' : 'r' :,)))
108 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
112 #if alpha_TARGET_ARCH
119 = Address Base Index Displacement
122 type Base = Maybe Reg
123 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
124 type Displacement = Imm
127 #if sparc_TARGET_ARCH
132 addrOffset :: Address -> Int -> Maybe Address
136 #if alpha_TARGET_ARCH
137 _ -> panic "MachMisc.addrOffset not defined for Alpha"
140 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
141 Address r i (ImmInt n) -> Just (Address r i (ImmInt (n + off)))
142 Address r i (ImmInteger n)
143 -> Just (Address r i (ImmInt (fromInteger (n + toInteger off))))
146 #if sparc_TARGET_ARCH
147 AddrRegImm r (ImmInt n)
148 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
149 | otherwise -> Nothing
152 AddrRegImm r (ImmInteger n)
153 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
154 | otherwise -> Nothing
155 where n2 = n + toInteger off
157 AddrRegReg r (FixedReg ILIT(0))
158 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
159 | otherwise -> Nothing
166 #if alpha_TARGET_ARCH
168 fits8Bits :: Integer -> Bool
169 fits8Bits i = i >= -256 && i < 256
173 #if sparc_TARGET_ARCH
175 fits13Bits :: Int -> Bool
178 fits13Bits :: Integer -> Bool
181 fits13Bits :: Integral a => a -> Bool
182 fits13Bits x = x >= -4096 && x < 4096
186 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
191 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
193 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
194 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
195 The rest are either in real machine registers or stored as offsets
199 data RegLoc = Save StixTree | Always StixTree
202 Trees for register save locations:
204 saveLoc :: MagicId -> StixTree
206 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
210 stgReg :: MagicId -> RegLoc
213 = case (magicIdRegMaybe x) of
214 Just _ -> Save nonReg
215 Nothing -> Always nonReg
217 offset = baseRegOffset x
219 baseLoc = case (magicIdRegMaybe BaseReg) of
220 Just _ -> StReg (StixMagicId BaseReg)
221 Nothing -> sStLitLbl SLIT("MainRegTable")
224 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
225 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
226 BaseReg -> sStLitLbl SLIT("MainRegTable")
227 -- these Hp&HpLim cases perhaps should
228 -- not be here for i386 (???) WDP 96/03
229 #ifndef i386_TARGET_ARCH
230 -- Yup, Hp&HpLim are not mapped into registers for x86's at the mo, so
231 -- fetching Hp off BaseReg is the sensible option, since that's
232 -- where gcc generated code stuffs/expects it (RTBL_Hp & RTBL_HpLim).
234 -- In fact, why use StorageMgrInfo at all?
235 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
236 HpLim -> StInd PtrRep (sStLitLbl
237 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
239 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
240 StInt (1*BYTES_PER_WORD)])
242 r2 = VanillaReg PtrRep ILIT(2)
243 infoptr = case (stgReg r2) of
245 Save _ -> StReg (StixMagicId r2)
246 _ -> StInd (magicIdPrimRep x)
247 (StPrim IntAddOp [baseLoc,
248 StInt (toInteger (offset*BYTES_PER_WORD))])
251 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
253 @spRel@ gives us a stack relative addressing mode for volatile
254 temporaries and for excess call arguments. @fpRel@, where
255 applicable, is the same but for the frame pointer.
258 spRel :: Int -- desired stack offset in words, positive or negative
263 = Address (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
265 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
268 #if sparc_TARGET_ARCH
269 fpRel :: Int -> Address
270 -- Duznae work for offsets greater than 13 bits; we just hope for
273 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
277 %************************************************************************
279 \subsection[Reg]{Real registers}
281 %************************************************************************
283 Static Registers correspond to actual machine registers. These should
284 be avoided until the last possible moment.
286 Dynamic registers are allocated on the fly, usually to represent a single
287 value in the abstract assembly code (i.e. dynamic registers are usually
288 single assignment). Ultimately, they are mapped to available machine
289 registers before spitting out the code.
293 = FixedReg FAST_INT -- A pre-allocated machine register
295 | MappedReg FAST_INT -- A dynamically allocated machine register
297 | MemoryReg Int PrimRep -- A machine "register" actually held in
298 -- a memory allocated table of
299 -- registers which didn't fit in real
302 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
303 -- always mapped to one of the earlier
304 -- two (?) before we're done.
305 mkReg :: Unique -> PrimRep -> Reg
308 getNewRegNCG :: PrimRep -> UniqSM Reg
310 = getUnique `thenUs` \ u ->
311 returnUs (UnmappedReg u pk)
313 instance Text Reg where
314 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
315 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
316 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
317 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
320 instance Outputable Reg where
321 ppr sty r = text (show r)
324 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
325 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
326 cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i'
327 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u'
329 = let tag1 = tagReg r1
332 if tag1 _LT_ tag2 then LT_ else GT_
334 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
335 tagReg (MappedReg _) = ILIT(2)
336 tagReg (MemoryReg _ _) = ILIT(3)
337 tagReg (UnmappedReg _ _) = ILIT(4)
339 cmp_i :: Int -> Int -> TAG_
340 cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_
342 cmp_ihash :: FAST_INT -> FAST_INT -> TAG_
343 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_
345 instance Ord3 Reg where
348 instance Eq Reg where
349 a == b = case (a `cmp` b) of { EQ_ -> True; _ -> False }
350 a /= b = case (a `cmp` b) of { EQ_ -> False; _ -> True }
352 instance Ord Reg where
353 a <= b = case (a `cmp` b) of { LT_ -> True; EQ_ -> True; GT__ -> False }
354 a < b = case (a `cmp` b) of { LT_ -> True; EQ_ -> False; GT__ -> False }
355 a >= b = case (a `cmp` b) of { LT_ -> False; EQ_ -> True; GT__ -> True }
356 a > b = case (a `cmp` b) of { LT_ -> False; EQ_ -> False; GT__ -> True }
357 _tagCmp a b = case (a `cmp` b) of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT }
359 instance Uniquable Reg where
360 uniqueOf (UnmappedReg u _) = u
361 uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i)
362 uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i)
363 uniqueOf (MemoryReg i _) = mkPseudoUnique3 i
369 realReg :: RegNo -> Reg
371 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
373 extractMappedRegNos :: [Reg] -> [RegNo]
375 extractMappedRegNos regs
378 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
379 ex _ acc = acc -- leave it out
382 ** Machine-specific Reg stuff: **
384 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
385 point registers. The mapping of STG registers to alpha machine registers
386 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
388 #if alpha_TARGET_ARCH
392 v0, f0, ra, pv, gp, sp, zeroh :: Reg
394 f0 = realReg (fReg 0)
395 ra = FixedReg ILIT(26)
397 gp = FixedReg ILIT(29)
398 sp = FixedReg ILIT(30)
399 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
401 t9, t10, t11, t12 :: Reg
409 Intel x86 architecture:
410 - All registers except 7 (esp) are available for use.
411 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
412 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
413 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
414 - Registers 8-15 hold extended floating point values.
418 gReg,fReg :: Int -> Int
422 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
423 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
424 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
425 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
426 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
427 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
428 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
429 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
430 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
431 st0 = realReg (fReg 0)
432 st1 = realReg (fReg 1)
433 st2 = realReg (fReg 2)
434 st3 = realReg (fReg 3)
435 st4 = realReg (fReg 4)
436 st5 = realReg (fReg 5)
437 st6 = realReg (fReg 6)
438 st7 = realReg (fReg 7)
443 The SPARC has 64 registers of interest; 32 integer registers and 32
444 floating point registers. The mapping of STG registers to SPARC
445 machine registers is defined in StgRegs.h. We are, of course,
446 prepared for any eventuality.
449 #if sparc_TARGET_ARCH
451 gReg,lReg,iReg,oReg,fReg :: Int -> Int
459 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
460 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
462 g0, fp, sp, o0, f0 :: Reg
463 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
464 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
465 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
466 o0 = realReg (oReg 0)
467 f0 = realReg (fReg 0)
472 Redefine the literals used for machine-registers with non-numeric
473 names in the header files. Gag me with a spoon, eh?
475 #if alpha_TARGET_ARCH
527 #if sparc_TARGET_ARCH
596 baseRegOffset :: MagicId -> Int
598 baseRegOffset StkOReg = OFFSET_StkO
599 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
600 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
601 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
602 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
603 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
604 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
605 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
606 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
607 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
608 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
609 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
610 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
611 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
612 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
613 baseRegOffset TagReg = OFFSET_Tag
614 baseRegOffset RetReg = OFFSET_Ret
615 baseRegOffset SpA = OFFSET_SpA
616 baseRegOffset SuA = OFFSET_SuA
617 baseRegOffset SpB = OFFSET_SpB
618 baseRegOffset SuB = OFFSET_SuB
619 baseRegOffset Hp = OFFSET_Hp
620 baseRegOffset HpLim = OFFSET_HpLim
621 baseRegOffset LivenessReg = OFFSET_Liveness
623 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
624 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
625 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
626 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
627 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
632 callerSaves :: MagicId -> Bool
634 #ifdef CALLER_SAVES_Base
635 callerSaves BaseReg = True
637 #ifdef CALLER_SAVES_StkO
638 callerSaves StkOReg = True
640 #ifdef CALLER_SAVES_R1
641 callerSaves (VanillaReg _ ILIT(1)) = True
643 #ifdef CALLER_SAVES_R2
644 callerSaves (VanillaReg _ ILIT(2)) = True
646 #ifdef CALLER_SAVES_R3
647 callerSaves (VanillaReg _ ILIT(3)) = True
649 #ifdef CALLER_SAVES_R4
650 callerSaves (VanillaReg _ ILIT(4)) = True
652 #ifdef CALLER_SAVES_R5
653 callerSaves (VanillaReg _ ILIT(5)) = True
655 #ifdef CALLER_SAVES_R6
656 callerSaves (VanillaReg _ ILIT(6)) = True
658 #ifdef CALLER_SAVES_R7
659 callerSaves (VanillaReg _ ILIT(7)) = True
661 #ifdef CALLER_SAVES_R8
662 callerSaves (VanillaReg _ ILIT(8)) = True
664 #ifdef CALLER_SAVES_FltReg1
665 callerSaves (FloatReg ILIT(1)) = True
667 #ifdef CALLER_SAVES_FltReg2
668 callerSaves (FloatReg ILIT(2)) = True
670 #ifdef CALLER_SAVES_FltReg3
671 callerSaves (FloatReg ILIT(3)) = True
673 #ifdef CALLER_SAVES_FltReg4
674 callerSaves (FloatReg ILIT(4)) = True
676 #ifdef CALLER_SAVES_DblReg1
677 callerSaves (DoubleReg ILIT(1)) = True
679 #ifdef CALLER_SAVES_DblReg2
680 callerSaves (DoubleReg ILIT(2)) = True
682 #ifdef CALLER_SAVES_Tag
683 callerSaves TagReg = True
685 #ifdef CALLER_SAVES_Ret
686 callerSaves RetReg = True
688 #ifdef CALLER_SAVES_SpA
689 callerSaves SpA = True
691 #ifdef CALLER_SAVES_SuA
692 callerSaves SuA = True
694 #ifdef CALLER_SAVES_SpB
695 callerSaves SpB = True
697 #ifdef CALLER_SAVES_SuB
698 callerSaves SuB = True
700 #ifdef CALLER_SAVES_Hp
701 callerSaves Hp = True
703 #ifdef CALLER_SAVES_HpLim
704 callerSaves HpLim = True
706 #ifdef CALLER_SAVES_Liveness
707 callerSaves LivenessReg = True
709 #ifdef CALLER_SAVES_StdUpdRetVec
710 callerSaves StdUpdRetVecReg = True
712 #ifdef CALLER_SAVES_StkStub
713 callerSaves StkStubReg = True
715 callerSaves _ = False
719 magicIdRegMaybe :: MagicId -> Maybe Reg
722 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
725 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
728 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
731 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
734 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
737 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
740 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
743 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
746 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
749 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
752 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
755 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
758 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
761 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
764 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
767 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
770 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
773 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
776 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
779 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
782 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
785 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
788 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
791 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
794 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
796 #ifdef REG_StdUpdRetVec
797 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
800 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
802 magicIdRegMaybe _ = Nothing
805 %************************************************************************
807 \subsection{Free, reserved, call-clobbered, and argument registers}
809 %************************************************************************
811 @freeRegs@ is the list of registers we can use in register allocation.
812 @freeReg@ (below) says if a particular register is free.
814 With a per-instruction clobber list, we might be able to get some of
815 these back, but it's probably not worth the hassle.
817 @callClobberedRegs@ ... the obvious.
819 @argRegs@: assuming a call with N arguments, what registers will be
820 used to hold arguments? (NB: it doesn't know whether the arguments
821 are integer or floating-point...)
824 reservedRegs :: [RegNo]
826 #if alpha_TARGET_ARCH
827 = [NCG_Reserved_I1, NCG_Reserved_I2,
828 NCG_Reserved_F1, NCG_Reserved_F2]
831 = [{-certainly cannot afford any!-}]
833 #if sparc_TARGET_ARCH
834 = [NCG_Reserved_I1, NCG_Reserved_I2,
835 NCG_Reserved_F1, NCG_Reserved_F2,
836 NCG_Reserved_D1, NCG_Reserved_D2]
839 -------------------------------
842 = freeMappedRegs IF_ARCH_alpha( [0..63],
843 IF_ARCH_i386( [0..15],
844 IF_ARCH_sparc( [0..63],)))
846 -------------------------------
847 callClobberedRegs :: [Reg]
850 #if alpha_TARGET_ARCH
851 [0, 1, 2, 3, 4, 5, 6, 7, 8,
852 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
853 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
854 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
855 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
856 #endif {- alpha_TARGET_ARCH -}
859 #endif {- i386_TARGET_ARCH -}
860 #if sparc_TARGET_ARCH
862 [oReg i | i <- [0..5]] ++
863 [gReg i | i <- [1..7]] ++
864 [fReg i | i <- [0..31]] )
865 #endif {- sparc_TARGET_ARCH -}
867 -------------------------------
868 argRegs :: Int -> [Reg]
871 #if alpha_TARGET_ARCH
872 argRegs 1 = freeMappedRegs [16, fReg 16]
873 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
874 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
875 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
876 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
877 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
878 #endif {- alpha_TARGET_ARCH -}
880 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
881 #endif {- i386_TARGET_ARCH -}
882 #if sparc_TARGET_ARCH
883 argRegs 1 = freeMappedRegs (map oReg [0])
884 argRegs 2 = freeMappedRegs (map oReg [0,1])
885 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
886 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
887 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
888 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
889 #endif {- sparc_TARGET_ARCH -}
890 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
892 -------------------------------
894 #if alpha_TARGET_ARCH
895 allArgRegs :: [(Reg, Reg)]
897 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
898 #endif {- alpha_TARGET_ARCH -}
900 #if sparc_TARGET_ARCH
903 allArgRegs = map realReg [oReg i | i <- [0..5]]
904 #endif {- sparc_TARGET_ARCH -}
906 -------------------------------
907 freeMappedRegs :: [Int] -> [Reg]
913 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
917 freeReg :: FAST_INT -> FAST_BOOL
919 #if alpha_TARGET_ARCH
920 freeReg ILIT(26) = _FALSE_ -- return address (ra)
921 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
922 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
923 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
924 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
925 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
929 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
932 #if sparc_TARGET_ARCH
933 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
934 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
935 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
936 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
937 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
938 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
942 freeReg ILIT(REG_Base) = _FALSE_
945 freeReg ILIT(REG_StkO) = _FALSE_
948 freeReg ILIT(REG_R1) = _FALSE_
951 freeReg ILIT(REG_R2) = _FALSE_
954 freeReg ILIT(REG_R3) = _FALSE_
957 freeReg ILIT(REG_R4) = _FALSE_
960 freeReg ILIT(REG_R5) = _FALSE_
963 freeReg ILIT(REG_R6) = _FALSE_
966 freeReg ILIT(REG_R7) = _FALSE_
969 freeReg ILIT(REG_R8) = _FALSE_
972 freeReg ILIT(REG_Flt1) = _FALSE_
975 freeReg ILIT(REG_Flt2) = _FALSE_
978 freeReg ILIT(REG_Flt3) = _FALSE_
981 freeReg ILIT(REG_Flt4) = _FALSE_
984 freeReg ILIT(REG_Dbl1) = _FALSE_
987 freeReg ILIT(REG_Dbl2) = _FALSE_
990 freeReg ILIT(REG_Tag) = _FALSE_
993 freeReg ILIT(REG_Ret) = _FALSE_
996 freeReg ILIT(REG_SpA) = _FALSE_
999 freeReg ILIT(REG_SuA) = _FALSE_
1002 freeReg ILIT(REG_SpB) = _FALSE_
1005 freeReg ILIT(REG_SuB) = _FALSE_
1008 freeReg ILIT(REG_Hp) = _FALSE_
1011 freeReg ILIT(REG_HpLim) = _FALSE_
1014 freeReg ILIT(REG_Liveness) = _FALSE_
1016 #ifdef REG_StdUpdRetVec
1017 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1020 freeReg ILIT(REG_StkStub) = _FALSE_
1024 -- we hang onto two double regs for dedicated
1025 -- use; this is not necessary on Alphas and
1026 -- may not be on other non-SPARCs.
1028 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1031 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1033 | otherwise = _TRUE_