1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 EABase(..), EAIndex(..),
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 EABase(..), EAIndex(..), ripRel,
56 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 r8, r9, r10, r11, r12, r13, r14, r15,
59 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
60 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
62 addrModeRegs, allFPArgRegs,
66 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
67 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
69 #if powerpc_TARGET_ARCH
78 #include "HsVersions.h"
81 # define STOLEN_X86_REGS 4
82 -- HACK: go for the max
85 #include "../includes/MachRegs.h"
88 import MachOp ( MachRep(..) )
90 import CLabel ( CLabel, mkMainCapabilityLabel )
91 import Unique ( Unique )
93 import Outputable ( Outputable(..), pprPanic, panic )
94 import qualified Outputable
99 #if powerpc_TARGET_ARCH
100 #if __GLASGOW_HASKELL__ >= 504
101 import Data.Word ( Word8, Word16, Word32 )
102 import Data.Int ( Int8, Int16, Int32 )
104 import Word ( Word8, Word16, Word32 )
105 import Int ( Int8, Int16, Int32 )
109 -- -----------------------------------------------------------------------------
114 | ImmInteger Integer -- Sigh.
115 | ImmCLbl CLabel -- AbstractC Label (with baggage)
116 | ImmLit Doc -- Simple string
117 | ImmIndex CLabel Int
120 | ImmConstantSum Imm Imm
121 | ImmConstantDiff Imm Imm
122 #if sparc_TARGET_ARCH
123 | LO Imm {- Possible restrictions... -}
126 #if powerpc_TARGET_ARCH
129 | HA Imm {- high halfword adjusted -}
131 strImmLit s = ImmLit (text s)
133 litToImm :: CmmLit -> Imm
134 litToImm (CmmInt i _) = ImmInteger i
135 litToImm (CmmFloat f F32) = ImmFloat f
136 litToImm (CmmFloat f F64) = ImmDouble f
137 litToImm (CmmLabel l) = ImmCLbl l
138 litToImm (CmmLabelOff l off) = ImmIndex l off
139 litToImm (CmmLabelDiffOff l1 l2 off)
141 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
144 -- -----------------------------------------------------------------------------
148 #if alpha_TARGET_ARCH
154 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
155 = AddrBaseIndex EABase EAIndex Displacement
158 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
159 data EAIndex = EAIndexNone | EAIndex Reg Int
160 type Displacement = Imm
163 #if sparc_TARGET_ARCH
168 #if powerpc_TARGET_ARCH
173 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
174 addrModeRegs :: AddrMode -> [Reg]
175 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
177 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
178 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
183 addrOffset :: AddrMode -> Int -> Maybe AddrMode
187 #if alpha_TARGET_ARCH
188 _ -> panic "MachMisc.addrOffset not defined for Alpha"
190 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
191 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
193 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
194 AddrBaseIndex r i (ImmInteger n)
195 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
197 AddrBaseIndex r i (ImmCLbl lbl)
198 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
200 AddrBaseIndex r i (ImmIndex lbl ix)
201 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
203 _ -> Nothing -- in theory, shouldn't happen
205 #if sparc_TARGET_ARCH
206 AddrRegImm r (ImmInt n)
207 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
208 | otherwise -> Nothing
211 AddrRegImm r (ImmInteger n)
212 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
213 | otherwise -> Nothing
214 where n2 = n + toInteger off
216 AddrRegReg r (RealReg 0)
217 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
218 | otherwise -> Nothing
222 #if powerpc_TARGET_ARCH
223 AddrRegImm r (ImmInt n)
224 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
225 | otherwise -> Nothing
228 AddrRegImm r (ImmInteger n)
229 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
230 | otherwise -> Nothing
231 where n2 = n + toInteger off
237 #if alpha_TARGET_ARCH
239 fits8Bits :: Integer -> Bool
240 fits8Bits i = i >= -256 && i < 256
244 #if sparc_TARGET_ARCH
246 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
247 fits13Bits :: Integral a => a -> Bool
248 fits13Bits x = x >= -4096 && x < 4096
252 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
253 ++show i++");\nprobably because of large constant data structures;" ++
254 "\nworkaround: use -fvia-C on this module.\n")
258 #if powerpc_TARGET_ARCH
259 fits16Bits :: Integral a => a -> Bool
260 fits16Bits x = x >= -32768 && x < 32768
262 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
264 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
266 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
267 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
268 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
269 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
270 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
271 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
273 narrowed = narrow rep signed
276 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
277 | otherwise = Nothing
279 | narrowed >= 0 && narrowed < 65536 = Just narrowed
280 | otherwise = Nothing
281 toI16 _ _ = Just narrowed
285 -- @spRel@ gives us a stack relative addressing mode for volatile
286 -- temporaries and for excess call arguments. @fpRel@, where
287 -- applicable, is the same but for the frame pointer.
289 spRel :: Int -- desired stack offset in words, positive or negative
293 #if defined(i386_TARGET_ARCH)
294 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
295 #elif defined(x86_64_TARGET_ARCH)
296 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
298 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
301 #if sparc_TARGET_ARCH
302 fpRel :: Int -> AddrMode
303 -- Duznae work for offsets greater than 13 bits; we just hope for
306 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
309 #if x86_64_TARGET_ARCH
310 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
313 -- -----------------------------------------------------------------------------
316 -- We map STG registers onto appropriate CmmExprs. Either they map
317 -- to real machine registers or stored as offsets from BaseReg. Given
318 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
319 -- register it is in, on this platform, or a StixExpr denoting the
320 -- address in the register table holding it. get_MagicId_addr always
321 -- produces the register table address for it.
323 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
324 get_GlobalReg_addr :: GlobalReg -> CmmExpr
325 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
327 get_GlobalReg_reg_or_addr mid
328 = case globalRegMaybe mid of
330 Nothing -> Right (get_GlobalReg_addr mid)
332 get_GlobalReg_addr BaseReg = regTableOffset 0
333 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
334 (globalRegRep mid) (baseRegOffset mid)
336 -- Calculate a literal representing an offset into the register table.
337 -- Used when we don't have an actual BaseReg to offset from.
339 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
341 get_Regtable_addr_from_offset rep offset
342 = case globalRegMaybe BaseReg of
343 Nothing -> regTableOffset offset
344 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
346 -- ---------------------------------------------------------------------------
349 -- RealRegs are machine regs which are available for allocation, in
350 -- the usual way. We know what class they are, because that's part of
351 -- the processor's architecture.
353 -- VirtualRegs are virtual registers. The register allocator will
354 -- eventually have to map them into RealRegs, or into spill slots.
355 -- VirtualRegs are allocated on the fly, usually to represent a single
356 -- value in the abstract assembly code (i.e. dynamic registers are
357 -- usually single assignment). With the new register allocator, the
358 -- single assignment restriction isn't necessary to get correct code,
359 -- although a better register allocation will result if single
360 -- assignment is used -- because the allocator maps a VirtualReg into
361 -- a single RealReg, even if the VirtualReg has multiple live ranges.
363 -- Virtual regs can be of either class, so that info is attached.
365 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
366 -- when supplied with the vreg for the lower-half of the quantity.
367 -- (NB. Not reversible).
368 getHiVRegFromLo (VirtualRegI u)
369 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
370 getHiVRegFromLo other
371 = pprPanic "getHiVRegFromLo" (ppr other)
382 = RealReg {-# UNPACK #-} !RegNo
383 | VirtualRegI {-# UNPACK #-} !Unique
384 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
385 | VirtualRegF {-# UNPACK #-} !Unique
386 | VirtualRegD {-# UNPACK #-} !Unique
389 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
390 -- in the register allocator.
391 instance Uniquable Reg where
392 getUnique (RealReg i) = mkUnique 'C' i
393 getUnique (VirtualRegI u) = u
394 getUnique (VirtualRegHi u) = u
395 getUnique (VirtualRegF u) = u
396 getUnique (VirtualRegD u) = u
398 mkVReg :: Unique -> MachRep -> Reg
401 #if sparc_TARGET_ARCH
407 other -> VirtualRegI u
409 isVirtualReg :: Reg -> Bool
410 isVirtualReg (RealReg _) = False
411 isVirtualReg (VirtualRegI _) = True
412 isVirtualReg (VirtualRegHi _) = True
413 isVirtualReg (VirtualRegF _) = True
414 isVirtualReg (VirtualRegD _) = True
416 isRealReg :: Reg -> Bool
417 isRealReg = not . isVirtualReg
419 instance Show Reg where
420 show (RealReg i) = showReg i
421 show (VirtualRegI u) = "%vI_" ++ show u
422 show (VirtualRegHi u) = "%vHi_" ++ show u
423 show (VirtualRegF u) = "%vF_" ++ show u
424 show (VirtualRegD u) = "%vD_" ++ show u
426 instance Outputable Reg where
427 ppr r = Outputable.text (show r)
430 -- -----------------------------------------------------------------------------
431 -- Machine-specific register stuff
433 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
434 -- point registers. The mapping of STG registers to alpha machine registers
435 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
437 #if alpha_TARGET_ARCH
441 v0, f0, ra, pv, gp, sp, zeroh :: Reg
443 f0 = realReg (fReg 0)
444 ra = FixedReg ILIT(26)
446 gp = FixedReg ILIT(29)
447 sp = FixedReg ILIT(30)
448 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
450 t9, t10, t11, t12 :: Reg
458 Intel x86 architecture:
459 - All registers except 7 (esp) are available for use.
460 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
461 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
462 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
463 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
464 fp registers, and 3-operand insns for them, and we translate this into
465 real stack-based x86 fp code after register allocation.
467 The fp registers are all Double registers; we don't have any RcFloat class
468 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
474 fake0, fake1, fake2, fake3, fake4, fake5,
475 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
491 -- On x86, we might want to have an 8-bit RegClass, which would
492 -- contain just regs 1-4 (the others don't have 8-bit versions).
493 -- However, we can get away without this at the moment because the
494 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
495 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
496 regClass (VirtualRegI u) = RcInteger
497 regClass (VirtualRegHi u) = RcInteger
498 regClass (VirtualRegD u) = RcDouble
499 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
500 (ppr (VirtualRegF u))
503 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
504 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
506 showReg :: RegNo -> String
508 = if n >= 0 && n < 14
510 else "%unknown_x86_real_reg_" ++ show n
515 AMD x86_64 architecture:
516 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
517 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
518 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
522 #if x86_64_TARGET_ARCH
524 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
525 r8, r9, r10, r11, r12, r13, r14, r15,
526 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
527 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
562 -- so we can re-use some x86 code:
572 xmm n = RealReg (16+n)
574 -- On x86, we might want to have an 8-bit RegClass, which would
575 -- contain just regs 1-4 (the others don't have 8-bit versions).
576 -- However, we can get away without this at the moment because the
577 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
578 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
579 regClass (VirtualRegI u) = RcInteger
580 regClass (VirtualRegHi u) = RcInteger
581 regClass (VirtualRegD u) = RcDouble
582 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
583 (ppr (VirtualRegF u))
586 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
588 showReg :: RegNo -> String
590 | n >= 16 = "%xmm" ++ show n
591 | n >= 8 = "%r" ++ show n
592 | otherwise = regNames !! n
597 The SPARC has 64 registers of interest; 32 integer registers and 32
598 floating point registers. The mapping of STG registers to SPARC
599 machine registers is defined in StgRegs.h. We are, of course,
600 prepared for any eventuality.
602 The whole fp-register pairing thing on sparcs is a huge nuisance. See
603 fptools/ghc/includes/MachRegs.h for a description of what's going on
607 #if sparc_TARGET_ARCH
609 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
616 nCG_FirstFloatReg :: RegNo
617 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
619 regClass (VirtualRegI u) = RcInteger
620 regClass (VirtualRegF u) = RcFloat
621 regClass (VirtualRegD u) = RcDouble
622 regClass (RealReg i) | i < 32 = RcInteger
623 | i < nCG_FirstFloatReg = RcDouble
624 | otherwise = RcFloat
626 showReg :: RegNo -> String
628 | n >= 0 && n < 8 = "%g" ++ show n
629 | n >= 8 && n < 16 = "%o" ++ show (n-8)
630 | n >= 16 && n < 24 = "%l" ++ show (n-16)
631 | n >= 24 && n < 32 = "%i" ++ show (n-24)
632 | n >= 32 && n < 64 = "%f" ++ show (n-32)
633 | otherwise = "%unknown_sparc_real_reg_" ++ show n
635 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
637 f6 = RealReg (fReg 6)
638 f8 = RealReg (fReg 8)
639 f22 = RealReg (fReg 22)
640 f26 = RealReg (fReg 26)
641 f27 = RealReg (fReg 27)
644 -- g0 is useful for codegen; is always zero, and writes to it vanish.
645 g0 = RealReg (gReg 0)
646 g1 = RealReg (gReg 1)
647 g2 = RealReg (gReg 2)
649 -- FP, SP, int and float return (from C) regs.
650 fp = RealReg (iReg 6)
651 sp = RealReg (oReg 6)
652 o0 = RealReg (oReg 0)
653 o1 = RealReg (oReg 1)
654 f0 = RealReg (fReg 0)
655 f1 = RealReg (fReg 1)
660 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
664 #if powerpc_TARGET_ARCH
668 regClass (VirtualRegI u) = RcInteger
669 regClass (VirtualRegHi u) = RcInteger
670 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
671 (ppr (VirtualRegF u))
672 regClass (VirtualRegD u) = RcDouble
673 regClass (RealReg i) | i < 32 = RcInteger
674 | otherwise = RcDouble
676 showReg :: RegNo -> String
678 | n >= 0 && n <= 31 = "%r" ++ show n
679 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
680 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
687 f1 = RealReg $ fReg 1
688 f20 = RealReg $ fReg 20
689 f21 = RealReg $ fReg 21
693 Redefine the literals used for machine-registers with non-numeric
694 names in the header files. Gag me with a spoon, eh?
697 #if alpha_TARGET_ARCH
748 #if x86_64_TARGET_ARCH
783 #if sparc_TARGET_ARCH
851 #if powerpc_TARGET_ARCH
885 #ifdef darwin_TARGET_OS
955 -- allMachRegs is the complete set of machine regs.
956 allMachRegNos :: [RegNo]
958 = IF_ARCH_alpha( [0..63],
959 IF_ARCH_i386( [0..13],
960 IF_ARCH_x86_64( [0..31],
961 IF_ARCH_sparc( ([0..31]
962 ++ [f0,f2 .. nCG_FirstFloatReg-1]
963 ++ [nCG_FirstFloatReg .. f31]),
964 IF_ARCH_powerpc([0..63],
967 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
968 -- i.e., these are the regs for which we are prepared to allow the
969 -- register allocator to attempt to map VRegs to.
970 allocatableRegs :: [RegNo]
972 = let isFree i = isFastTrue (freeReg i)
973 in filter isFree allMachRegNos
975 -- these are the regs which we cannot assume stay alive over a
977 callClobberedRegs :: [Reg]
980 #if alpha_TARGET_ARCH
981 [0, 1, 2, 3, 4, 5, 6, 7, 8,
982 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
983 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
984 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
985 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
986 #endif /* alpha_TARGET_ARCH */
988 -- caller-saves registers
989 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
990 #endif /* i386_TARGET_ARCH */
991 #if x86_64_TARGET_ARCH
992 -- caller-saves registers
993 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
994 -- all xmm regs are caller-saves
995 #endif /* x86_64_TARGET_ARCH */
996 #if sparc_TARGET_ARCH
999 [oReg i | i <- [0..5]] ++
1000 [gReg i | i <- [1..7]] ++
1001 [fReg i | i <- [0..31]] )
1002 #endif /* sparc_TARGET_ARCH */
1003 #if powerpc_TARGET_ARCH
1004 #if darwin_TARGET_OS
1005 map RealReg (0:[2..12] ++ map fReg [0..13])
1006 #elif linux_TARGET_OS
1007 map RealReg (0:[2..13] ++ map fReg [0..13])
1009 #endif /* powerpc_TARGET_ARCH */
1012 -- argRegs is the set of regs which are read for an n-argument call to C.
1013 -- For archs which pass all args on the stack (x86), is empty.
1014 -- Sparc passes up to the first 6 args in regs.
1015 -- Dunno about Alpha.
1016 argRegs :: RegNo -> [Reg]
1018 #if i386_TARGET_ARCH
1019 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1022 #if x86_64_TARGET_ARCH
1023 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1026 #if alpha_TARGET_ARCH
1028 argRegs 1 = freeMappedRegs [16, fReg 16]
1029 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1030 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1031 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1032 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1033 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1034 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1035 #endif /* alpha_TARGET_ARCH */
1037 #if sparc_TARGET_ARCH
1039 argRegs 1 = map (RealReg . oReg) [0]
1040 argRegs 2 = map (RealReg . oReg) [0,1]
1041 argRegs 3 = map (RealReg . oReg) [0,1,2]
1042 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1043 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1044 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1045 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1046 #endif /* sparc_TARGET_ARCH */
1048 #if powerpc_TARGET_ARCH
1050 argRegs 1 = map RealReg [3]
1051 argRegs 2 = map RealReg [3,4]
1052 argRegs 3 = map RealReg [3..5]
1053 argRegs 4 = map RealReg [3..6]
1054 argRegs 5 = map RealReg [3..7]
1055 argRegs 6 = map RealReg [3..8]
1056 argRegs 7 = map RealReg [3..9]
1057 argRegs 8 = map RealReg [3..10]
1058 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1059 #endif /* powerpc_TARGET_ARCH */
1062 -- all of the arg regs ??
1063 #if alpha_TARGET_ARCH
1064 allArgRegs :: [(Reg, Reg)]
1065 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1066 #endif /* alpha_TARGET_ARCH */
1068 #if sparc_TARGET_ARCH
1070 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1071 #endif /* sparc_TARGET_ARCH */
1073 #if i386_TARGET_ARCH
1075 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1078 #if x86_64_TARGET_ARCH
1080 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1081 allFPArgRegs :: [Reg]
1082 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1085 #if powerpc_TARGET_ARCH
1087 allArgRegs = map RealReg [3..10]
1088 allFPArgRegs :: [Reg]
1089 #if darwin_TARGET_OS
1090 allFPArgRegs = map (RealReg . fReg) [1..13]
1091 #elif linux_TARGET_OS
1092 allFPArgRegs = map (RealReg . fReg) [1..8]
1094 #endif /* powerpc_TARGET_ARCH */
1098 freeReg :: RegNo -> FastBool
1100 #if alpha_TARGET_ARCH
1101 freeReg 26 = fastBool False -- return address (ra)
1102 freeReg 28 = fastBool False -- reserved for the assembler (at)
1103 freeReg 29 = fastBool False -- global pointer (gp)
1104 freeReg 30 = fastBool False -- stack pointer (sp)
1105 freeReg 31 = fastBool False -- always zero (zeroh)
1106 freeReg 63 = fastBool False -- always zero (f31)
1109 #if i386_TARGET_ARCH
1110 freeReg esp = fastBool False -- %esp is the C stack pointer
1113 #if x86_64_TARGET_ARCH
1114 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1117 #if sparc_TARGET_ARCH
1118 freeReg g0 = fastBool False -- %g0 is always 0.
1119 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1120 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1121 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1122 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1123 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1124 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1125 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1126 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1127 freeReg f1 = fastBool False
1130 #if powerpc_TARGET_ARCH
1131 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1132 freeReg 1 = fastBool False -- The Stack Pointer
1133 #if !darwin_TARGET_OS
1134 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1135 freeReg 2 = fastBool False
1140 freeReg REG_Base = fastBool False
1143 freeReg REG_R1 = fastBool False
1146 freeReg REG_R2 = fastBool False
1149 freeReg REG_R3 = fastBool False
1152 freeReg REG_R4 = fastBool False
1155 freeReg REG_R5 = fastBool False
1158 freeReg REG_R6 = fastBool False
1161 freeReg REG_R7 = fastBool False
1164 freeReg REG_R8 = fastBool False
1167 freeReg REG_F1 = fastBool False
1170 freeReg REG_F2 = fastBool False
1173 freeReg REG_F3 = fastBool False
1176 freeReg REG_F4 = fastBool False
1179 freeReg REG_D1 = fastBool False
1182 freeReg REG_D2 = fastBool False
1185 freeReg REG_Sp = fastBool False
1188 freeReg REG_Su = fastBool False
1191 freeReg REG_SpLim = fastBool False
1194 freeReg REG_Hp = fastBool False
1197 freeReg REG_HpLim = fastBool False
1199 freeReg n = fastBool True
1202 -- -----------------------------------------------------------------------------
1203 -- Information about global registers
1205 baseRegOffset :: GlobalReg -> Int
1207 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1208 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1209 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1210 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1211 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1212 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1213 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1214 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1215 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1216 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1217 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1218 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1219 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1220 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1221 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1222 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1223 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1224 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1225 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1226 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1227 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1228 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1229 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1230 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1231 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1232 baseRegOffset GCFun = oFFSET_stgGCFun
1234 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1235 baseRegOffset _ = panic "baseRegOffset:other"
1239 -- | Returns 'True' if this global register is stored in a caller-saves
1240 -- machine register.
1242 callerSaves :: GlobalReg -> Bool
1244 #ifdef CALLER_SAVES_Base
1245 callerSaves BaseReg = True
1247 #ifdef CALLER_SAVES_R1
1248 callerSaves (VanillaReg _ ILIT(1)) = True
1250 #ifdef CALLER_SAVES_R2
1251 callerSaves (VanillaReg _ ILIT(2)) = True
1253 #ifdef CALLER_SAVES_R3
1254 callerSaves (VanillaReg _ ILIT(3)) = True
1256 #ifdef CALLER_SAVES_R4
1257 callerSaves (VanillaReg _ ILIT(4)) = True
1259 #ifdef CALLER_SAVES_R5
1260 callerSaves (VanillaReg _ ILIT(5)) = True
1262 #ifdef CALLER_SAVES_R6
1263 callerSaves (VanillaReg _ ILIT(6)) = True
1265 #ifdef CALLER_SAVES_R7
1266 callerSaves (VanillaReg _ ILIT(7)) = True
1268 #ifdef CALLER_SAVES_R8
1269 callerSaves (VanillaReg _ ILIT(8)) = True
1271 #ifdef CALLER_SAVES_F1
1272 callerSaves (FloatReg 1#) = True
1274 #ifdef CALLER_SAVES_F2
1275 callerSaves (FloatReg 2#) = True
1277 #ifdef CALLER_SAVES_F3
1278 callerSaves (FloatReg 3#) = True
1280 #ifdef CALLER_SAVES_F4
1281 callerSaves (FloatReg 4#) = True
1283 #ifdef CALLER_SAVES_D1
1284 callerSaves (DoubleReg 1#) = True
1286 #ifdef CALLER_SAVES_D2
1287 callerSaves (DoubleReg 2#) = True
1289 #ifdef CALLER_SAVES_L1
1290 callerSaves (LongReg _ ILIT(1)) = True
1292 #ifdef CALLER_SAVES_Sp
1293 callerSaves Sp = True
1295 #ifdef CALLER_SAVES_SpLim
1296 callerSaves SpLim = True
1298 #ifdef CALLER_SAVES_Hp
1299 callerSaves Hp = True
1301 #ifdef CALLER_SAVES_HpLim
1302 callerSaves HpLim = True
1304 #ifdef CALLER_SAVES_CurrentTSO
1305 callerSaves CurrentTSO = True
1307 #ifdef CALLER_SAVES_CurrentNursery
1308 callerSaves CurrentNursery = True
1310 callerSaves _ = False
1313 -- | Returns 'Nothing' if this global register is not stored
1314 -- in a real machine register, otherwise returns @'Just' reg@, where
1315 -- reg is the machine register it is stored in.
1317 globalRegMaybe :: GlobalReg -> Maybe Reg
1320 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1323 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1326 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1329 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1332 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1335 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1338 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1341 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1344 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1347 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1350 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1353 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1356 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1359 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1362 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1365 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1368 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1371 globalRegMaybe Sp = Just (RealReg REG_Sp)
1374 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1377 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1380 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1383 globalRegMaybe Hp = Just (RealReg REG_Hp)
1386 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1388 #ifdef REG_CurrentTSO
1389 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1391 #ifdef REG_CurrentNursery
1392 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1394 globalRegMaybe _ = Nothing