2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
17 RegClass(..), regClass,
18 Reg(..), isRealReg, isVirtualReg,
19 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
42 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
45 , eax, ebx, ecx, edx, esi, esp
46 , fake0, fake1, fake2, fake3, fake4, fake5
50 , fpRel, gReg, iReg, lReg, oReg, largeOffsetError
51 , fp, sp, g0, g1, g2, o0, f0, f6, f8, f26, f27
56 #include "HsVersions.h"
58 import AbsCSyn ( MagicId(..) )
59 import AbsCUtils ( magicIdPrimRep )
60 import CLabel ( CLabel, mkMainRegTableLabel )
61 import PrimOp ( PrimOp(..) )
62 import PrimRep ( PrimRep(..), isFloatingRep )
63 import Stix ( StixTree(..), StixReg(..),
64 getUniqueNat, returnNat, thenNat, NatM )
65 import Unique ( mkPseudoUnique2, Uniquable(..), Unique )
67 import Outputable ( Outputable(..), pprPanic, panic )
68 import qualified Outputable
72 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
77 | ImmInteger Integer -- Sigh.
78 | ImmCLbl CLabel -- AbstractC Label (with baggage)
79 | ImmLab Bool Doc -- Simple string label (underscore-able)
80 -- Bool==True ==> in a different DLL
81 | ImmLit Doc -- Simple string
86 | LO Imm -- Possible restrictions...
89 strImmLit s = ImmLit (text s)
92 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
103 = AddrBaseIndex Base Index Displacement
106 type Base = Maybe Reg
107 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
108 type Displacement = Imm
111 #if sparc_TARGET_ARCH
116 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
120 #if alpha_TARGET_ARCH
121 _ -> panic "MachMisc.addrOffset not defined for Alpha"
124 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
125 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
126 AddrBaseIndex r i (ImmInteger n)
127 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
130 #if sparc_TARGET_ARCH
131 AddrRegImm r (ImmInt n)
132 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
133 | otherwise -> Nothing
136 AddrRegImm r (ImmInteger n)
137 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
138 | otherwise -> Nothing
139 where n2 = n + toInteger off
141 AddrRegReg r (RealReg 0)
142 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
143 | otherwise -> Nothing
150 #if alpha_TARGET_ARCH
152 fits8Bits :: Integer -> Bool
153 fits8Bits i = i >= -256 && i < 256
157 #if sparc_TARGET_ARCH
159 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
160 fits13Bits :: Integral a => a -> Bool
161 fits13Bits x = x >= -4096 && x < 4096
165 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
166 ++show i++");\nprobably because of large constant data structures;" ++
167 "\nworkaround: use -fvia-C on this module.\n")
172 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
174 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
175 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
176 The rest are either in real machine registers or stored as offsets
180 data RegLoc = Save StixTree | Always StixTree
183 Trees for register save locations:
185 saveLoc :: MagicId -> StixTree
186 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
190 stgReg :: MagicId -> RegLoc
192 = case magicIdRegMaybe BaseReg of
193 Nothing -> Always (StCLbl mkMainRegTableLabel)
194 Just _ -> Save (StCLbl mkMainRegTableLabel)
196 = case magicIdRegMaybe x of
198 Nothing -> Always stix
200 stix = regTableEntry (magicIdPrimRep x) (baseRegOffset x)
202 regTableEntry :: PrimRep -> Int -> StixTree
203 regTableEntry rep offset
204 = StInd rep (StPrim IntAddOp
205 [baseLoc, StInt (toInteger (offset*BYTES_PER_WORD))])
207 baseLoc = case (magicIdRegMaybe BaseReg) of
208 Just _ -> StReg (StixMagicId BaseReg)
209 Nothing -> StCLbl mkMainRegTableLabel
212 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
214 @spRel@ gives us a stack relative addressing mode for volatile
215 temporaries and for excess call arguments. @fpRel@, where
216 applicable, is the same but for the frame pointer.
219 spRel :: Int -- desired stack offset in words, positive or negative
224 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
226 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
229 #if sparc_TARGET_ARCH
230 fpRel :: Int -> MachRegsAddr
231 -- Duznae work for offsets greater than 13 bits; we just hope for
234 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
238 %************************************************************************
240 \subsection[Reg]{Real registers}
242 %************************************************************************
244 RealRegs are machine regs which are available for allocation, in the
245 usual way. We know what class they are, because that's part of the
246 processor's architecture.
248 VirtualRegs are virtual registers. The register allocator will
249 eventually have to map them into RealRegs, or into spill slots.
250 VirtualRegs are allocated on the fly, usually to represent a single
251 value in the abstract assembly code (i.e. dynamic registers are
252 usually single assignment). With the new register allocator, the
253 single assignment restriction isn't necessary to get correct code,
254 although a better register allocation will result if single assignment
255 is used -- because the allocator maps a VirtualReg into a single
256 RealReg, even if the VirtualReg has multiple live ranges.
258 Virtual regs can be of either class, so that info is attached.
274 unRealReg (RealReg i) = i
275 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
277 mkVReg :: Unique -> PrimRep -> Reg
279 #if sparc_TARGET_ARCH
281 FloatRep -> VirtualRegF u
282 DoubleRep -> VirtualRegD u
283 other -> VirtualRegI u
285 = if isFloatingRep pk then VirtualRegD u else VirtualRegI u
288 isVirtualReg (RealReg _) = False
289 isVirtualReg (VirtualRegI _) = True
290 isVirtualReg (VirtualRegF _) = True
291 isVirtualReg (VirtualRegD _) = True
292 isRealReg = not . isVirtualReg
294 getNewRegNCG :: PrimRep -> NatM Reg
296 = getUniqueNat `thenNat` \ u -> returnNat (mkVReg u pk)
298 instance Eq Reg where
299 (==) (RealReg i1) (RealReg i2) = i1 == i2
300 (==) (VirtualRegI u1) (VirtualRegI u2) = u1 == u2
301 (==) (VirtualRegF u1) (VirtualRegF u2) = u1 == u2
302 (==) (VirtualRegD u1) (VirtualRegD u2) = u1 == u2
303 (==) reg1 reg2 = False
305 instance Ord Reg where
306 compare (RealReg i1) (RealReg i2) = compare i1 i2
307 compare (RealReg _) (VirtualRegI _) = LT
308 compare (RealReg _) (VirtualRegF _) = LT
309 compare (RealReg _) (VirtualRegD _) = LT
311 compare (VirtualRegI _) (RealReg _) = GT
312 compare (VirtualRegI u1) (VirtualRegI u2) = compare u1 u2
313 compare (VirtualRegI _) (VirtualRegF _) = LT
314 compare (VirtualRegI _) (VirtualRegD _) = LT
316 compare (VirtualRegF _) (RealReg _) = GT
317 compare (VirtualRegF _) (VirtualRegI _) = GT
318 compare (VirtualRegF u1) (VirtualRegF u2) = compare u1 u2
319 compare (VirtualRegF _) (VirtualRegD _) = LT
321 compare (VirtualRegD _) (RealReg _) = GT
322 compare (VirtualRegD _) (VirtualRegI _) = GT
323 compare (VirtualRegD _) (VirtualRegF _) = GT
324 compare (VirtualRegD u1) (VirtualRegD u2) = compare u1 u2
327 instance Show Reg where
328 showsPrec _ (RealReg i) = showString (showReg i)
329 showsPrec _ (VirtualRegI u) = showString "%vI_" . shows u
330 showsPrec _ (VirtualRegF u) = showString "%vF_" . shows u
331 showsPrec _ (VirtualRegD u) = showString "%vD_" . shows u
333 instance Outputable Reg where
334 ppr r = Outputable.text (show r)
336 instance Uniquable Reg where
337 getUnique (RealReg i) = mkPseudoUnique2 i
338 getUnique (VirtualRegI u) = u
339 getUnique (VirtualRegF u) = u
340 getUnique (VirtualRegD u) = u
343 ** Machine-specific Reg stuff: **
345 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
346 point registers. The mapping of STG registers to alpha machine registers
347 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
349 #if alpha_TARGET_ARCH
353 v0, f0, ra, pv, gp, sp, zeroh :: Reg
355 f0 = realReg (fReg 0)
356 ra = FixedReg ILIT(26)
358 gp = FixedReg ILIT(29)
359 sp = FixedReg ILIT(30)
360 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
362 t9, t10, t11, t12 :: Reg
370 Intel x86 architecture:
371 - All registers except 7 (esp) are available for use.
372 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
373 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
374 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
375 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
376 fp registers, and 3-operand insns for them, and we translate this into
377 real stack-based x86 fp code after register allocation.
379 The fp registers are all Double registers; we don't have any RcFloat class
380 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
386 fake0, fake1, fake2, fake3, fake4, fake5,
387 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
403 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
404 regClass (VirtualRegI u) = RcInteger
405 regClass (VirtualRegD u) = RcDouble
406 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
407 (ppr (VirtualRegF u))
410 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
411 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
413 showReg :: Int -> String
415 = if n >= 0 && n < 14
417 else "%unknown_x86_real_reg_" ++ show n
422 The SPARC has 64 registers of interest; 32 integer registers and 32
423 floating point registers. The mapping of STG registers to SPARC
424 machine registers is defined in StgRegs.h. We are, of course,
425 prepared for any eventuality.
427 The whole fp-register pairing thing on sparcs is a huge nuisance. See
428 fptools/ghc/includes/MachRegs.h for a description of what's going on
432 #if sparc_TARGET_ARCH
434 gReg,lReg,iReg,oReg,fReg :: Int -> Int
441 nCG_FirstFloatReg :: Int
442 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
444 regClass (VirtualRegI u) = RcInteger
445 regClass (VirtualRegF u) = RcFloat
446 regClass (VirtualRegD u) = RcDouble
447 regClass (RealReg i) | i < 32 = RcInteger
448 | i < nCG_FirstFloatReg = RcDouble
449 | otherwise = RcFloat
451 showReg :: Int -> String
453 | n >= 0 && n < 8 = "%g" ++ show n
454 | n >= 8 && n < 16 = "%o" ++ show (n-8)
455 | n >= 16 && n < 24 = "%l" ++ show (n-16)
456 | n >= 24 && n < 32 = "%i" ++ show (n-24)
457 | n >= 32 && n < 64 = "%f" ++ show (n-32)
458 | otherwise = "%unknown_sparc_real_reg_" ++ show n
460 g0, g1, g2, fp, sp, o0, f0, f1, f6, f8, f22, f26, f27 :: Reg
462 f6 = RealReg (fReg 6)
463 f8 = RealReg (fReg 8)
464 f22 = RealReg (fReg 22)
465 f26 = RealReg (fReg 26)
466 f27 = RealReg (fReg 27)
469 -- g0 is useful for codegen; is always zero, and writes to it vanish.
470 g0 = RealReg (gReg 0)
471 g1 = RealReg (gReg 1)
472 g2 = RealReg (gReg 2)
474 -- FP, SP, int and float return (from C) regs.
475 fp = RealReg (iReg 6)
476 sp = RealReg (oReg 6)
477 o0 = RealReg (oReg 0)
478 f0 = RealReg (fReg 0)
479 f1 = RealReg (fReg 1)
484 Redefine the literals used for machine-registers with non-numeric
485 names in the header files. Gag me with a spoon, eh?
487 #if alpha_TARGET_ARCH
537 #if sparc_TARGET_ARCH
608 baseRegOffset :: MagicId -> Int
610 baseRegOffset (VanillaReg _ 1#) = OFFSET_R1
611 baseRegOffset (VanillaReg _ 2#) = OFFSET_R2
612 baseRegOffset (VanillaReg _ 3#) = OFFSET_R3
613 baseRegOffset (VanillaReg _ 4#) = OFFSET_R4
614 baseRegOffset (VanillaReg _ 5#) = OFFSET_R5
615 baseRegOffset (VanillaReg _ 6#) = OFFSET_R6
616 baseRegOffset (VanillaReg _ 7#) = OFFSET_R7
617 baseRegOffset (VanillaReg _ 8#) = OFFSET_R8
618 baseRegOffset (VanillaReg _ 9#) = OFFSET_R9
619 baseRegOffset (VanillaReg _ 10#) = OFFSET_R10
620 baseRegOffset (FloatReg 1#) = OFFSET_F1
621 baseRegOffset (FloatReg 2#) = OFFSET_F2
622 baseRegOffset (FloatReg 3#) = OFFSET_F3
623 baseRegOffset (FloatReg 4#) = OFFSET_F4
624 baseRegOffset (DoubleReg 1#) = OFFSET_D1
625 baseRegOffset (DoubleReg 2#) = OFFSET_D2
626 baseRegOffset Sp = OFFSET_Sp
627 baseRegOffset Su = OFFSET_Su
628 baseRegOffset SpLim = OFFSET_SpLim
630 baseRegOffset (LongReg _ 1#) = OFFSET_L1
632 baseRegOffset Hp = OFFSET_Hp
633 baseRegOffset HpLim = OFFSET_HpLim
634 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
635 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
636 baseRegOffset HpAlloc = OFFSET_HpAlloc
638 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
639 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
640 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
645 callerSaves :: MagicId -> Bool
647 #ifdef CALLER_SAVES_Base
648 callerSaves BaseReg = True
650 #ifdef CALLER_SAVES_R1
651 callerSaves (VanillaReg _ ILIT(1)) = True
653 #ifdef CALLER_SAVES_R2
654 callerSaves (VanillaReg _ ILIT(2)) = True
656 #ifdef CALLER_SAVES_R3
657 callerSaves (VanillaReg _ ILIT(3)) = True
659 #ifdef CALLER_SAVES_R4
660 callerSaves (VanillaReg _ ILIT(4)) = True
662 #ifdef CALLER_SAVES_R5
663 callerSaves (VanillaReg _ ILIT(5)) = True
665 #ifdef CALLER_SAVES_R6
666 callerSaves (VanillaReg _ ILIT(6)) = True
668 #ifdef CALLER_SAVES_R7
669 callerSaves (VanillaReg _ ILIT(7)) = True
671 #ifdef CALLER_SAVES_R8
672 callerSaves (VanillaReg _ ILIT(8)) = True
674 #ifdef CALLER_SAVES_F1
675 callerSaves (FloatReg 1#) = True
677 #ifdef CALLER_SAVES_F2
678 callerSaves (FloatReg 2#) = True
680 #ifdef CALLER_SAVES_F3
681 callerSaves (FloatReg 3#) = True
683 #ifdef CALLER_SAVES_F4
684 callerSaves (FloatReg 4#) = True
686 #ifdef CALLER_SAVES_D1
687 callerSaves (DoubleReg 1#) = True
689 #ifdef CALLER_SAVES_D2
690 callerSaves (DoubleReg 2#) = True
692 #ifdef CALLER_SAVES_L1
693 callerSaves (LongReg _ ILIT(1)) = True
695 #ifdef CALLER_SAVES_Sp
696 callerSaves Sp = True
698 #ifdef CALLER_SAVES_Su
699 callerSaves Su = True
701 #ifdef CALLER_SAVES_SpLim
702 callerSaves SpLim = True
704 #ifdef CALLER_SAVES_Hp
705 callerSaves Hp = True
707 #ifdef CALLER_SAVES_HpLim
708 callerSaves HpLim = True
710 #ifdef CALLER_SAVES_CurrentTSO
711 callerSaves CurrentTSO = True
713 #ifdef CALLER_SAVES_CurrentNursery
714 callerSaves CurrentNursery = True
716 callerSaves _ = False
720 magicIdRegMaybe :: MagicId -> Maybe Reg
723 magicIdRegMaybe BaseReg = Just (RealReg REG_Base)
726 magicIdRegMaybe (VanillaReg _ 1#) = Just (RealReg REG_R1)
729 magicIdRegMaybe (VanillaReg _ 2#) = Just (RealReg REG_R2)
732 magicIdRegMaybe (VanillaReg _ 3#) = Just (RealReg REG_R3)
735 magicIdRegMaybe (VanillaReg _ 4#) = Just (RealReg REG_R4)
738 magicIdRegMaybe (VanillaReg _ 5#) = Just (RealReg REG_R5)
741 magicIdRegMaybe (VanillaReg _ 6#) = Just (RealReg REG_R6)
744 magicIdRegMaybe (VanillaReg _ 7#) = Just (RealReg REG_R7)
747 magicIdRegMaybe (VanillaReg _ 8#) = Just (RealReg REG_R8)
750 magicIdRegMaybe (VanillaReg _ 9#) = Just (RealReg REG_R9)
753 magicIdRegMaybe (VanillaReg _ 10#) = Just (RealReg REG_R10)
756 magicIdRegMaybe (FloatReg 1#) = Just (RealReg REG_F1)
759 magicIdRegMaybe (FloatReg 2#) = Just (RealReg REG_F2)
762 magicIdRegMaybe (FloatReg 3#) = Just (RealReg REG_F3)
765 magicIdRegMaybe (FloatReg 4#) = Just (RealReg REG_F4)
768 magicIdRegMaybe (DoubleReg 1#) = Just (RealReg REG_D1)
771 magicIdRegMaybe (DoubleReg 2#) = Just (RealReg REG_D2)
774 magicIdRegMaybe Sp = Just (RealReg REG_Sp)
777 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (RealReg REG_Lng1)
780 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (RealReg REG_Lng2)
783 magicIdRegMaybe Su = Just (RealReg REG_Su)
786 magicIdRegMaybe SpLim = Just (RealReg REG_SpLim)
789 magicIdRegMaybe Hp = Just (RealReg REG_Hp)
792 magicIdRegMaybe HpLim = Just (RealReg REG_HpLim)
794 #ifdef REG_CurrentTSO
795 magicIdRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
797 #ifdef REG_CurrentNursery
798 magicIdRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
800 magicIdRegMaybe _ = Nothing
804 -------------------------------
805 -- allMachRegs is the complete set of machine regs.
806 allMachRegNos :: [Int]
808 = IF_ARCH_alpha( [0..63],
809 IF_ARCH_i386( [0..13],
810 IF_ARCH_sparc( ([0..31]
811 ++ [f0,f2 .. nCG_FirstFloatReg-1]
812 ++ [nCG_FirstFloatReg .. f31]),
814 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
815 -- i.e., these are the regs for which we are prepared to allow the
816 -- register allocator to attempt to map VRegs to.
817 allocatableRegs :: [Reg]
819 = let isFree i = isFastTrue (freeReg i)
820 in map RealReg (filter isFree allMachRegNos)
822 -------------------------------
823 -- these are the regs which we cannot assume stay alive over a
825 callClobberedRegs :: [Reg]
828 #if alpha_TARGET_ARCH
829 [0, 1, 2, 3, 4, 5, 6, 7, 8,
830 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
831 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
832 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
833 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
834 #endif {- alpha_TARGET_ARCH -}
836 -- caller-saves registers
837 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
838 #endif {- i386_TARGET_ARCH -}
839 #if sparc_TARGET_ARCH
842 [oReg i | i <- [0..5]] ++
843 [gReg i | i <- [1..7]] ++
844 [fReg i | i <- [0..31]] )
845 #endif {- sparc_TARGET_ARCH -}
847 -------------------------------
848 -- argRegs is the set of regs which are read for an n-argument call to C.
849 -- For archs which pass all args on the stack (x86), is empty.
850 -- Sparc passes up to the first 6 args in regs.
851 -- Dunno about Alpha.
852 argRegs :: Int -> [Reg]
855 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
858 #if alpha_TARGET_ARCH
860 argRegs 1 = freeMappedRegs [16, fReg 16]
861 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
862 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
863 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
864 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
865 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
866 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
867 #endif {- alpha_TARGET_ARCH -}
869 #if sparc_TARGET_ARCH
871 argRegs 1 = map (RealReg . oReg) [0]
872 argRegs 2 = map (RealReg . oReg) [0,1]
873 argRegs 3 = map (RealReg . oReg) [0,1,2]
874 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
875 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
876 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
877 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
878 #endif {- sparc_TARGET_ARCH -}
880 -------------------------------
881 -- all of the arg regs ??
882 #if alpha_TARGET_ARCH
883 allArgRegs :: [(Reg, Reg)]
884 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
885 #endif {- alpha_TARGET_ARCH -}
887 #if sparc_TARGET_ARCH
889 allArgRegs = map RealReg [oReg i | i <- [0..5]]
890 #endif {- sparc_TARGET_ARCH -}
894 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
899 freeReg :: Int -> FastBool
901 #if alpha_TARGET_ARCH
902 freeReg 26 = fastBool False -- return address (ra)
903 freeReg 28 = fastBool False -- reserved for the assembler (at)
904 freeReg 29 = fastBool False -- global pointer (gp)
905 freeReg 30 = fastBool False -- stack pointer (sp)
906 freeReg 31 = fastBool False -- always zero (zeroh)
907 freeReg 63 = fastBool False -- always zero (f31)
911 freeReg esp = fastBool False -- %esp is the C stack pointer
914 #if sparc_TARGET_ARCH
915 freeReg g0 = fastBool False -- %g0 is always 0.
916 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
917 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
918 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
919 freeReg i6 = fastBool False -- %i6 is our frame pointer.
920 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
921 freeReg o6 = fastBool False -- %o6 is our stack pointer.
922 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
923 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
924 freeReg f1 = fastBool False
928 freeReg REG_Base = fastBool False
931 freeReg REG_R1 = fastBool False
934 freeReg REG_R2 = fastBool False
937 freeReg REG_R3 = fastBool False
940 freeReg REG_R4 = fastBool False
943 freeReg REG_R5 = fastBool False
946 freeReg REG_R6 = fastBool False
949 freeReg REG_R7 = fastBool False
952 freeReg REG_R8 = fastBool False
955 freeReg REG_F1 = fastBool False
958 freeReg REG_F2 = fastBool False
961 freeReg REG_F3 = fastBool False
964 freeReg REG_F4 = fastBool False
967 freeReg REG_D1 = fastBool False
970 freeReg REG_D2 = fastBool False
973 freeReg REG_Sp = fastBool False
976 freeReg REG_Su = fastBool False
979 freeReg REG_SpLim = fastBool False
982 freeReg REG_Hp = fastBool False
985 freeReg REG_HpLim = fastBool False
987 freeReg n = fastBool True