2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
17 RegClass(..), regClass,
18 VRegUnique(..), pprVRegUnique, getHiVRegFromLo,
19 Reg(..), isRealReg, isVirtualReg, getVRegUnique,
20 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
31 get_MagicId_reg_or_addr,
33 get_Regtable_addr_from_offset,
41 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
44 , eax, ebx, ecx, edx, esi, esp
45 , fake0, fake1, fake2, fake3, fake4, fake5
49 , fpRel, gReg, iReg, lReg, oReg, largeOffsetError
50 , fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27
53 #if powerpc_TARGET_ARCH
62 #include "HsVersions.h"
64 import AbsCSyn ( MagicId(..) )
65 import CLabel ( CLabel, mkMainCapabilityLabel )
66 import MachOp ( MachOp(..) )
67 import PrimRep ( PrimRep(..), isFloatingRep )
68 import Stix ( StixExpr(..), StixReg(..),
69 getUniqueNat, returnNat, thenNat, NatM )
70 import Unique ( mkPseudoUnique2, Uniquable(..), Unique )
72 import Outputable ( Outputable(..), pprPanic, panic )
73 import qualified Outputable
77 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
82 | ImmInteger Integer -- Sigh.
83 | ImmCLbl CLabel -- AbstractC Label (with baggage)
84 | ImmLab Bool Doc -- Simple string label (underscore-able)
85 -- Bool==True ==> in a different DLL
86 | ImmLit Doc -- Simple string
91 | LO Imm -- Possible restrictions...
96 | HA Imm -- high halfword adjusted
98 strImmLit s = ImmLit (text s)
101 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
105 #if alpha_TARGET_ARCH
112 = AddrBaseIndex Base Index Displacement
115 type Base = Maybe Reg
116 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
117 type Displacement = Imm
120 #if sparc_TARGET_ARCH
125 #if powerpc_TARGET_ARCH
130 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
134 #if alpha_TARGET_ARCH
135 _ -> panic "MachMisc.addrOffset not defined for Alpha"
138 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
139 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
140 AddrBaseIndex r i (ImmInteger n)
141 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
144 #if sparc_TARGET_ARCH
145 AddrRegImm r (ImmInt n)
146 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
147 | otherwise -> Nothing
150 AddrRegImm r (ImmInteger n)
151 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
152 | otherwise -> Nothing
153 where n2 = n + toInteger off
155 AddrRegReg r (RealReg 0)
156 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
157 | otherwise -> Nothing
162 #if powerpc_TARGET_ARCH
163 AddrRegImm r (ImmInt n)
164 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
165 | otherwise -> Nothing
168 AddrRegImm r (ImmInteger n)
169 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
170 | otherwise -> Nothing
171 where n2 = n + toInteger off
173 AddrRegReg r (RealReg 0)
174 | fits16Bits off -> Just (AddrRegImm r (ImmInt off))
175 | otherwise -> Nothing
181 #if alpha_TARGET_ARCH
183 fits8Bits :: Integer -> Bool
184 fits8Bits i = i >= -256 && i < 256
188 #if sparc_TARGET_ARCH
190 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
191 fits13Bits :: Integral a => a -> Bool
192 fits13Bits x = x >= -4096 && x < 4096
196 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
197 ++show i++");\nprobably because of large constant data structures;" ++
198 "\nworkaround: use -fvia-C on this module.\n")
202 #if powerpc_TARGET_ARCH
203 fits16Bits :: Integral a => a -> Bool
204 fits16Bits x = x >= -32768 && x < 32768
208 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
210 @stgReg@: we map STG registers onto appropriate Stix Trees. Either
211 they map to real machine registers or stored as offsets from BaseReg.
212 Given a MagicId, get_MagicId_reg_or_addr produces either the real
213 register it is in, on this platform, or a StixExpr denoting the
214 address in the register table holding it. get_MagicId_addr always
215 produces the register table address for it.
218 get_MagicId_reg_or_addr :: MagicId -> Either Reg StixExpr
219 get_MagicId_addr :: MagicId -> StixExpr
220 get_Regtable_addr_from_offset :: Int -> StixExpr
222 get_MagicId_reg_or_addr mid
223 = case magicIdRegMaybe mid of
225 Nothing -> Right (get_MagicId_addr mid)
227 get_MagicId_addr BaseReg
228 = -- This arch doesn't have BaseReg in a register, so we have to
229 -- use &MainRegTable.r instead.
230 StIndex PtrRep (StCLbl mkMainCapabilityLabel)
231 (StInt (toInteger OFFW_Capability_r))
233 = get_Regtable_addr_from_offset (baseRegOffset mid)
235 get_Regtable_addr_from_offset offset_in_words
236 = let ptr_to_RegTable
237 = case magicIdRegMaybe BaseReg of
239 -> -- This arch doesn't have BaseReg in a register, so we have to
240 -- use &MainRegTable.r instead.
241 StIndex PtrRep (StCLbl mkMainCapabilityLabel)
242 (StInt (toInteger OFFW_Capability_r))
244 -> -- It's in a reg, so leave it as it is
245 StReg (StixMagicId BaseReg)
247 StIndex PtrRep ptr_to_RegTable (StInt (toInteger offset_in_words))
250 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
252 @spRel@ gives us a stack relative addressing mode for volatile
253 temporaries and for excess call arguments. @fpRel@, where
254 applicable, is the same but for the frame pointer.
257 spRel :: Int -- desired stack offset in words, positive or negative
262 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
264 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
267 #if sparc_TARGET_ARCH
268 fpRel :: Int -> MachRegsAddr
269 -- Duznae work for offsets greater than 13 bits; we just hope for
272 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
276 %************************************************************************
278 \subsection[Reg]{Real registers}
280 %************************************************************************
282 RealRegs are machine regs which are available for allocation, in the
283 usual way. We know what class they are, because that's part of the
284 processor's architecture.
286 VirtualRegs are virtual registers. The register allocator will
287 eventually have to map them into RealRegs, or into spill slots.
288 VirtualRegs are allocated on the fly, usually to represent a single
289 value in the abstract assembly code (i.e. dynamic registers are
290 usually single assignment). With the new register allocator, the
291 single assignment restriction isn't necessary to get correct code,
292 although a better register allocation will result if single assignment
293 is used -- because the allocator maps a VirtualReg into a single
294 RealReg, even if the VirtualReg has multiple live ranges.
296 Virtual regs can be of either class, so that info is attached.
301 = VRegUniqueLo Unique -- lower part of a split quantity
302 | VRegUniqueHi Unique -- upper part thereof
305 instance Show VRegUnique where
306 show (VRegUniqueLo u) = show u
307 show (VRegUniqueHi u) = "_hi_" ++ show u
309 pprVRegUnique :: VRegUnique -> Outputable.SDoc
311 = Outputable.text . show
313 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
314 -- when supplied with the vreg for the lower-half of the quantity.
315 getHiVRegFromLo (VirtualRegI (VRegUniqueLo u))
316 = VirtualRegI (VRegUniqueHi u)
317 getHiVRegFromLo other
318 = pprPanic "getHiVRegFromLo" (ppr other)
328 | VirtualRegI VRegUnique
329 | VirtualRegF VRegUnique
330 | VirtualRegD VRegUnique
332 unRealReg (RealReg i) = i
333 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
335 getVRegUnique :: Reg -> VRegUnique
336 getVRegUnique (VirtualRegI vu) = vu
337 getVRegUnique (VirtualRegF vu) = vu
338 getVRegUnique (VirtualRegD vu) = vu
339 getVRegUnique rreg = pprPanic "getVRegUnique on RealReg" (ppr rreg)
341 mkVReg :: Unique -> PrimRep -> Reg
343 #if sparc_TARGET_ARCH
345 FloatRep -> VirtualRegF (VRegUniqueLo u)
346 DoubleRep -> VirtualRegD (VRegUniqueLo u)
347 other -> VirtualRegI (VRegUniqueLo u)
349 = if isFloatingRep pk then VirtualRegD (VRegUniqueLo u)
350 else VirtualRegI (VRegUniqueLo u)
353 isVirtualReg (RealReg _) = False
354 isVirtualReg (VirtualRegI _) = True
355 isVirtualReg (VirtualRegF _) = True
356 isVirtualReg (VirtualRegD _) = True
357 isRealReg = not . isVirtualReg
359 getNewRegNCG :: PrimRep -> NatM Reg
361 = getUniqueNat `thenNat` \ u -> returnNat (mkVReg u pk)
363 instance Eq Reg where
364 (==) (RealReg i1) (RealReg i2) = i1 == i2
365 (==) (VirtualRegI u1) (VirtualRegI u2) = u1 == u2
366 (==) (VirtualRegF u1) (VirtualRegF u2) = u1 == u2
367 (==) (VirtualRegD u1) (VirtualRegD u2) = u1 == u2
368 (==) reg1 reg2 = False
370 instance Ord Reg where
371 compare (RealReg i1) (RealReg i2) = compare i1 i2
372 compare (RealReg _) (VirtualRegI _) = LT
373 compare (RealReg _) (VirtualRegF _) = LT
374 compare (RealReg _) (VirtualRegD _) = LT
376 compare (VirtualRegI _) (RealReg _) = GT
377 compare (VirtualRegI u1) (VirtualRegI u2) = compare u1 u2
378 compare (VirtualRegI _) (VirtualRegF _) = LT
379 compare (VirtualRegI _) (VirtualRegD _) = LT
381 compare (VirtualRegF _) (RealReg _) = GT
382 compare (VirtualRegF _) (VirtualRegI _) = GT
383 compare (VirtualRegF u1) (VirtualRegF u2) = compare u1 u2
384 compare (VirtualRegF _) (VirtualRegD _) = LT
386 compare (VirtualRegD _) (RealReg _) = GT
387 compare (VirtualRegD _) (VirtualRegI _) = GT
388 compare (VirtualRegD _) (VirtualRegF _) = GT
389 compare (VirtualRegD u1) (VirtualRegD u2) = compare u1 u2
392 instance Show Reg where
393 show (RealReg i) = showReg i
394 show (VirtualRegI u) = "%vI_" ++ show u
395 show (VirtualRegF u) = "%vF_" ++ show u
396 show (VirtualRegD u) = "%vD_" ++ show u
398 instance Outputable Reg where
399 ppr r = Outputable.text (show r)
402 ** Machine-specific Reg stuff: **
404 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
405 point registers. The mapping of STG registers to alpha machine registers
406 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
408 #if alpha_TARGET_ARCH
412 v0, f0, ra, pv, gp, sp, zeroh :: Reg
414 f0 = realReg (fReg 0)
415 ra = FixedReg ILIT(26)
417 gp = FixedReg ILIT(29)
418 sp = FixedReg ILIT(30)
419 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
421 t9, t10, t11, t12 :: Reg
429 Intel x86 architecture:
430 - All registers except 7 (esp) are available for use.
431 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
432 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
433 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
434 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
435 fp registers, and 3-operand insns for them, and we translate this into
436 real stack-based x86 fp code after register allocation.
438 The fp registers are all Double registers; we don't have any RcFloat class
439 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
445 fake0, fake1, fake2, fake3, fake4, fake5,
446 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
462 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
463 regClass (VirtualRegI u) = RcInteger
464 regClass (VirtualRegD u) = RcDouble
465 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
466 (ppr (VirtualRegF u))
469 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
470 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
472 showReg :: Int -> String
474 = if n >= 0 && n < 14
476 else "%unknown_x86_real_reg_" ++ show n
481 The SPARC has 64 registers of interest; 32 integer registers and 32
482 floating point registers. The mapping of STG registers to SPARC
483 machine registers is defined in StgRegs.h. We are, of course,
484 prepared for any eventuality.
486 The whole fp-register pairing thing on sparcs is a huge nuisance. See
487 fptools/ghc/includes/MachRegs.h for a description of what's going on
491 #if sparc_TARGET_ARCH
493 gReg,lReg,iReg,oReg,fReg :: Int -> Int
500 nCG_FirstFloatReg :: Int
501 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
503 regClass (VirtualRegI u) = RcInteger
504 regClass (VirtualRegF u) = RcFloat
505 regClass (VirtualRegD u) = RcDouble
506 regClass (RealReg i) | i < 32 = RcInteger
507 | i < nCG_FirstFloatReg = RcDouble
508 | otherwise = RcFloat
510 showReg :: Int -> String
512 | n >= 0 && n < 8 = "%g" ++ show n
513 | n >= 8 && n < 16 = "%o" ++ show (n-8)
514 | n >= 16 && n < 24 = "%l" ++ show (n-16)
515 | n >= 24 && n < 32 = "%i" ++ show (n-24)
516 | n >= 32 && n < 64 = "%f" ++ show (n-32)
517 | otherwise = "%unknown_sparc_real_reg_" ++ show n
519 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
521 f6 = RealReg (fReg 6)
522 f8 = RealReg (fReg 8)
523 f22 = RealReg (fReg 22)
524 f26 = RealReg (fReg 26)
525 f27 = RealReg (fReg 27)
528 -- g0 is useful for codegen; is always zero, and writes to it vanish.
529 g0 = RealReg (gReg 0)
530 g1 = RealReg (gReg 1)
531 g2 = RealReg (gReg 2)
533 -- FP, SP, int and float return (from C) regs.
534 fp = RealReg (iReg 6)
535 sp = RealReg (oReg 6)
536 o0 = RealReg (oReg 0)
537 o1 = RealReg (oReg 1)
538 f0 = RealReg (fReg 0)
539 f1 = RealReg (fReg 1)
544 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
547 #if powerpc_TARGET_ARCH
551 regClass (VirtualRegI u) = RcInteger
552 regClass (VirtualRegF u) = RcFloat
553 regClass (VirtualRegD u) = RcDouble
554 regClass (RealReg i) | i < 32 = RcInteger
555 | otherwise = RcDouble
556 -- | i < nCG_FirstFloatReg = RcDouble
557 -- | otherwise = RcFloat
559 showReg :: Int -> String
561 | n >= 0 && n <= 31 = "%r" ++ show n
562 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
563 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
570 f1 = RealReg $ fReg 1
571 f20 = RealReg $ fReg 20
572 f21 = RealReg $ fReg 21
576 Redefine the literals used for machine-registers with non-numeric
577 names in the header files. Gag me with a spoon, eh?
579 #if alpha_TARGET_ARCH
629 #if sparc_TARGET_ARCH
697 #if powerpc_TARGET_ARCH
766 baseRegOffset :: MagicId -> Int
768 baseRegOffset (VanillaReg _ 1#) = OFFSET_R1
769 baseRegOffset (VanillaReg _ 2#) = OFFSET_R2
770 baseRegOffset (VanillaReg _ 3#) = OFFSET_R3
771 baseRegOffset (VanillaReg _ 4#) = OFFSET_R4
772 baseRegOffset (VanillaReg _ 5#) = OFFSET_R5
773 baseRegOffset (VanillaReg _ 6#) = OFFSET_R6
774 baseRegOffset (VanillaReg _ 7#) = OFFSET_R7
775 baseRegOffset (VanillaReg _ 8#) = OFFSET_R8
776 baseRegOffset (VanillaReg _ 9#) = OFFSET_R9
777 baseRegOffset (VanillaReg _ 10#) = OFFSET_R10
778 baseRegOffset (FloatReg 1#) = OFFSET_F1
779 baseRegOffset (FloatReg 2#) = OFFSET_F2
780 baseRegOffset (FloatReg 3#) = OFFSET_F3
781 baseRegOffset (FloatReg 4#) = OFFSET_F4
782 baseRegOffset (DoubleReg 1#) = OFFSET_D1
783 baseRegOffset (DoubleReg 2#) = OFFSET_D2
784 baseRegOffset Sp = OFFSET_Sp
785 baseRegOffset SpLim = OFFSET_SpLim
787 baseRegOffset (LongReg _ 1#) = OFFSET_L1
789 baseRegOffset Hp = OFFSET_Hp
790 baseRegOffset HpLim = OFFSET_HpLim
791 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
792 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
793 baseRegOffset HpAlloc = OFFSET_HpAlloc
795 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
796 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
797 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
802 callerSaves :: MagicId -> Bool
804 #ifdef CALLER_SAVES_Base
805 callerSaves BaseReg = True
807 #ifdef CALLER_SAVES_R1
808 callerSaves (VanillaReg _ ILIT(1)) = True
810 #ifdef CALLER_SAVES_R2
811 callerSaves (VanillaReg _ ILIT(2)) = True
813 #ifdef CALLER_SAVES_R3
814 callerSaves (VanillaReg _ ILIT(3)) = True
816 #ifdef CALLER_SAVES_R4
817 callerSaves (VanillaReg _ ILIT(4)) = True
819 #ifdef CALLER_SAVES_R5
820 callerSaves (VanillaReg _ ILIT(5)) = True
822 #ifdef CALLER_SAVES_R6
823 callerSaves (VanillaReg _ ILIT(6)) = True
825 #ifdef CALLER_SAVES_R7
826 callerSaves (VanillaReg _ ILIT(7)) = True
828 #ifdef CALLER_SAVES_R8
829 callerSaves (VanillaReg _ ILIT(8)) = True
831 #ifdef CALLER_SAVES_F1
832 callerSaves (FloatReg 1#) = True
834 #ifdef CALLER_SAVES_F2
835 callerSaves (FloatReg 2#) = True
837 #ifdef CALLER_SAVES_F3
838 callerSaves (FloatReg 3#) = True
840 #ifdef CALLER_SAVES_F4
841 callerSaves (FloatReg 4#) = True
843 #ifdef CALLER_SAVES_D1
844 callerSaves (DoubleReg 1#) = True
846 #ifdef CALLER_SAVES_D2
847 callerSaves (DoubleReg 2#) = True
849 #ifdef CALLER_SAVES_L1
850 callerSaves (LongReg _ ILIT(1)) = True
852 #ifdef CALLER_SAVES_Sp
853 callerSaves Sp = True
855 #ifdef CALLER_SAVES_SpLim
856 callerSaves SpLim = True
858 #ifdef CALLER_SAVES_Hp
859 callerSaves Hp = True
861 #ifdef CALLER_SAVES_HpLim
862 callerSaves HpLim = True
864 #ifdef CALLER_SAVES_CurrentTSO
865 callerSaves CurrentTSO = True
867 #ifdef CALLER_SAVES_CurrentNursery
868 callerSaves CurrentNursery = True
870 callerSaves _ = False
874 magicIdRegMaybe :: MagicId -> Maybe Reg
877 magicIdRegMaybe BaseReg = Just (RealReg REG_Base)
880 magicIdRegMaybe (VanillaReg _ 1#) = Just (RealReg REG_R1)
883 magicIdRegMaybe (VanillaReg _ 2#) = Just (RealReg REG_R2)
886 magicIdRegMaybe (VanillaReg _ 3#) = Just (RealReg REG_R3)
889 magicIdRegMaybe (VanillaReg _ 4#) = Just (RealReg REG_R4)
892 magicIdRegMaybe (VanillaReg _ 5#) = Just (RealReg REG_R5)
895 magicIdRegMaybe (VanillaReg _ 6#) = Just (RealReg REG_R6)
898 magicIdRegMaybe (VanillaReg _ 7#) = Just (RealReg REG_R7)
901 magicIdRegMaybe (VanillaReg _ 8#) = Just (RealReg REG_R8)
904 magicIdRegMaybe (VanillaReg _ 9#) = Just (RealReg REG_R9)
907 magicIdRegMaybe (VanillaReg _ 10#) = Just (RealReg REG_R10)
910 magicIdRegMaybe (FloatReg 1#) = Just (RealReg REG_F1)
913 magicIdRegMaybe (FloatReg 2#) = Just (RealReg REG_F2)
916 magicIdRegMaybe (FloatReg 3#) = Just (RealReg REG_F3)
919 magicIdRegMaybe (FloatReg 4#) = Just (RealReg REG_F4)
922 magicIdRegMaybe (DoubleReg 1#) = Just (RealReg REG_D1)
925 magicIdRegMaybe (DoubleReg 2#) = Just (RealReg REG_D2)
928 magicIdRegMaybe Sp = Just (RealReg REG_Sp)
931 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (RealReg REG_Lng1)
934 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (RealReg REG_Lng2)
937 magicIdRegMaybe SpLim = Just (RealReg REG_SpLim)
940 magicIdRegMaybe Hp = Just (RealReg REG_Hp)
943 magicIdRegMaybe HpLim = Just (RealReg REG_HpLim)
945 #ifdef REG_CurrentTSO
946 magicIdRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
948 #ifdef REG_CurrentNursery
949 magicIdRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
951 magicIdRegMaybe _ = Nothing
955 -------------------------------
956 -- allMachRegs is the complete set of machine regs.
957 allMachRegNos :: [Int]
959 = IF_ARCH_alpha( [0..63],
960 IF_ARCH_i386( [0..13],
961 IF_ARCH_sparc( ([0..31]
962 ++ [f0,f2 .. nCG_FirstFloatReg-1]
963 ++ [nCG_FirstFloatReg .. f31]),
964 IF_ARCH_powerpc([0..63],
966 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
967 -- i.e., these are the regs for which we are prepared to allow the
968 -- register allocator to attempt to map VRegs to.
969 allocatableRegs :: [Reg]
971 = let isFree i = isFastTrue (freeReg i)
972 in map RealReg (filter isFree allMachRegNos)
974 -------------------------------
975 -- these are the regs which we cannot assume stay alive over a
977 callClobberedRegs :: [Reg]
980 #if alpha_TARGET_ARCH
981 [0, 1, 2, 3, 4, 5, 6, 7, 8,
982 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
983 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
984 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
985 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
986 #endif {- alpha_TARGET_ARCH -}
988 -- caller-saves registers
989 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
990 #endif {- i386_TARGET_ARCH -}
991 #if sparc_TARGET_ARCH
994 [oReg i | i <- [0..5]] ++
995 [gReg i | i <- [1..7]] ++
996 [fReg i | i <- [0..31]] )
997 #endif {- sparc_TARGET_ARCH -}
998 #if powerpc_TARGET_ARCH
999 map RealReg ([0..12] ++ map fReg [0..13])
1000 #endif {- powerpc_TARGET_ARCH -}
1002 -------------------------------
1003 -- argRegs is the set of regs which are read for an n-argument call to C.
1004 -- For archs which pass all args on the stack (x86), is empty.
1005 -- Sparc passes up to the first 6 args in regs.
1006 -- Dunno about Alpha.
1007 argRegs :: Int -> [Reg]
1009 #if i386_TARGET_ARCH
1010 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1013 #if alpha_TARGET_ARCH
1015 argRegs 1 = freeMappedRegs [16, fReg 16]
1016 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1017 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1018 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1019 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1020 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1021 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1022 #endif {- alpha_TARGET_ARCH -}
1024 #if sparc_TARGET_ARCH
1026 argRegs 1 = map (RealReg . oReg) [0]
1027 argRegs 2 = map (RealReg . oReg) [0,1]
1028 argRegs 3 = map (RealReg . oReg) [0,1,2]
1029 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1030 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1031 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1032 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1033 #endif {- sparc_TARGET_ARCH -}
1035 #if powerpc_TARGET_ARCH
1037 argRegs 1 = map RealReg [3]
1038 argRegs 2 = map RealReg [3,4]
1039 argRegs 3 = map RealReg [3..5]
1040 argRegs 4 = map RealReg [3..6]
1041 argRegs 5 = map RealReg [3..7]
1042 argRegs 6 = map RealReg [3..8]
1043 argRegs 7 = map RealReg [3..9]
1044 argRegs 8 = map RealReg [3..10]
1045 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1046 #endif {- powerpc_TARGET_ARCH -}
1048 -------------------------------
1049 -- all of the arg regs ??
1050 #if alpha_TARGET_ARCH
1051 allArgRegs :: [(Reg, Reg)]
1052 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1053 #endif {- alpha_TARGET_ARCH -}
1055 #if sparc_TARGET_ARCH
1057 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1058 #endif {- sparc_TARGET_ARCH -}
1060 #if i386_TARGET_ARCH
1062 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1065 #if powerpc_TARGET_ARCH
1067 allArgRegs = map RealReg [3..10]
1068 allFPArgRegs :: [Reg]
1069 allFPArgRegs = map (RealReg . fReg) [1..13]
1070 #endif {- powerpc_TARGET_ARCH -}
1074 freeReg :: Int -> FastBool
1076 #if alpha_TARGET_ARCH
1077 freeReg 26 = fastBool False -- return address (ra)
1078 freeReg 28 = fastBool False -- reserved for the assembler (at)
1079 freeReg 29 = fastBool False -- global pointer (gp)
1080 freeReg 30 = fastBool False -- stack pointer (sp)
1081 freeReg 31 = fastBool False -- always zero (zeroh)
1082 freeReg 63 = fastBool False -- always zero (f31)
1085 #if i386_TARGET_ARCH
1086 freeReg esp = fastBool False -- %esp is the C stack pointer
1089 #if sparc_TARGET_ARCH
1090 freeReg g0 = fastBool False -- %g0 is always 0.
1091 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1092 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1093 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1094 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1095 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1096 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1097 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1098 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1099 freeReg f1 = fastBool False
1102 #if powerpc_TARGET_ARCH
1103 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1104 freeReg 1 = fastBool False -- The Stack Pointer
1105 #if !darwin_TARGET_OS
1106 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1107 freeReg 2 = fastBool False
1112 freeReg REG_Base = fastBool False
1115 freeReg REG_R1 = fastBool False
1118 freeReg REG_R2 = fastBool False
1121 freeReg REG_R3 = fastBool False
1124 freeReg REG_R4 = fastBool False
1127 freeReg REG_R5 = fastBool False
1130 freeReg REG_R6 = fastBool False
1133 freeReg REG_R7 = fastBool False
1136 freeReg REG_R8 = fastBool False
1139 freeReg REG_F1 = fastBool False
1142 freeReg REG_F2 = fastBool False
1145 freeReg REG_F3 = fastBool False
1148 freeReg REG_F4 = fastBool False
1151 freeReg REG_D1 = fastBool False
1154 freeReg REG_D2 = fastBool False
1157 freeReg REG_Sp = fastBool False
1160 freeReg REG_Su = fastBool False
1163 freeReg REG_SpLim = fastBool False
1166 freeReg REG_Hp = fastBool False
1169 freeReg REG_HpLim = fastBool False
1171 freeReg n = fastBool True