2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "HsVersions.h"
14 #include "nativeGen/NCG.h"
47 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
50 , eax, ebx, ecx, edx, esi, esp
51 , st0, st1, st2, st3, st4, st5, st6, st7
56 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
62 #if __GLASGOW_HASKELL__ >= 202
63 import GlaExts hiding (Addr)
70 import AbsCSyn ( MagicId(..) )
71 import AbsCUtils ( magicIdPrimRep )
72 import CLabel ( CLabel )
73 import Outputable ( Outputable(..) )
74 import Pretty ( Doc, text, rational )
75 import PrimOp ( PrimOp(..) )
76 import PrimRep ( PrimRep(..) )
77 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
80 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
81 Unique{-instance Ord3-}
83 import UniqSupply ( getUnique, returnUs, thenUs, SYN_IE(UniqSM) )
84 import Util ( panic, Ord3(..) )
87 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
92 | ImmInteger Integer -- Sigh.
93 | ImmCLbl CLabel -- AbstractC Label (with baggage)
94 | ImmLab Doc -- Simple string label (underscore-able)
95 | ImmLit Doc -- Simple string
97 | LO Imm -- Possible restrictions...
101 strImmLit s = ImmLit (text s)
104 IF_ARCH_alpha({-prepend nothing-}
105 ,IF_ARCH_i386( '0' : 'd' :
106 ,IF_ARCH_sparc('0' : 'r' :,)))
110 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
114 #if alpha_TARGET_ARCH
121 = Addr Base Index Displacement
124 type Base = Maybe Reg
125 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
126 type Displacement = Imm
129 #if sparc_TARGET_ARCH
134 addrOffset :: Addr -> Int -> Maybe Addr
138 #if alpha_TARGET_ARCH
139 _ -> panic "MachMisc.addrOffset not defined for Alpha"
142 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
143 Addr r i (ImmInt n) -> Just (Addr r i (ImmInt (n + off)))
144 Addr r i (ImmInteger n)
145 -> Just (Addr r i (ImmInt (fromInteger (n + toInteger off))))
148 #if sparc_TARGET_ARCH
149 AddrRegImm r (ImmInt n)
150 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
151 | otherwise -> Nothing
154 AddrRegImm r (ImmInteger n)
155 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
156 | otherwise -> Nothing
157 where n2 = n + toInteger off
159 AddrRegReg r (FixedReg ILIT(0))
160 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
161 | otherwise -> Nothing
168 #if alpha_TARGET_ARCH
170 fits8Bits :: Integer -> Bool
171 fits8Bits i = i >= -256 && i < 256
175 #if sparc_TARGET_ARCH
177 fits13Bits :: Int -> Bool
180 fits13Bits :: Integer -> Bool
183 fits13Bits :: Integral a => a -> Bool
184 fits13Bits x = x >= -4096 && x < 4096
188 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
193 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
195 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
196 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
197 The rest are either in real machine registers or stored as offsets
201 data RegLoc = Save StixTree | Always StixTree
204 Trees for register save locations:
206 saveLoc :: MagicId -> StixTree
208 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
212 stgReg :: MagicId -> RegLoc
215 = case (magicIdRegMaybe x) of
216 Just _ -> Save nonReg
217 Nothing -> Always nonReg
219 offset = baseRegOffset x
221 baseLoc = case (magicIdRegMaybe BaseReg) of
222 Just _ -> StReg (StixMagicId BaseReg)
223 Nothing -> sStLitLbl SLIT("MainRegTable")
226 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
227 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
228 BaseReg -> sStLitLbl SLIT("MainRegTable")
229 -- these Hp&HpLim cases perhaps should
230 -- not be here for i386 (???) WDP 96/03
231 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
232 HpLim -> StInd PtrRep (sStLitLbl
233 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
234 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
235 StInt (1*BYTES_PER_WORD)])
237 r2 = VanillaReg PtrRep ILIT(2)
238 infoptr = case (stgReg r2) of
240 Save _ -> StReg (StixMagicId r2)
241 _ -> StInd (magicIdPrimRep x)
242 (StPrim IntAddOp [baseLoc,
243 StInt (toInteger (offset*BYTES_PER_WORD))])
246 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
248 @spRel@ gives us a stack relative addressing mode for volatile
249 temporaries and for excess call arguments. @fpRel@, where
250 applicable, is the same but for the frame pointer.
253 spRel :: Int -- desired stack offset in words, positive or negative
258 = Addr (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
260 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
263 #if sparc_TARGET_ARCH
265 -- Duznae work for offsets greater than 13 bits; we just hope for
268 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
272 %************************************************************************
274 \subsection[Reg]{Real registers}
276 %************************************************************************
278 Static Registers correspond to actual machine registers. These should
279 be avoided until the last possible moment.
281 Dynamic registers are allocated on the fly, usually to represent a single
282 value in the abstract assembly code (i.e. dynamic registers are usually
283 single assignment). Ultimately, they are mapped to available machine
284 registers before spitting out the code.
288 = FixedReg FAST_INT -- A pre-allocated machine register
290 | MappedReg FAST_INT -- A dynamically allocated machine register
292 | MemoryReg Int PrimRep -- A machine "register" actually held in
293 -- a memory allocated table of
294 -- registers which didn't fit in real
297 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
298 -- always mapped to one of the earlier
299 -- two (?) before we're done.
301 mkReg :: Unique -> PrimRep -> Reg
304 getNewRegNCG :: PrimRep -> UniqSM Reg
306 = getUnique `thenUs` \ u ->
307 returnUs (UnmappedReg u pk)
309 instance Text Reg where
310 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
311 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
312 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
313 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
316 instance Outputable Reg where
317 ppr sty r = text (show r)
320 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
321 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
322 cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i'
323 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u'
325 = let tag1 = tagReg r1
328 if tag1 _LT_ tag2 then LT_ else GT_
330 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
331 tagReg (MappedReg _) = ILIT(2)
332 tagReg (MemoryReg _ _) = ILIT(3)
333 tagReg (UnmappedReg _ _) = ILIT(4)
335 cmp_i :: Int -> Int -> TAG_
336 cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_
338 cmp_ihash :: FAST_INT -> FAST_INT -> TAG_
339 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_
341 instance Ord3 Reg where
344 instance Eq Reg where
345 a == b = case (a `cmp` b) of { EQ_ -> True; _ -> False }
346 a /= b = case (a `cmp` b) of { EQ_ -> False; _ -> True }
348 instance Ord Reg where
349 a <= b = case (a `cmp` b) of { LT_ -> True; EQ_ -> True; GT__ -> False }
350 a < b = case (a `cmp` b) of { LT_ -> True; EQ_ -> False; GT__ -> False }
351 a >= b = case (a `cmp` b) of { LT_ -> False; EQ_ -> True; GT__ -> True }
352 a > b = case (a `cmp` b) of { LT_ -> False; EQ_ -> False; GT__ -> True }
353 _tagCmp a b = case (a `cmp` b) of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT }
355 instance Uniquable Reg where
356 uniqueOf (UnmappedReg u _) = u
357 uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i)
358 uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i)
359 uniqueOf (MemoryReg i _) = mkPseudoUnique3 i
365 realReg :: RegNo -> Reg
367 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
369 extractMappedRegNos :: [Reg] -> [RegNo]
371 extractMappedRegNos regs
374 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
375 ex _ acc = acc -- leave it out
378 ** Machine-specific Reg stuff: **
380 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
381 point registers. The mapping of STG registers to alpha machine registers
382 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
384 #if alpha_TARGET_ARCH
388 v0, f0, ra, pv, gp, sp, zeroh :: Reg
390 f0 = realReg (fReg 0)
391 ra = FixedReg ILIT(26)
393 gp = FixedReg ILIT(29)
394 sp = FixedReg ILIT(30)
395 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
397 t9, t10, t11, t12 :: Reg
405 Intel x86 architecture:
406 - All registers except 7 (esp) are available for use.
407 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
408 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
409 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
410 - Registers 8-15 hold extended floating point values.
414 gReg,fReg :: Int -> Int
418 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
419 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
420 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
421 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
422 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
423 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
424 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
425 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
426 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
427 st0 = realReg (fReg 0)
428 st1 = realReg (fReg 1)
429 st2 = realReg (fReg 2)
430 st3 = realReg (fReg 3)
431 st4 = realReg (fReg 4)
432 st5 = realReg (fReg 5)
433 st6 = realReg (fReg 6)
434 st7 = realReg (fReg 7)
439 The SPARC has 64 registers of interest; 32 integer registers and 32
440 floating point registers. The mapping of STG registers to SPARC
441 machine registers is defined in StgRegs.h. We are, of course,
442 prepared for any eventuality.
445 #if sparc_TARGET_ARCH
447 gReg,lReg,iReg,oReg,fReg :: Int -> Int
455 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
456 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
458 g0, fp, sp, o0, f0 :: Reg
459 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
460 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
461 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
462 o0 = realReg (oReg 0)
463 f0 = realReg (fReg 0)
468 Redefine the literals used for machine-registers with non-numeric
469 names in the header files. Gag me with a spoon, eh?
471 #if alpha_TARGET_ARCH
523 #if sparc_TARGET_ARCH
592 baseRegOffset :: MagicId -> Int
594 baseRegOffset StkOReg = OFFSET_StkO
595 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
596 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
597 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
598 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
599 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
600 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
601 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
602 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
603 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
604 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
605 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
606 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
607 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
608 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
609 baseRegOffset TagReg = OFFSET_Tag
610 baseRegOffset RetReg = OFFSET_Ret
611 baseRegOffset SpA = OFFSET_SpA
612 baseRegOffset SuA = OFFSET_SuA
613 baseRegOffset SpB = OFFSET_SpB
614 baseRegOffset SuB = OFFSET_SuB
615 baseRegOffset Hp = OFFSET_Hp
616 baseRegOffset HpLim = OFFSET_HpLim
617 baseRegOffset LivenessReg = OFFSET_Liveness
619 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
620 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
621 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
622 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
623 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
628 callerSaves :: MagicId -> Bool
630 #ifdef CALLER_SAVES_Base
631 callerSaves BaseReg = True
633 #ifdef CALLER_SAVES_StkO
634 callerSaves StkOReg = True
636 #ifdef CALLER_SAVES_R1
637 callerSaves (VanillaReg _ ILIT(1)) = True
639 #ifdef CALLER_SAVES_R2
640 callerSaves (VanillaReg _ ILIT(2)) = True
642 #ifdef CALLER_SAVES_R3
643 callerSaves (VanillaReg _ ILIT(3)) = True
645 #ifdef CALLER_SAVES_R4
646 callerSaves (VanillaReg _ ILIT(4)) = True
648 #ifdef CALLER_SAVES_R5
649 callerSaves (VanillaReg _ ILIT(5)) = True
651 #ifdef CALLER_SAVES_R6
652 callerSaves (VanillaReg _ ILIT(6)) = True
654 #ifdef CALLER_SAVES_R7
655 callerSaves (VanillaReg _ ILIT(7)) = True
657 #ifdef CALLER_SAVES_R8
658 callerSaves (VanillaReg _ ILIT(8)) = True
660 #ifdef CALLER_SAVES_FltReg1
661 callerSaves (FloatReg ILIT(1)) = True
663 #ifdef CALLER_SAVES_FltReg2
664 callerSaves (FloatReg ILIT(2)) = True
666 #ifdef CALLER_SAVES_FltReg3
667 callerSaves (FloatReg ILIT(3)) = True
669 #ifdef CALLER_SAVES_FltReg4
670 callerSaves (FloatReg ILIT(4)) = True
672 #ifdef CALLER_SAVES_DblReg1
673 callerSaves (DoubleReg ILIT(1)) = True
675 #ifdef CALLER_SAVES_DblReg2
676 callerSaves (DoubleReg ILIT(2)) = True
678 #ifdef CALLER_SAVES_Tag
679 callerSaves TagReg = True
681 #ifdef CALLER_SAVES_Ret
682 callerSaves RetReg = True
684 #ifdef CALLER_SAVES_SpA
685 callerSaves SpA = True
687 #ifdef CALLER_SAVES_SuA
688 callerSaves SuA = True
690 #ifdef CALLER_SAVES_SpB
691 callerSaves SpB = True
693 #ifdef CALLER_SAVES_SuB
694 callerSaves SuB = True
696 #ifdef CALLER_SAVES_Hp
697 callerSaves Hp = True
699 #ifdef CALLER_SAVES_HpLim
700 callerSaves HpLim = True
702 #ifdef CALLER_SAVES_Liveness
703 callerSaves LivenessReg = True
705 #ifdef CALLER_SAVES_StdUpdRetVec
706 callerSaves StdUpdRetVecReg = True
708 #ifdef CALLER_SAVES_StkStub
709 callerSaves StkStubReg = True
711 callerSaves _ = False
715 magicIdRegMaybe :: MagicId -> Maybe Reg
718 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
721 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
724 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
727 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
730 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
733 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
736 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
739 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
742 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
745 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
748 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
751 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
754 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
757 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
760 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
763 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
766 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
769 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
772 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
775 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
778 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
781 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
784 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
787 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
790 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
792 #ifdef REG_StdUpdRetVec
793 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
796 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
798 magicIdRegMaybe _ = Nothing
801 %************************************************************************
803 \subsection{Free, reserved, call-clobbered, and argument registers}
805 %************************************************************************
807 @freeRegs@ is the list of registers we can use in register allocation.
808 @freeReg@ (below) says if a particular register is free.
810 With a per-instruction clobber list, we might be able to get some of
811 these back, but it's probably not worth the hassle.
813 @callClobberedRegs@ ... the obvious.
815 @argRegs@: assuming a call with N arguments, what registers will be
816 used to hold arguments? (NB: it doesn't know whether the arguments
817 are integer or floating-point...)
820 reservedRegs :: [RegNo]
822 #if alpha_TARGET_ARCH
823 = [NCG_Reserved_I1, NCG_Reserved_I2,
824 NCG_Reserved_F1, NCG_Reserved_F2]
827 = [{-certainly cannot afford any!-}]
829 #if sparc_TARGET_ARCH
830 = [NCG_Reserved_I1, NCG_Reserved_I2,
831 NCG_Reserved_F1, NCG_Reserved_F2,
832 NCG_Reserved_D1, NCG_Reserved_D2]
835 -------------------------------
838 = freeMappedRegs IF_ARCH_alpha( [0..63],
839 IF_ARCH_i386( [0..15],
840 IF_ARCH_sparc( [0..63],)))
842 -------------------------------
843 callClobberedRegs :: [Reg]
846 #if alpha_TARGET_ARCH
847 [0, 1, 2, 3, 4, 5, 6, 7, 8,
848 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
849 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
850 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
851 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
852 #endif {- alpha_TARGET_ARCH -}
855 #endif {- i386_TARGET_ARCH -}
856 #if sparc_TARGET_ARCH
858 [oReg i | i <- [0..5]] ++
859 [gReg i | i <- [1..7]] ++
860 [fReg i | i <- [0..31]] )
861 #endif {- sparc_TARGET_ARCH -}
863 -------------------------------
864 argRegs :: Int -> [Reg]
867 #if alpha_TARGET_ARCH
868 argRegs 1 = freeMappedRegs [16, fReg 16]
869 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
870 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
871 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
872 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
873 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
874 #endif {- alpha_TARGET_ARCH -}
876 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
877 #endif {- i386_TARGET_ARCH -}
878 #if sparc_TARGET_ARCH
879 argRegs 1 = freeMappedRegs (map oReg [0])
880 argRegs 2 = freeMappedRegs (map oReg [0,1])
881 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
882 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
883 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
884 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
885 #endif {- sparc_TARGET_ARCH -}
886 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
888 -------------------------------
890 #if alpha_TARGET_ARCH
891 allArgRegs :: [(Reg, Reg)]
893 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
894 #endif {- alpha_TARGET_ARCH -}
896 #if sparc_TARGET_ARCH
899 allArgRegs = map realReg [oReg i | i <- [0..5]]
900 #endif {- sparc_TARGET_ARCH -}
902 -------------------------------
903 freeMappedRegs :: [Int] -> [Reg]
909 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
913 freeReg :: FAST_INT -> FAST_BOOL
915 #if alpha_TARGET_ARCH
916 freeReg ILIT(26) = _FALSE_ -- return address (ra)
917 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
918 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
919 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
920 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
921 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
925 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
928 #if sparc_TARGET_ARCH
929 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
930 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
931 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
932 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
933 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
934 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
938 freeReg ILIT(REG_Base) = _FALSE_
941 freeReg ILIT(REG_StkO) = _FALSE_
944 freeReg ILIT(REG_R1) = _FALSE_
947 freeReg ILIT(REG_R2) = _FALSE_
950 freeReg ILIT(REG_R3) = _FALSE_
953 freeReg ILIT(REG_R4) = _FALSE_
956 freeReg ILIT(REG_R5) = _FALSE_
959 freeReg ILIT(REG_R6) = _FALSE_
962 freeReg ILIT(REG_R7) = _FALSE_
965 freeReg ILIT(REG_R8) = _FALSE_
968 freeReg ILIT(REG_Flt1) = _FALSE_
971 freeReg ILIT(REG_Flt2) = _FALSE_
974 freeReg ILIT(REG_Flt3) = _FALSE_
977 freeReg ILIT(REG_Flt4) = _FALSE_
980 freeReg ILIT(REG_Dbl1) = _FALSE_
983 freeReg ILIT(REG_Dbl2) = _FALSE_
986 freeReg ILIT(REG_Tag) = _FALSE_
989 freeReg ILIT(REG_Ret) = _FALSE_
992 freeReg ILIT(REG_SpA) = _FALSE_
995 freeReg ILIT(REG_SuA) = _FALSE_
998 freeReg ILIT(REG_SpB) = _FALSE_
1001 freeReg ILIT(REG_SuB) = _FALSE_
1004 freeReg ILIT(REG_Hp) = _FALSE_
1007 freeReg ILIT(REG_HpLim) = _FALSE_
1010 freeReg ILIT(REG_Liveness) = _FALSE_
1012 #ifdef REG_StdUpdRetVec
1013 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1016 freeReg ILIT(REG_StkStub) = _FALSE_
1020 -- we hang onto two double regs for dedicated
1021 -- use; this is not necessary on Alphas and
1022 -- may not be on other non-SPARCs.
1024 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1027 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1029 | otherwise = _TRUE_