2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
17 RegClass(..), regClass,
18 Reg(..), isRealReg, isVirtualReg,
19 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
41 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
44 , eax, ebx, ecx, edx, esi, esp
45 , fake0, fake1, fake2, fake3, fake4, fake5
49 , fpRel, gReg, iReg, lReg, oReg, largeOffsetError
50 , fp, sp, g0, g1, g2, o0, f0, f6, f8, f26, f27
55 #include "HsVersions.h"
57 import AbsCSyn ( MagicId(..) )
58 import AbsCUtils ( magicIdPrimRep )
59 import CLabel ( CLabel, mkMainRegTableLabel )
60 import PrimOp ( PrimOp(..) )
61 import PrimRep ( PrimRep(..), isFloatingRep )
62 import Stix ( StixTree(..), StixReg(..),
63 getUniqueNat, returnNat, thenNat, NatM )
64 import Unique ( mkPseudoUnique2, Uniquable(..), Unique )
68 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
73 | ImmInteger Integer -- Sigh.
74 | ImmCLbl CLabel -- AbstractC Label (with baggage)
75 | ImmLab Bool SDoc -- Simple string label (underscore-able)
76 -- Bool==True ==> in a different DLL
77 | ImmLit SDoc -- Simple string
82 | LO Imm -- Possible restrictions...
85 strImmLit s = ImmLit (text s)
88 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
99 = AddrBaseIndex Base Index Displacement
102 type Base = Maybe Reg
103 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
104 type Displacement = Imm
107 #if sparc_TARGET_ARCH
112 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
116 #if alpha_TARGET_ARCH
117 _ -> panic "MachMisc.addrOffset not defined for Alpha"
120 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
121 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
122 AddrBaseIndex r i (ImmInteger n)
123 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
126 #if sparc_TARGET_ARCH
127 AddrRegImm r (ImmInt n)
128 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
129 | otherwise -> Nothing
132 AddrRegImm r (ImmInteger n)
133 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
134 | otherwise -> Nothing
135 where n2 = n + toInteger off
137 AddrRegReg r (RealReg 0)
138 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
139 | otherwise -> Nothing
146 #if alpha_TARGET_ARCH
148 fits8Bits :: Integer -> Bool
149 fits8Bits i = i >= -256 && i < 256
153 #if sparc_TARGET_ARCH
155 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
156 fits13Bits :: Integral a => a -> Bool
157 fits13Bits x = x >= -4096 && x < 4096
161 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
162 ++show i++");\nprobably because of large constant data structures;" ++
163 "\nworkaround: use -fvia-C on this module.\n")
168 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
170 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
171 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
172 The rest are either in real machine registers or stored as offsets
176 data RegLoc = Save StixTree | Always StixTree
179 Trees for register save locations:
181 saveLoc :: MagicId -> StixTree
183 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
187 stgReg :: MagicId -> RegLoc
190 = case (magicIdRegMaybe x) of
191 Just _ -> Save nonReg
192 Nothing -> Always nonReg
194 offset = baseRegOffset x
196 baseLoc = case (magicIdRegMaybe BaseReg) of
197 Just _ -> StReg (StixMagicId BaseReg)
198 Nothing -> StCLbl mkMainRegTableLabel
201 BaseReg -> StCLbl mkMainRegTableLabel
203 _ -> StInd (magicIdPrimRep x)
204 (StPrim IntAddOp [baseLoc,
205 StInt (toInteger (offset*BYTES_PER_WORD))])
208 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
210 @spRel@ gives us a stack relative addressing mode for volatile
211 temporaries and for excess call arguments. @fpRel@, where
212 applicable, is the same but for the frame pointer.
215 spRel :: Int -- desired stack offset in words, positive or negative
220 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
222 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
225 #if sparc_TARGET_ARCH
226 fpRel :: Int -> MachRegsAddr
227 -- Duznae work for offsets greater than 13 bits; we just hope for
230 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
234 %************************************************************************
236 \subsection[Reg]{Real registers}
238 %************************************************************************
240 RealRegs are machine regs which are available for allocation, in the
241 usual way. We know what class they are, because that's part of the
242 processor's architecture.
244 VirtualRegs are virtual registers. The register allocator will
245 eventually have to map them into RealRegs, or into spill slots.
246 VirtualRegs are allocated on the fly, usually to represent a single
247 value in the abstract assembly code (i.e. dynamic registers are
248 usually single assignment). With the new register allocator, the
249 single assignment restriction isn't necessary to get correct code,
250 although a better register allocation will result if single assignment
251 is used -- because the allocator maps a VirtualReg into a single
252 RealReg, even if the VirtualReg has multiple live ranges.
254 Virtual regs can be of either class, so that info is attached.
270 unRealReg (RealReg i) = i
271 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
273 mkVReg :: Unique -> PrimRep -> Reg
275 #if sparc_TARGET_ARCH
277 FloatRep -> VirtualRegF u
278 DoubleRep -> VirtualRegD u
279 other -> VirtualRegI u
281 = if isFloatingRep pk then VirtualRegD u else VirtualRegI u
284 isVirtualReg (RealReg _) = False
285 isVirtualReg (VirtualRegI _) = True
286 isVirtualReg (VirtualRegF _) = True
287 isVirtualReg (VirtualRegD _) = True
288 isRealReg = not . isVirtualReg
290 getNewRegNCG :: PrimRep -> NatM Reg
292 = getUniqueNat `thenNat` \ u -> returnNat (mkVReg u pk)
294 instance Eq Reg where
295 (==) (RealReg i1) (RealReg i2) = i1 == i2
296 (==) (VirtualRegI u1) (VirtualRegI u2) = u1 == u2
297 (==) (VirtualRegF u1) (VirtualRegF u2) = u1 == u2
298 (==) (VirtualRegD u1) (VirtualRegD u2) = u1 == u2
299 (==) reg1 reg2 = False
301 instance Ord Reg where
302 compare (RealReg i1) (RealReg i2) = compare i1 i2
303 compare (RealReg _) (VirtualRegI _) = LT
304 compare (RealReg _) (VirtualRegF _) = LT
305 compare (RealReg _) (VirtualRegD _) = LT
307 compare (VirtualRegI _) (RealReg _) = GT
308 compare (VirtualRegI u1) (VirtualRegI u2) = compare u1 u2
309 compare (VirtualRegI _) (VirtualRegF _) = LT
310 compare (VirtualRegI _) (VirtualRegD _) = LT
312 compare (VirtualRegF _) (RealReg _) = GT
313 compare (VirtualRegF _) (VirtualRegI _) = GT
314 compare (VirtualRegF u1) (VirtualRegF u2) = compare u1 u2
315 compare (VirtualRegF _) (VirtualRegD _) = LT
317 compare (VirtualRegD _) (RealReg _) = GT
318 compare (VirtualRegD _) (VirtualRegI _) = GT
319 compare (VirtualRegD _) (VirtualRegF _) = GT
320 compare (VirtualRegD u1) (VirtualRegD u2) = compare u1 u2
323 instance Show Reg where
324 showsPrec _ (RealReg i) = showString (showReg i)
325 showsPrec _ (VirtualRegI u) = showString "%vI_" . shows u
326 showsPrec _ (VirtualRegF u) = showString "%vF_" . shows u
327 showsPrec _ (VirtualRegD u) = showString "%vD_" . shows u
329 instance Outputable Reg where
330 ppr r = text (show r)
332 instance Uniquable Reg where
333 getUnique (RealReg i) = mkPseudoUnique2 i
334 getUnique (VirtualRegI u) = u
335 getUnique (VirtualRegF u) = u
336 getUnique (VirtualRegD u) = u
339 ** Machine-specific Reg stuff: **
341 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
342 point registers. The mapping of STG registers to alpha machine registers
343 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
345 #if alpha_TARGET_ARCH
349 v0, f0, ra, pv, gp, sp, zeroh :: Reg
351 f0 = realReg (fReg 0)
352 ra = FixedReg ILIT(26)
354 gp = FixedReg ILIT(29)
355 sp = FixedReg ILIT(30)
356 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
358 t9, t10, t11, t12 :: Reg
366 Intel x86 architecture:
367 - All registers except 7 (esp) are available for use.
368 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
369 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
370 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
371 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
372 fp registers, and 3-operand insns for them, and we translate this into
373 real stack-based x86 fp code after register allocation.
375 The fp registers are all Double registers; we don't have any RcFloat class
376 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
382 fake0, fake1, fake2, fake3, fake4, fake5,
383 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
399 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
400 regClass (VirtualRegI u) = RcInteger
401 regClass (VirtualRegD u) = RcDouble
402 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
403 (ppr (VirtualRegF u))
406 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
407 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
409 showReg :: Int -> String
411 = if n >= 0 && n < 14
413 else "%unknown_x86_real_reg_" ++ show n
418 The SPARC has 64 registers of interest; 32 integer registers and 32
419 floating point registers. The mapping of STG registers to SPARC
420 machine registers is defined in StgRegs.h. We are, of course,
421 prepared for any eventuality.
423 The whole fp-register pairing thing on sparcs is a huge nuisance. See
424 fptools/ghc/includes/MachRegs.h for a description of what's going on
428 #if sparc_TARGET_ARCH
430 gReg,lReg,iReg,oReg,fReg :: Int -> Int
437 nCG_FirstFloatReg :: Int
438 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
440 regClass (VirtualRegI u) = RcInteger
441 regClass (VirtualRegF u) = RcFloat
442 regClass (VirtualRegD u) = RcDouble
443 regClass (RealReg i) | i < 32 = RcInteger
444 | i < nCG_FirstFloatReg = RcDouble
445 | otherwise = RcFloat
447 showReg :: Int -> String
449 | n >= 0 && n < 8 = "%g" ++ show n
450 | n >= 8 && n < 16 = "%o" ++ show (n-8)
451 | n >= 16 && n < 24 = "%l" ++ show (n-16)
452 | n >= 24 && n < 32 = "%i" ++ show (n-24)
453 | n >= 32 && n < 64 = "%f" ++ show (n-32)
454 | otherwise = "%unknown_sparc_real_reg_" ++ show n
456 g0, g1, g2, fp, sp, o0, f0, f1, f6, f8, f22, f26, f27 :: Reg
458 f6 = RealReg (fReg 6)
459 f8 = RealReg (fReg 8)
460 f22 = RealReg (fReg 22)
461 f26 = RealReg (fReg 26)
462 f27 = RealReg (fReg 27)
465 -- g0 is useful for codegen; is always zero, and writes to it vanish.
466 g0 = RealReg (gReg 0)
467 g1 = RealReg (gReg 1)
468 g2 = RealReg (gReg 2)
470 -- FP, SP, int and float return (from C) regs.
471 fp = RealReg (iReg 6)
472 sp = RealReg (oReg 6)
473 o0 = RealReg (oReg 0)
474 f0 = RealReg (fReg 0)
475 f1 = RealReg (fReg 1)
480 Redefine the literals used for machine-registers with non-numeric
481 names in the header files. Gag me with a spoon, eh?
483 #if alpha_TARGET_ARCH
533 #if sparc_TARGET_ARCH
604 baseRegOffset :: MagicId -> Int
606 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
607 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
608 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
609 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
610 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
611 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
612 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
613 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
614 baseRegOffset (VanillaReg _ ILIT(9)) = OFFSET_R9
615 baseRegOffset (VanillaReg _ ILIT(10)) = OFFSET_R10
616 baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1
617 baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2
618 baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3
619 baseRegOffset (FloatReg ILIT(4)) = OFFSET_F4
620 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_D1
621 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_D2
622 baseRegOffset Sp = OFFSET_Sp
623 baseRegOffset Su = OFFSET_Su
624 baseRegOffset SpLim = OFFSET_SpLim
626 baseRegOffset (LongReg _ ILIT(1)) = OFFSET_Lng1
629 baseRegOffset (LongReg _ ILIT(2)) = OFFSET_Lng2
631 baseRegOffset Hp = OFFSET_Hp
632 baseRegOffset HpLim = OFFSET_HpLim
633 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
634 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
636 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
637 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
638 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
643 callerSaves :: MagicId -> Bool
645 #ifdef CALLER_SAVES_Base
646 callerSaves BaseReg = True
648 #ifdef CALLER_SAVES_R1
649 callerSaves (VanillaReg _ ILIT(1)) = True
651 #ifdef CALLER_SAVES_R2
652 callerSaves (VanillaReg _ ILIT(2)) = True
654 #ifdef CALLER_SAVES_R3
655 callerSaves (VanillaReg _ ILIT(3)) = True
657 #ifdef CALLER_SAVES_R4
658 callerSaves (VanillaReg _ ILIT(4)) = True
660 #ifdef CALLER_SAVES_R5
661 callerSaves (VanillaReg _ ILIT(5)) = True
663 #ifdef CALLER_SAVES_R6
664 callerSaves (VanillaReg _ ILIT(6)) = True
666 #ifdef CALLER_SAVES_R7
667 callerSaves (VanillaReg _ ILIT(7)) = True
669 #ifdef CALLER_SAVES_R8
670 callerSaves (VanillaReg _ ILIT(8)) = True
672 #ifdef CALLER_SAVES_F1
673 callerSaves (FloatReg ILIT(1)) = True
675 #ifdef CALLER_SAVES_F2
676 callerSaves (FloatReg ILIT(2)) = True
678 #ifdef CALLER_SAVES_F3
679 callerSaves (FloatReg ILIT(3)) = True
681 #ifdef CALLER_SAVES_F4
682 callerSaves (FloatReg ILIT(4)) = True
684 #ifdef CALLER_SAVES_D1
685 callerSaves (DoubleReg ILIT(1)) = True
687 #ifdef CALLER_SAVES_D2
688 callerSaves (DoubleReg ILIT(2)) = True
690 #ifdef CALLER_SAVES_L1
691 callerSaves (LongReg _ ILIT(1)) = True
693 #ifdef CALLER_SAVES_Sp
694 callerSaves Sp = True
696 #ifdef CALLER_SAVES_Su
697 callerSaves Su = True
699 #ifdef CALLER_SAVES_SpLim
700 callerSaves SpLim = True
702 #ifdef CALLER_SAVES_Hp
703 callerSaves Hp = True
705 #ifdef CALLER_SAVES_HpLim
706 callerSaves HpLim = True
708 #ifdef CALLER_SAVES_CurrentTSO
709 callerSaves CurrentTSO = True
711 #ifdef CALLER_SAVES_CurrentNursery
712 callerSaves CurrentNursery = True
714 callerSaves _ = False
718 magicIdRegMaybe :: MagicId -> Maybe Reg
721 magicIdRegMaybe BaseReg = Just (RealReg REG_Base)
724 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (RealReg REG_R1)
727 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (RealReg REG_R2)
730 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (RealReg REG_R3)
733 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (RealReg REG_R4)
736 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (RealReg REG_R5)
739 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (RealReg REG_R6)
742 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (RealReg REG_R7)
745 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (RealReg REG_R8)
748 magicIdRegMaybe (VanillaReg _ ILIT(9)) = Just (RealReg REG_R9)
751 magicIdRegMaybe (VanillaReg _ ILIT(10)) = Just (RealReg REG_R10)
754 magicIdRegMaybe (FloatReg ILIT(1)) = Just (RealReg REG_F1)
757 magicIdRegMaybe (FloatReg ILIT(2)) = Just (RealReg REG_F2)
760 magicIdRegMaybe (FloatReg ILIT(3)) = Just (RealReg REG_F3)
763 magicIdRegMaybe (FloatReg ILIT(4)) = Just (RealReg REG_F4)
766 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (RealReg REG_D1)
769 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (RealReg REG_D2)
772 magicIdRegMaybe Sp = Just (RealReg REG_Sp)
775 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (RealReg REG_Lng1)
778 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (RealReg REG_Lng2)
781 magicIdRegMaybe Su = Just (RealReg REG_Su)
784 magicIdRegMaybe SpLim = Just (RealReg REG_SpLim)
787 magicIdRegMaybe Hp = Just (RealReg REG_Hp)
790 magicIdRegMaybe HpLim = Just (RealReg REG_HpLim)
792 #ifdef REG_CurrentTSO
793 magicIdRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
795 #ifdef REG_CurrentNursery
796 magicIdRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
798 magicIdRegMaybe _ = Nothing
802 -------------------------------
803 -- allMachRegs is the complete set of machine regs.
804 allMachRegNos :: [Int]
806 = IF_ARCH_alpha( [0..63],
807 IF_ARCH_i386( [0..13],
808 IF_ARCH_sparc( ([0..31]
809 ++ [f0,f2 .. nCG_FirstFloatReg-1]
810 ++ [nCG_FirstFloatReg .. f31]),
812 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
813 -- i.e., these are the regs for which we are prepared to allow the
814 -- register allocator to attempt to map VRegs to.
815 allocatableRegs :: [Reg]
817 = let isFree (I# i) = _IS_TRUE_(freeReg i)
818 in map RealReg (filter isFree allMachRegNos)
820 -------------------------------
821 -- these are the regs which we cannot assume stay alive over a
823 callClobberedRegs :: [Reg]
826 #if alpha_TARGET_ARCH
827 [0, 1, 2, 3, 4, 5, 6, 7, 8,
828 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
829 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
830 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
831 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
832 #endif {- alpha_TARGET_ARCH -}
834 -- caller-saves registers
835 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
836 #endif {- i386_TARGET_ARCH -}
837 #if sparc_TARGET_ARCH
840 [oReg i | i <- [0..5]] ++
841 [gReg i | i <- [1..7]] ++
842 [fReg i | i <- [0..31]] )
843 #endif {- sparc_TARGET_ARCH -}
845 -------------------------------
846 -- argRegs is the set of regs which are read for an n-argument call to C.
847 -- For archs which pass all args on the stack (x86), is empty.
848 -- Sparc passes up to the first 6 args in regs.
849 -- Dunno about Alpha.
850 argRegs :: Int -> [Reg]
853 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
856 #if alpha_TARGET_ARCH
858 argRegs 1 = freeMappedRegs [16, fReg 16]
859 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
860 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
861 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
862 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
863 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
864 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
865 #endif {- alpha_TARGET_ARCH -}
867 #if sparc_TARGET_ARCH
869 argRegs 1 = map (RealReg . oReg) [0]
870 argRegs 2 = map (RealReg . oReg) [0,1]
871 argRegs 3 = map (RealReg . oReg) [0,1,2]
872 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
873 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
874 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
875 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
876 #endif {- sparc_TARGET_ARCH -}
878 -------------------------------
879 -- all of the arg regs ??
880 #if alpha_TARGET_ARCH
881 allArgRegs :: [(Reg, Reg)]
882 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
883 #endif {- alpha_TARGET_ARCH -}
885 #if sparc_TARGET_ARCH
887 allArgRegs = map RealReg [oReg i | i <- [0..5]]
888 #endif {- sparc_TARGET_ARCH -}
892 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
897 freeReg :: FastInt -> FastBool
899 #if alpha_TARGET_ARCH
900 freeReg ILIT(26) = fastBool False -- return address (ra)
901 freeReg ILIT(28) = fastBool False -- reserved for the assembler (at)
902 freeReg ILIT(29) = fastBool False -- global pointer (gp)
903 freeReg ILIT(30) = fastBool False -- stack pointer (sp)
904 freeReg ILIT(31) = fastBool False -- always zero (zeroh)
905 freeReg ILIT(63) = fastBool False -- always zero (f31)
909 freeReg ILIT(esp) = fastBool False -- %esp is the C stack pointer
912 #if sparc_TARGET_ARCH
913 freeReg ILIT(g0) = fastBool False -- %g0 is always 0.
914 freeReg ILIT(g5) = fastBool False -- %g5 is reserved (ABI).
915 freeReg ILIT(g6) = fastBool False -- %g6 is reserved (ABI).
916 freeReg ILIT(g7) = fastBool False -- %g7 is reserved (ABI).
917 freeReg ILIT(i6) = fastBool False -- %i6 is our frame pointer.
918 freeReg ILIT(o6) = fastBool False -- %o6 is our stack pointer.
919 freeReg ILIT(f0) = fastBool False -- %f0/%f1 are the C fp return registers.
920 freeReg ILIT(f1) = fastBool False
924 freeReg ILIT(REG_Base) = fastBool False
927 freeReg ILIT(REG_R1) = fastBool False
930 freeReg ILIT(REG_R2) = fastBool False
933 freeReg ILIT(REG_R3) = fastBool False
936 freeReg ILIT(REG_R4) = fastBool False
939 freeReg ILIT(REG_R5) = fastBool False
942 freeReg ILIT(REG_R6) = fastBool False
945 freeReg ILIT(REG_R7) = fastBool False
948 freeReg ILIT(REG_R8) = fastBool False
951 freeReg ILIT(REG_F1) = fastBool False
954 freeReg ILIT(REG_F2) = fastBool False
957 freeReg ILIT(REG_F3) = fastBool False
960 freeReg ILIT(REG_F4) = fastBool False
963 freeReg ILIT(REG_D1) = fastBool False
966 freeReg ILIT(REG_D2) = fastBool False
969 freeReg ILIT(REG_Sp) = fastBool False
972 freeReg ILIT(REG_Su) = fastBool False
975 freeReg ILIT(REG_SpLim) = fastBool False
978 freeReg ILIT(REG_Hp) = fastBool False
981 freeReg ILIT(REG_HpLim) = fastBool False
983 freeReg n = fastBool True