1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
47 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
56 eax, ebx, ecx, edx, esi, edi, ebp, esp,
57 r8, r9, r10, r11, r12, r13, r14, r15,
58 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
59 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
61 addrModeRegs, allFPArgRegs,
65 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
66 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
68 #if powerpc_TARGET_ARCH
77 #include "HsVersions.h"
80 # define STOLEN_X86_REGS 4
81 -- HACK: go for the max
84 #include "../includes/MachRegs.h"
87 import MachOp ( MachRep(..) )
89 import CLabel ( CLabel, mkMainCapabilityLabel )
90 import Unique ( Unique )
92 import Outputable ( Outputable(..), pprPanic, panic )
93 import qualified Outputable
98 #if powerpc_TARGET_ARCH
99 #if __GLASGOW_HASKELL__ >= 504
100 import Data.Word ( Word8, Word16, Word32 )
101 import Data.Int ( Int8, Int16, Int32 )
103 import Word ( Word8, Word16, Word32 )
104 import Int ( Int8, Int16, Int32 )
108 -- -----------------------------------------------------------------------------
113 | ImmInteger Integer -- Sigh.
114 | ImmCLbl CLabel -- AbstractC Label (with baggage)
115 | ImmLit Doc -- Simple string
116 | ImmIndex CLabel Int
119 | ImmConstantSum Imm Imm
120 | ImmConstantDiff Imm Imm
121 #if sparc_TARGET_ARCH
122 | LO Imm {- Possible restrictions... -}
125 #if powerpc_TARGET_ARCH
128 | HA Imm {- high halfword adjusted -}
130 strImmLit s = ImmLit (text s)
132 litToImm :: CmmLit -> Imm
133 litToImm (CmmInt i _) = ImmInteger i
134 litToImm (CmmFloat f F32) = ImmFloat f
135 litToImm (CmmFloat f F64) = ImmDouble f
136 litToImm (CmmLabel l) = ImmCLbl l
137 litToImm (CmmLabelOff l off) = ImmIndex l off
138 litToImm (CmmLabelDiffOff l1 l2 off)
140 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
143 -- -----------------------------------------------------------------------------
147 #if alpha_TARGET_ARCH
153 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
154 = AddrBaseIndex Base Index Displacement
157 type Base = Maybe Reg
158 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
159 type Displacement = Imm
162 #if sparc_TARGET_ARCH
167 #if powerpc_TARGET_ARCH
172 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
173 addrModeRegs :: AddrMode -> [Reg]
174 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
176 b_regs = case b of { Just r -> [r]; _ -> [] }
177 i_regs = case i of { Just (r,_) -> [r]; _ -> [] }
182 addrOffset :: AddrMode -> Int -> Maybe AddrMode
186 #if alpha_TARGET_ARCH
187 _ -> panic "MachMisc.addrOffset not defined for Alpha"
189 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
190 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
192 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
193 AddrBaseIndex r i (ImmInteger n)
194 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
196 AddrBaseIndex r i (ImmCLbl lbl)
197 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
199 AddrBaseIndex r i (ImmIndex lbl ix)
200 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
202 _ -> Nothing -- in theory, shouldn't happen
204 #if sparc_TARGET_ARCH
205 AddrRegImm r (ImmInt n)
206 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
207 | otherwise -> Nothing
210 AddrRegImm r (ImmInteger n)
211 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
212 | otherwise -> Nothing
213 where n2 = n + toInteger off
215 AddrRegReg r (RealReg 0)
216 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
217 | otherwise -> Nothing
221 #if powerpc_TARGET_ARCH
222 AddrRegImm r (ImmInt n)
223 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
224 | otherwise -> Nothing
227 AddrRegImm r (ImmInteger n)
228 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
229 | otherwise -> Nothing
230 where n2 = n + toInteger off
236 #if alpha_TARGET_ARCH
238 fits8Bits :: Integer -> Bool
239 fits8Bits i = i >= -256 && i < 256
243 #if sparc_TARGET_ARCH
245 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
246 fits13Bits :: Integral a => a -> Bool
247 fits13Bits x = x >= -4096 && x < 4096
251 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
252 ++show i++");\nprobably because of large constant data structures;" ++
253 "\nworkaround: use -fvia-C on this module.\n")
257 #if powerpc_TARGET_ARCH
258 fits16Bits :: Integral a => a -> Bool
259 fits16Bits x = x >= -32768 && x < 32768
261 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
263 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
265 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
266 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
267 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
268 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
269 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
270 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
272 narrowed = narrow rep signed
275 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
276 | otherwise = Nothing
278 | narrowed >= 0 && narrowed < 65536 = Just narrowed
279 | otherwise = Nothing
280 toI16 _ _ = Just narrowed
284 -- @spRel@ gives us a stack relative addressing mode for volatile
285 -- temporaries and for excess call arguments. @fpRel@, where
286 -- applicable, is the same but for the frame pointer.
288 spRel :: Int -- desired stack offset in words, positive or negative
292 #if defined(i386_TARGET_ARCH)
293 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * wORD_SIZE))
294 #elif defined(x86_64_TARGET_ARCH)
295 = AddrBaseIndex (Just rsp) Nothing (ImmInt (n * wORD_SIZE))
297 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
300 #if sparc_TARGET_ARCH
301 fpRel :: Int -> AddrMode
302 -- Duznae work for offsets greater than 13 bits; we just hope for
305 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
309 -- -----------------------------------------------------------------------------
312 -- We map STG registers onto appropriate CmmExprs. Either they map
313 -- to real machine registers or stored as offsets from BaseReg. Given
314 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
315 -- register it is in, on this platform, or a StixExpr denoting the
316 -- address in the register table holding it. get_MagicId_addr always
317 -- produces the register table address for it.
319 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
320 get_GlobalReg_addr :: GlobalReg -> CmmExpr
321 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
323 get_GlobalReg_reg_or_addr mid
324 = case globalRegMaybe mid of
326 Nothing -> Right (get_GlobalReg_addr mid)
328 get_GlobalReg_addr BaseReg = regTableOffset 0
329 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
330 (globalRegRep mid) (baseRegOffset mid)
332 -- Calculate a literal representing an offset into the register table.
333 -- Used when we don't have an actual BaseReg to offset from.
335 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
337 get_Regtable_addr_from_offset rep offset
338 = case globalRegMaybe BaseReg of
339 Nothing -> regTableOffset offset
340 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
342 -- ---------------------------------------------------------------------------
345 -- RealRegs are machine regs which are available for allocation, in
346 -- the usual way. We know what class they are, because that's part of
347 -- the processor's architecture.
349 -- VirtualRegs are virtual registers. The register allocator will
350 -- eventually have to map them into RealRegs, or into spill slots.
351 -- VirtualRegs are allocated on the fly, usually to represent a single
352 -- value in the abstract assembly code (i.e. dynamic registers are
353 -- usually single assignment). With the new register allocator, the
354 -- single assignment restriction isn't necessary to get correct code,
355 -- although a better register allocation will result if single
356 -- assignment is used -- because the allocator maps a VirtualReg into
357 -- a single RealReg, even if the VirtualReg has multiple live ranges.
359 -- Virtual regs can be of either class, so that info is attached.
361 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
362 -- when supplied with the vreg for the lower-half of the quantity.
363 -- (NB. Not reversible).
364 getHiVRegFromLo (VirtualRegI u)
365 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
366 getHiVRegFromLo other
367 = pprPanic "getHiVRegFromLo" (ppr other)
378 = RealReg {-# UNPACK #-} !RegNo
379 | VirtualRegI {-# UNPACK #-} !Unique
380 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
381 | VirtualRegF {-# UNPACK #-} !Unique
382 | VirtualRegD {-# UNPACK #-} !Unique
385 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
386 -- in the register allocator.
387 instance Uniquable Reg where
388 getUnique (RealReg i) = mkUnique 'C' i
389 getUnique (VirtualRegI u) = u
390 getUnique (VirtualRegHi u) = u
391 getUnique (VirtualRegF u) = u
392 getUnique (VirtualRegD u) = u
394 mkVReg :: Unique -> MachRep -> Reg
397 #if sparc_TARGET_ARCH
403 other -> VirtualRegI u
405 isVirtualReg :: Reg -> Bool
406 isVirtualReg (RealReg _) = False
407 isVirtualReg (VirtualRegI _) = True
408 isVirtualReg (VirtualRegHi _) = True
409 isVirtualReg (VirtualRegF _) = True
410 isVirtualReg (VirtualRegD _) = True
412 isRealReg :: Reg -> Bool
413 isRealReg = not . isVirtualReg
415 instance Show Reg where
416 show (RealReg i) = showReg i
417 show (VirtualRegI u) = "%vI_" ++ show u
418 show (VirtualRegHi u) = "%vHi_" ++ show u
419 show (VirtualRegF u) = "%vF_" ++ show u
420 show (VirtualRegD u) = "%vD_" ++ show u
422 instance Outputable Reg where
423 ppr r = Outputable.text (show r)
426 -- -----------------------------------------------------------------------------
427 -- Machine-specific register stuff
429 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
430 -- point registers. The mapping of STG registers to alpha machine registers
431 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
433 #if alpha_TARGET_ARCH
437 v0, f0, ra, pv, gp, sp, zeroh :: Reg
439 f0 = realReg (fReg 0)
440 ra = FixedReg ILIT(26)
442 gp = FixedReg ILIT(29)
443 sp = FixedReg ILIT(30)
444 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
446 t9, t10, t11, t12 :: Reg
454 Intel x86 architecture:
455 - All registers except 7 (esp) are available for use.
456 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
457 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
458 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
459 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
460 fp registers, and 3-operand insns for them, and we translate this into
461 real stack-based x86 fp code after register allocation.
463 The fp registers are all Double registers; we don't have any RcFloat class
464 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
470 fake0, fake1, fake2, fake3, fake4, fake5,
471 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
487 -- On x86, we might want to have an 8-bit RegClass, which would
488 -- contain just regs 1-4 (the others don't have 8-bit versions).
489 -- However, we can get away without this at the moment because the
490 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
491 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
492 regClass (VirtualRegI u) = RcInteger
493 regClass (VirtualRegHi u) = RcInteger
494 regClass (VirtualRegD u) = RcDouble
495 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
496 (ppr (VirtualRegF u))
499 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
500 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
502 showReg :: RegNo -> String
504 = if n >= 0 && n < 14
506 else "%unknown_x86_real_reg_" ++ show n
511 AMD x86_64 architecture:
512 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
513 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
514 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
518 #if x86_64_TARGET_ARCH
520 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
521 r8, r9, r10, r11, r12, r13, r14, r15,
522 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
523 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
558 -- so we can re-use some x86 code:
568 xmm n = RealReg (16+n)
570 -- On x86, we might want to have an 8-bit RegClass, which would
571 -- contain just regs 1-4 (the others don't have 8-bit versions).
572 -- However, we can get away without this at the moment because the
573 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
574 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
575 regClass (VirtualRegI u) = RcInteger
576 regClass (VirtualRegHi u) = RcInteger
577 regClass (VirtualRegD u) = RcDouble
578 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
579 (ppr (VirtualRegF u))
582 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
584 showReg :: RegNo -> String
586 | n >= 16 = "%xmm" ++ show n
587 | n >= 8 = "%r" ++ show n
588 | otherwise = regNames !! n
593 The SPARC has 64 registers of interest; 32 integer registers and 32
594 floating point registers. The mapping of STG registers to SPARC
595 machine registers is defined in StgRegs.h. We are, of course,
596 prepared for any eventuality.
598 The whole fp-register pairing thing on sparcs is a huge nuisance. See
599 fptools/ghc/includes/MachRegs.h for a description of what's going on
603 #if sparc_TARGET_ARCH
605 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
612 nCG_FirstFloatReg :: RegNo
613 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
615 regClass (VirtualRegI u) = RcInteger
616 regClass (VirtualRegF u) = RcFloat
617 regClass (VirtualRegD u) = RcDouble
618 regClass (RealReg i) | i < 32 = RcInteger
619 | i < nCG_FirstFloatReg = RcDouble
620 | otherwise = RcFloat
622 showReg :: RegNo -> String
624 | n >= 0 && n < 8 = "%g" ++ show n
625 | n >= 8 && n < 16 = "%o" ++ show (n-8)
626 | n >= 16 && n < 24 = "%l" ++ show (n-16)
627 | n >= 24 && n < 32 = "%i" ++ show (n-24)
628 | n >= 32 && n < 64 = "%f" ++ show (n-32)
629 | otherwise = "%unknown_sparc_real_reg_" ++ show n
631 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
633 f6 = RealReg (fReg 6)
634 f8 = RealReg (fReg 8)
635 f22 = RealReg (fReg 22)
636 f26 = RealReg (fReg 26)
637 f27 = RealReg (fReg 27)
640 -- g0 is useful for codegen; is always zero, and writes to it vanish.
641 g0 = RealReg (gReg 0)
642 g1 = RealReg (gReg 1)
643 g2 = RealReg (gReg 2)
645 -- FP, SP, int and float return (from C) regs.
646 fp = RealReg (iReg 6)
647 sp = RealReg (oReg 6)
648 o0 = RealReg (oReg 0)
649 o1 = RealReg (oReg 1)
650 f0 = RealReg (fReg 0)
651 f1 = RealReg (fReg 1)
656 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
660 #if powerpc_TARGET_ARCH
664 regClass (VirtualRegI u) = RcInteger
665 regClass (VirtualRegHi u) = RcInteger
666 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
667 (ppr (VirtualRegF u))
668 regClass (VirtualRegD u) = RcDouble
669 regClass (RealReg i) | i < 32 = RcInteger
670 | otherwise = RcDouble
672 showReg :: RegNo -> String
674 | n >= 0 && n <= 31 = "%r" ++ show n
675 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
676 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
683 f1 = RealReg $ fReg 1
684 f20 = RealReg $ fReg 20
685 f21 = RealReg $ fReg 21
689 Redefine the literals used for machine-registers with non-numeric
690 names in the header files. Gag me with a spoon, eh?
693 #if alpha_TARGET_ARCH
744 #if x86_64_TARGET_ARCH
779 #if sparc_TARGET_ARCH
847 #if powerpc_TARGET_ARCH
881 #ifdef darwin_TARGET_OS
951 -- allMachRegs is the complete set of machine regs.
952 allMachRegNos :: [RegNo]
954 = IF_ARCH_alpha( [0..63],
955 IF_ARCH_i386( [0..13],
956 IF_ARCH_x86_64( [0..31],
957 IF_ARCH_sparc( ([0..31]
958 ++ [f0,f2 .. nCG_FirstFloatReg-1]
959 ++ [nCG_FirstFloatReg .. f31]),
960 IF_ARCH_powerpc([0..63],
963 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
964 -- i.e., these are the regs for which we are prepared to allow the
965 -- register allocator to attempt to map VRegs to.
966 allocatableRegs :: [RegNo]
968 = let isFree i = isFastTrue (freeReg i)
969 in filter isFree allMachRegNos
971 -- these are the regs which we cannot assume stay alive over a
973 callClobberedRegs :: [Reg]
976 #if alpha_TARGET_ARCH
977 [0, 1, 2, 3, 4, 5, 6, 7, 8,
978 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
979 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
980 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
981 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
982 #endif /* alpha_TARGET_ARCH */
984 -- caller-saves registers
985 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
986 #endif /* i386_TARGET_ARCH */
987 #if x86_64_TARGET_ARCH
988 -- caller-saves registers
989 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
990 -- all xmm regs are caller-saves
991 #endif /* x86_64_TARGET_ARCH */
992 #if sparc_TARGET_ARCH
995 [oReg i | i <- [0..5]] ++
996 [gReg i | i <- [1..7]] ++
997 [fReg i | i <- [0..31]] )
998 #endif /* sparc_TARGET_ARCH */
999 #if powerpc_TARGET_ARCH
1000 #if darwin_TARGET_OS
1001 map RealReg (0:[2..12] ++ map fReg [0..13])
1002 #elif linux_TARGET_OS
1003 map RealReg (0:[2..13] ++ map fReg [0..13])
1005 #endif /* powerpc_TARGET_ARCH */
1008 -- argRegs is the set of regs which are read for an n-argument call to C.
1009 -- For archs which pass all args on the stack (x86), is empty.
1010 -- Sparc passes up to the first 6 args in regs.
1011 -- Dunno about Alpha.
1012 argRegs :: RegNo -> [Reg]
1014 #if i386_TARGET_ARCH
1015 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1018 #if x86_64_TARGET_ARCH
1019 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1022 #if alpha_TARGET_ARCH
1024 argRegs 1 = freeMappedRegs [16, fReg 16]
1025 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1026 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1027 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1028 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1029 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1030 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1031 #endif /* alpha_TARGET_ARCH */
1033 #if sparc_TARGET_ARCH
1035 argRegs 1 = map (RealReg . oReg) [0]
1036 argRegs 2 = map (RealReg . oReg) [0,1]
1037 argRegs 3 = map (RealReg . oReg) [0,1,2]
1038 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1039 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1040 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1041 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1042 #endif /* sparc_TARGET_ARCH */
1044 #if powerpc_TARGET_ARCH
1046 argRegs 1 = map RealReg [3]
1047 argRegs 2 = map RealReg [3,4]
1048 argRegs 3 = map RealReg [3..5]
1049 argRegs 4 = map RealReg [3..6]
1050 argRegs 5 = map RealReg [3..7]
1051 argRegs 6 = map RealReg [3..8]
1052 argRegs 7 = map RealReg [3..9]
1053 argRegs 8 = map RealReg [3..10]
1054 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1055 #endif /* powerpc_TARGET_ARCH */
1058 -- all of the arg regs ??
1059 #if alpha_TARGET_ARCH
1060 allArgRegs :: [(Reg, Reg)]
1061 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1062 #endif /* alpha_TARGET_ARCH */
1064 #if sparc_TARGET_ARCH
1066 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1067 #endif /* sparc_TARGET_ARCH */
1069 #if i386_TARGET_ARCH
1071 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1074 #if x86_64_TARGET_ARCH
1076 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1077 allFPArgRegs :: [Reg]
1078 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1081 #if powerpc_TARGET_ARCH
1083 allArgRegs = map RealReg [3..10]
1084 allFPArgRegs :: [Reg]
1085 #if darwin_TARGET_OS
1086 allFPArgRegs = map (RealReg . fReg) [1..13]
1087 #elif linux_TARGET_OS
1088 allFPArgRegs = map (RealReg . fReg) [1..8]
1090 #endif /* powerpc_TARGET_ARCH */
1094 freeReg :: RegNo -> FastBool
1096 #if alpha_TARGET_ARCH
1097 freeReg 26 = fastBool False -- return address (ra)
1098 freeReg 28 = fastBool False -- reserved for the assembler (at)
1099 freeReg 29 = fastBool False -- global pointer (gp)
1100 freeReg 30 = fastBool False -- stack pointer (sp)
1101 freeReg 31 = fastBool False -- always zero (zeroh)
1102 freeReg 63 = fastBool False -- always zero (f31)
1105 #if i386_TARGET_ARCH
1106 freeReg esp = fastBool False -- %esp is the C stack pointer
1109 #if x86_64_TARGET_ARCH
1110 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1113 #if sparc_TARGET_ARCH
1114 freeReg g0 = fastBool False -- %g0 is always 0.
1115 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1116 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1117 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1118 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1119 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1120 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1121 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1122 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1123 freeReg f1 = fastBool False
1126 #if powerpc_TARGET_ARCH
1127 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1128 freeReg 1 = fastBool False -- The Stack Pointer
1129 #if !darwin_TARGET_OS
1130 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1131 freeReg 2 = fastBool False
1136 freeReg REG_Base = fastBool False
1139 freeReg REG_R1 = fastBool False
1142 freeReg REG_R2 = fastBool False
1145 freeReg REG_R3 = fastBool False
1148 freeReg REG_R4 = fastBool False
1151 freeReg REG_R5 = fastBool False
1154 freeReg REG_R6 = fastBool False
1157 freeReg REG_R7 = fastBool False
1160 freeReg REG_R8 = fastBool False
1163 freeReg REG_F1 = fastBool False
1166 freeReg REG_F2 = fastBool False
1169 freeReg REG_F3 = fastBool False
1172 freeReg REG_F4 = fastBool False
1175 freeReg REG_D1 = fastBool False
1178 freeReg REG_D2 = fastBool False
1181 freeReg REG_Sp = fastBool False
1184 freeReg REG_Su = fastBool False
1187 freeReg REG_SpLim = fastBool False
1190 freeReg REG_Hp = fastBool False
1193 freeReg REG_HpLim = fastBool False
1195 freeReg n = fastBool True
1198 -- -----------------------------------------------------------------------------
1199 -- Information about global registers
1201 baseRegOffset :: GlobalReg -> Int
1203 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1204 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1205 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1206 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1207 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1208 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1209 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1210 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1211 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1212 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1213 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1214 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1215 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1216 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1217 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1218 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1219 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1220 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1221 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1222 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1223 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1224 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1225 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1226 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1227 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1228 baseRegOffset GCFun = oFFSET_stgGCFun
1230 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1231 baseRegOffset _ = panic "baseRegOffset:other"
1235 -- | Returns 'True' if this global register is stored in a caller-saves
1236 -- machine register.
1238 callerSaves :: GlobalReg -> Bool
1240 #ifdef CALLER_SAVES_Base
1241 callerSaves BaseReg = True
1243 #ifdef CALLER_SAVES_R1
1244 callerSaves (VanillaReg _ ILIT(1)) = True
1246 #ifdef CALLER_SAVES_R2
1247 callerSaves (VanillaReg _ ILIT(2)) = True
1249 #ifdef CALLER_SAVES_R3
1250 callerSaves (VanillaReg _ ILIT(3)) = True
1252 #ifdef CALLER_SAVES_R4
1253 callerSaves (VanillaReg _ ILIT(4)) = True
1255 #ifdef CALLER_SAVES_R5
1256 callerSaves (VanillaReg _ ILIT(5)) = True
1258 #ifdef CALLER_SAVES_R6
1259 callerSaves (VanillaReg _ ILIT(6)) = True
1261 #ifdef CALLER_SAVES_R7
1262 callerSaves (VanillaReg _ ILIT(7)) = True
1264 #ifdef CALLER_SAVES_R8
1265 callerSaves (VanillaReg _ ILIT(8)) = True
1267 #ifdef CALLER_SAVES_F1
1268 callerSaves (FloatReg 1#) = True
1270 #ifdef CALLER_SAVES_F2
1271 callerSaves (FloatReg 2#) = True
1273 #ifdef CALLER_SAVES_F3
1274 callerSaves (FloatReg 3#) = True
1276 #ifdef CALLER_SAVES_F4
1277 callerSaves (FloatReg 4#) = True
1279 #ifdef CALLER_SAVES_D1
1280 callerSaves (DoubleReg 1#) = True
1282 #ifdef CALLER_SAVES_D2
1283 callerSaves (DoubleReg 2#) = True
1285 #ifdef CALLER_SAVES_L1
1286 callerSaves (LongReg _ ILIT(1)) = True
1288 #ifdef CALLER_SAVES_Sp
1289 callerSaves Sp = True
1291 #ifdef CALLER_SAVES_SpLim
1292 callerSaves SpLim = True
1294 #ifdef CALLER_SAVES_Hp
1295 callerSaves Hp = True
1297 #ifdef CALLER_SAVES_HpLim
1298 callerSaves HpLim = True
1300 #ifdef CALLER_SAVES_CurrentTSO
1301 callerSaves CurrentTSO = True
1303 #ifdef CALLER_SAVES_CurrentNursery
1304 callerSaves CurrentNursery = True
1306 callerSaves _ = False
1309 -- | Returns 'Nothing' if this global register is not stored
1310 -- in a real machine register, otherwise returns @'Just' reg@, where
1311 -- reg is the machine register it is stored in.
1313 globalRegMaybe :: GlobalReg -> Maybe Reg
1316 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1319 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1322 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1325 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1328 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1331 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1334 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1337 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1340 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1343 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1346 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1349 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1352 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1355 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1358 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1361 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1364 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1367 globalRegMaybe Sp = Just (RealReg REG_Sp)
1370 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1373 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1376 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1379 globalRegMaybe Hp = Just (RealReg REG_Hp)
1382 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1384 #ifdef REG_CurrentTSO
1385 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1387 #ifdef REG_CurrentNursery
1388 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1390 globalRegMaybe _ = Nothing