2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "HsVersions.h"
14 #include "nativeGen/NCG.h"
47 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
50 , eax, ebx, ecx, edx, esi, esp
51 , st0, st1, st2, st3, st4, st5, st6, st7
56 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
62 #if __GLASGOW_HASKELL__ >= 202
63 import GlaExts hiding (Addr)
69 import AbsCSyn ( MagicId(..) )
70 import AbsCUtils ( magicIdPrimRep )
71 import CLabel ( CLabel )
72 import Outputable ( Outputable(..) )
73 import Pretty ( Doc, text, rational )
74 import PrimOp ( PrimOp(..) )
75 import PrimRep ( PrimRep(..) )
76 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
79 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
80 Unique{-instance Ord3-}
82 import UniqSupply ( getUnique, returnUs, thenUs, SYN_IE(UniqSM) )
83 import Util ( panic, Ord3(..) )
86 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
91 | ImmInteger Integer -- Sigh.
92 | ImmCLbl CLabel -- AbstractC Label (with baggage)
93 | ImmLab Doc -- Simple string label (underscore-able)
94 | ImmLit Doc -- Simple string
96 | LO Imm -- Possible restrictions...
100 strImmLit s = ImmLit (text s)
103 IF_ARCH_alpha({-prepend nothing-}
104 ,IF_ARCH_i386( '0' : 'd' :
105 ,IF_ARCH_sparc('0' : 'r' :,)))
109 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
113 #if alpha_TARGET_ARCH
120 = Addr Base Index Displacement
123 type Base = Maybe Reg
124 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
125 type Displacement = Imm
128 #if sparc_TARGET_ARCH
133 addrOffset :: Addr -> Int -> Maybe Addr
137 #if alpha_TARGET_ARCH
138 _ -> panic "MachMisc.addrOffset not defined for Alpha"
141 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
142 Addr r i (ImmInt n) -> Just (Addr r i (ImmInt (n + off)))
143 Addr r i (ImmInteger n)
144 -> Just (Addr r i (ImmInt (fromInteger (n + toInteger off))))
147 #if sparc_TARGET_ARCH
148 AddrRegImm r (ImmInt n)
149 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
150 | otherwise -> Nothing
153 AddrRegImm r (ImmInteger n)
154 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
155 | otherwise -> Nothing
156 where n2 = n + toInteger off
158 AddrRegReg r (FixedReg ILIT(0))
159 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
160 | otherwise -> Nothing
167 #if alpha_TARGET_ARCH
169 fits8Bits :: Integer -> Bool
170 fits8Bits i = i >= -256 && i < 256
174 #if sparc_TARGET_ARCH
176 fits13Bits :: Int -> Bool
179 fits13Bits :: Integer -> Bool
182 fits13Bits :: Integral a => a -> Bool
183 fits13Bits x = x >= -4096 && x < 4096
187 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
192 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
194 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
195 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
196 The rest are either in real machine registers or stored as offsets
200 data RegLoc = Save StixTree | Always StixTree
203 Trees for register save locations:
205 saveLoc :: MagicId -> StixTree
207 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
211 stgReg :: MagicId -> RegLoc
214 = case (magicIdRegMaybe x) of
215 Just _ -> Save nonReg
216 Nothing -> Always nonReg
218 offset = baseRegOffset x
220 baseLoc = case (magicIdRegMaybe BaseReg) of
221 Just _ -> StReg (StixMagicId BaseReg)
222 Nothing -> sStLitLbl SLIT("MainRegTable")
225 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
226 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
227 BaseReg -> sStLitLbl SLIT("MainRegTable")
228 -- these Hp&HpLim cases perhaps should
229 -- not be here for i386 (???) WDP 96/03
230 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
231 HpLim -> StInd PtrRep (sStLitLbl
232 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
233 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
234 StInt (1*BYTES_PER_WORD)])
236 r2 = VanillaReg PtrRep ILIT(2)
237 infoptr = case (stgReg r2) of
239 Save _ -> StReg (StixMagicId r2)
240 _ -> StInd (magicIdPrimRep x)
241 (StPrim IntAddOp [baseLoc,
242 StInt (toInteger (offset*BYTES_PER_WORD))])
245 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
247 @spRel@ gives us a stack relative addressing mode for volatile
248 temporaries and for excess call arguments. @fpRel@, where
249 applicable, is the same but for the frame pointer.
252 spRel :: Int -- desired stack offset in words, positive or negative
257 = Addr (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
259 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
262 #if sparc_TARGET_ARCH
264 -- Duznae work for offsets greater than 13 bits; we just hope for
267 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
271 %************************************************************************
273 \subsection[Reg]{Real registers}
275 %************************************************************************
277 Static Registers correspond to actual machine registers. These should
278 be avoided until the last possible moment.
280 Dynamic registers are allocated on the fly, usually to represent a single
281 value in the abstract assembly code (i.e. dynamic registers are usually
282 single assignment). Ultimately, they are mapped to available machine
283 registers before spitting out the code.
287 = FixedReg FAST_INT -- A pre-allocated machine register
289 | MappedReg FAST_INT -- A dynamically allocated machine register
291 | MemoryReg Int PrimRep -- A machine "register" actually held in
292 -- a memory allocated table of
293 -- registers which didn't fit in real
296 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
297 -- always mapped to one of the earlier
298 -- two (?) before we're done.
300 mkReg :: Unique -> PrimRep -> Reg
303 getNewRegNCG :: PrimRep -> UniqSM Reg
305 = getUnique `thenUs` \ u ->
306 returnUs (UnmappedReg u pk)
308 instance Text Reg where
309 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
310 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
311 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
312 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
315 instance Outputable Reg where
316 ppr sty r = text (show r)
319 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
320 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
321 cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i'
322 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u'
324 = let tag1 = tagReg r1
327 if tag1 _LT_ tag2 then LT_ else GT_
329 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
330 tagReg (MappedReg _) = ILIT(2)
331 tagReg (MemoryReg _ _) = ILIT(3)
332 tagReg (UnmappedReg _ _) = ILIT(4)
334 cmp_i :: Int -> Int -> TAG_
335 cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_
337 cmp_ihash :: FAST_INT -> FAST_INT -> TAG_
338 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_
340 instance Ord3 Reg where
343 instance Eq Reg where
344 a == b = case (a `cmp` b) of { EQ_ -> True; _ -> False }
345 a /= b = case (a `cmp` b) of { EQ_ -> False; _ -> True }
347 instance Ord Reg where
348 a <= b = case (a `cmp` b) of { LT_ -> True; EQ_ -> True; GT__ -> False }
349 a < b = case (a `cmp` b) of { LT_ -> True; EQ_ -> False; GT__ -> False }
350 a >= b = case (a `cmp` b) of { LT_ -> False; EQ_ -> True; GT__ -> True }
351 a > b = case (a `cmp` b) of { LT_ -> False; EQ_ -> False; GT__ -> True }
352 _tagCmp a b = case (a `cmp` b) of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT }
354 instance Uniquable Reg where
355 uniqueOf (UnmappedReg u _) = u
356 uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i)
357 uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i)
358 uniqueOf (MemoryReg i _) = mkPseudoUnique3 i
364 realReg :: RegNo -> Reg
366 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
368 extractMappedRegNos :: [Reg] -> [RegNo]
370 extractMappedRegNos regs
373 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
374 ex _ acc = acc -- leave it out
377 ** Machine-specific Reg stuff: **
379 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
380 point registers. The mapping of STG registers to alpha machine registers
381 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
383 #if alpha_TARGET_ARCH
387 v0, f0, ra, pv, gp, sp, zeroh :: Reg
389 f0 = realReg (fReg 0)
390 ra = FixedReg ILIT(26)
392 gp = FixedReg ILIT(29)
393 sp = FixedReg ILIT(30)
394 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
396 t9, t10, t11, t12 :: Reg
404 Intel x86 architecture:
405 - All registers except 7 (esp) are available for use.
406 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
407 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
408 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
409 - Registers 8-15 hold extended floating point values.
413 gReg,fReg :: Int -> Int
417 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
418 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
419 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
420 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
421 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
422 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
423 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
424 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
425 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
426 st0 = realReg (fReg 0)
427 st1 = realReg (fReg 1)
428 st2 = realReg (fReg 2)
429 st3 = realReg (fReg 3)
430 st4 = realReg (fReg 4)
431 st5 = realReg (fReg 5)
432 st6 = realReg (fReg 6)
433 st7 = realReg (fReg 7)
438 The SPARC has 64 registers of interest; 32 integer registers and 32
439 floating point registers. The mapping of STG registers to SPARC
440 machine registers is defined in StgRegs.h. We are, of course,
441 prepared for any eventuality.
444 #if sparc_TARGET_ARCH
446 gReg,lReg,iReg,oReg,fReg :: Int -> Int
454 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
455 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
457 g0, fp, sp, o0, f0 :: Reg
458 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
459 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
460 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
461 o0 = realReg (oReg 0)
462 f0 = realReg (fReg 0)
467 Redefine the literals used for machine-registers with non-numeric
468 names in the header files. Gag me with a spoon, eh?
470 #if alpha_TARGET_ARCH
522 #if sparc_TARGET_ARCH
591 baseRegOffset :: MagicId -> Int
593 baseRegOffset StkOReg = OFFSET_StkO
594 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
595 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
596 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
597 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
598 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
599 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
600 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
601 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
602 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
603 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
604 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
605 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
606 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
607 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
608 baseRegOffset TagReg = OFFSET_Tag
609 baseRegOffset RetReg = OFFSET_Ret
610 baseRegOffset SpA = OFFSET_SpA
611 baseRegOffset SuA = OFFSET_SuA
612 baseRegOffset SpB = OFFSET_SpB
613 baseRegOffset SuB = OFFSET_SuB
614 baseRegOffset Hp = OFFSET_Hp
615 baseRegOffset HpLim = OFFSET_HpLim
616 baseRegOffset LivenessReg = OFFSET_Liveness
618 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
619 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
620 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
621 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
622 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
627 callerSaves :: MagicId -> Bool
629 #ifdef CALLER_SAVES_Base
630 callerSaves BaseReg = True
632 #ifdef CALLER_SAVES_StkO
633 callerSaves StkOReg = True
635 #ifdef CALLER_SAVES_R1
636 callerSaves (VanillaReg _ ILIT(1)) = True
638 #ifdef CALLER_SAVES_R2
639 callerSaves (VanillaReg _ ILIT(2)) = True
641 #ifdef CALLER_SAVES_R3
642 callerSaves (VanillaReg _ ILIT(3)) = True
644 #ifdef CALLER_SAVES_R4
645 callerSaves (VanillaReg _ ILIT(4)) = True
647 #ifdef CALLER_SAVES_R5
648 callerSaves (VanillaReg _ ILIT(5)) = True
650 #ifdef CALLER_SAVES_R6
651 callerSaves (VanillaReg _ ILIT(6)) = True
653 #ifdef CALLER_SAVES_R7
654 callerSaves (VanillaReg _ ILIT(7)) = True
656 #ifdef CALLER_SAVES_R8
657 callerSaves (VanillaReg _ ILIT(8)) = True
659 #ifdef CALLER_SAVES_FltReg1
660 callerSaves (FloatReg ILIT(1)) = True
662 #ifdef CALLER_SAVES_FltReg2
663 callerSaves (FloatReg ILIT(2)) = True
665 #ifdef CALLER_SAVES_FltReg3
666 callerSaves (FloatReg ILIT(3)) = True
668 #ifdef CALLER_SAVES_FltReg4
669 callerSaves (FloatReg ILIT(4)) = True
671 #ifdef CALLER_SAVES_DblReg1
672 callerSaves (DoubleReg ILIT(1)) = True
674 #ifdef CALLER_SAVES_DblReg2
675 callerSaves (DoubleReg ILIT(2)) = True
677 #ifdef CALLER_SAVES_Tag
678 callerSaves TagReg = True
680 #ifdef CALLER_SAVES_Ret
681 callerSaves RetReg = True
683 #ifdef CALLER_SAVES_SpA
684 callerSaves SpA = True
686 #ifdef CALLER_SAVES_SuA
687 callerSaves SuA = True
689 #ifdef CALLER_SAVES_SpB
690 callerSaves SpB = True
692 #ifdef CALLER_SAVES_SuB
693 callerSaves SuB = True
695 #ifdef CALLER_SAVES_Hp
696 callerSaves Hp = True
698 #ifdef CALLER_SAVES_HpLim
699 callerSaves HpLim = True
701 #ifdef CALLER_SAVES_Liveness
702 callerSaves LivenessReg = True
704 #ifdef CALLER_SAVES_StdUpdRetVec
705 callerSaves StdUpdRetVecReg = True
707 #ifdef CALLER_SAVES_StkStub
708 callerSaves StkStubReg = True
710 callerSaves _ = False
714 magicIdRegMaybe :: MagicId -> Maybe Reg
717 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
720 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
723 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
726 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
729 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
732 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
735 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
738 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
741 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
744 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
747 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
750 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
753 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
756 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
759 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
762 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
765 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
768 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
771 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
774 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
777 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
780 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
783 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
786 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
789 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
791 #ifdef REG_StdUpdRetVec
792 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
795 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
797 magicIdRegMaybe _ = Nothing
800 %************************************************************************
802 \subsection{Free, reserved, call-clobbered, and argument registers}
804 %************************************************************************
806 @freeRegs@ is the list of registers we can use in register allocation.
807 @freeReg@ (below) says if a particular register is free.
809 With a per-instruction clobber list, we might be able to get some of
810 these back, but it's probably not worth the hassle.
812 @callClobberedRegs@ ... the obvious.
814 @argRegs@: assuming a call with N arguments, what registers will be
815 used to hold arguments? (NB: it doesn't know whether the arguments
816 are integer or floating-point...)
819 reservedRegs :: [RegNo]
821 #if alpha_TARGET_ARCH
822 = [NCG_Reserved_I1, NCG_Reserved_I2,
823 NCG_Reserved_F1, NCG_Reserved_F2]
826 = [{-certainly cannot afford any!-}]
828 #if sparc_TARGET_ARCH
829 = [NCG_Reserved_I1, NCG_Reserved_I2,
830 NCG_Reserved_F1, NCG_Reserved_F2,
831 NCG_Reserved_D1, NCG_Reserved_D2]
834 -------------------------------
837 = freeMappedRegs IF_ARCH_alpha( [0..63],
838 IF_ARCH_i386( [0..15],
839 IF_ARCH_sparc( [0..63],)))
841 -------------------------------
842 callClobberedRegs :: [Reg]
845 #if alpha_TARGET_ARCH
846 [0, 1, 2, 3, 4, 5, 6, 7, 8,
847 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
848 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
849 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
850 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
851 #endif {- alpha_TARGET_ARCH -}
854 #endif {- i386_TARGET_ARCH -}
855 #if sparc_TARGET_ARCH
857 [oReg i | i <- [0..5]] ++
858 [gReg i | i <- [1..7]] ++
859 [fReg i | i <- [0..31]] )
860 #endif {- sparc_TARGET_ARCH -}
862 -------------------------------
863 argRegs :: Int -> [Reg]
866 #if alpha_TARGET_ARCH
867 argRegs 1 = freeMappedRegs [16, fReg 16]
868 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
869 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
870 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
871 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
872 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
873 #endif {- alpha_TARGET_ARCH -}
875 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
876 #endif {- i386_TARGET_ARCH -}
877 #if sparc_TARGET_ARCH
878 argRegs 1 = freeMappedRegs (map oReg [0])
879 argRegs 2 = freeMappedRegs (map oReg [0,1])
880 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
881 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
882 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
883 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
884 #endif {- sparc_TARGET_ARCH -}
885 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
887 -------------------------------
889 #if alpha_TARGET_ARCH
890 allArgRegs :: [(Reg, Reg)]
892 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
893 #endif {- alpha_TARGET_ARCH -}
895 #if sparc_TARGET_ARCH
898 allArgRegs = map realReg [oReg i | i <- [0..5]]
899 #endif {- sparc_TARGET_ARCH -}
901 -------------------------------
902 freeMappedRegs :: [Int] -> [Reg]
908 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
912 freeReg :: FAST_INT -> FAST_BOOL
914 #if alpha_TARGET_ARCH
915 freeReg ILIT(26) = _FALSE_ -- return address (ra)
916 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
917 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
918 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
919 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
920 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
924 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
927 #if sparc_TARGET_ARCH
928 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
929 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
930 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
931 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
932 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
933 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
937 freeReg ILIT(REG_Base) = _FALSE_
940 freeReg ILIT(REG_StkO) = _FALSE_
943 freeReg ILIT(REG_R1) = _FALSE_
946 freeReg ILIT(REG_R2) = _FALSE_
949 freeReg ILIT(REG_R3) = _FALSE_
952 freeReg ILIT(REG_R4) = _FALSE_
955 freeReg ILIT(REG_R5) = _FALSE_
958 freeReg ILIT(REG_R6) = _FALSE_
961 freeReg ILIT(REG_R7) = _FALSE_
964 freeReg ILIT(REG_R8) = _FALSE_
967 freeReg ILIT(REG_Flt1) = _FALSE_
970 freeReg ILIT(REG_Flt2) = _FALSE_
973 freeReg ILIT(REG_Flt3) = _FALSE_
976 freeReg ILIT(REG_Flt4) = _FALSE_
979 freeReg ILIT(REG_Dbl1) = _FALSE_
982 freeReg ILIT(REG_Dbl2) = _FALSE_
985 freeReg ILIT(REG_Tag) = _FALSE_
988 freeReg ILIT(REG_Ret) = _FALSE_
991 freeReg ILIT(REG_SpA) = _FALSE_
994 freeReg ILIT(REG_SuA) = _FALSE_
997 freeReg ILIT(REG_SpB) = _FALSE_
1000 freeReg ILIT(REG_SuB) = _FALSE_
1003 freeReg ILIT(REG_Hp) = _FALSE_
1006 freeReg ILIT(REG_HpLim) = _FALSE_
1009 freeReg ILIT(REG_Liveness) = _FALSE_
1011 #ifdef REG_StdUpdRetVec
1012 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1015 freeReg ILIT(REG_StkStub) = _FALSE_
1019 -- we hang onto two double regs for dedicated
1020 -- use; this is not necessary on Alphas and
1021 -- may not be on other non-SPARCs.
1023 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1026 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1028 | otherwise = _TRUE_