1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 EABase(..), EAIndex(..),
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
54 #if x86_64_TARGET_ARCH
55 EABase(..), EAIndex(..), ripRel,
56 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 r8, r9, r10, r11, r12, r13, r14, r15,
59 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
60 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
62 addrModeRegs, allFPArgRegs,
66 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
67 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
69 #if powerpc_TARGET_ARCH
78 #include "HsVersions.h"
81 # define STOLEN_X86_REGS 4
82 -- HACK: go for the max
85 #include "../includes/MachRegs.h"
88 import MachOp ( MachRep(..) )
90 import CLabel ( CLabel, mkMainCapabilityLabel )
92 import Outputable ( Outputable(..), pprPanic, panic )
93 import qualified Outputable
98 #if powerpc_TARGET_ARCH
99 #if __GLASGOW_HASKELL__ >= 504
100 import Data.Word ( Word8, Word16, Word32 )
101 import Data.Int ( Int8, Int16, Int32 )
103 import Word ( Word8, Word16, Word32 )
104 import Int ( Int8, Int16, Int32 )
108 -- -----------------------------------------------------------------------------
113 | ImmInteger Integer -- Sigh.
114 | ImmCLbl CLabel -- AbstractC Label (with baggage)
115 | ImmLit Doc -- Simple string
116 | ImmIndex CLabel Int
119 | ImmConstantSum Imm Imm
120 | ImmConstantDiff Imm Imm
121 #if sparc_TARGET_ARCH
122 | LO Imm {- Possible restrictions... -}
125 #if powerpc_TARGET_ARCH
128 | HA Imm {- high halfword adjusted -}
130 strImmLit s = ImmLit (text s)
132 litToImm :: CmmLit -> Imm
133 litToImm (CmmInt i _) = ImmInteger i
134 litToImm (CmmFloat f F32) = ImmFloat f
135 litToImm (CmmFloat f F64) = ImmDouble f
136 litToImm (CmmLabel l) = ImmCLbl l
137 litToImm (CmmLabelOff l off) = ImmIndex l off
138 litToImm (CmmLabelDiffOff l1 l2 off)
140 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
143 -- -----------------------------------------------------------------------------
147 #if alpha_TARGET_ARCH
153 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
154 = AddrBaseIndex EABase EAIndex Displacement
157 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
158 data EAIndex = EAIndexNone | EAIndex Reg Int
159 type Displacement = Imm
162 #if sparc_TARGET_ARCH
167 #if powerpc_TARGET_ARCH
172 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
173 addrModeRegs :: AddrMode -> [Reg]
174 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
176 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
177 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
182 addrOffset :: AddrMode -> Int -> Maybe AddrMode
186 #if alpha_TARGET_ARCH
187 _ -> panic "MachMisc.addrOffset not defined for Alpha"
189 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
190 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
192 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
193 AddrBaseIndex r i (ImmInteger n)
194 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
196 AddrBaseIndex r i (ImmCLbl lbl)
197 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
199 AddrBaseIndex r i (ImmIndex lbl ix)
200 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
202 _ -> Nothing -- in theory, shouldn't happen
204 #if sparc_TARGET_ARCH
205 AddrRegImm r (ImmInt n)
206 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
207 | otherwise -> Nothing
210 AddrRegImm r (ImmInteger n)
211 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
212 | otherwise -> Nothing
213 where n2 = n + toInteger off
215 AddrRegReg r (RealReg 0)
216 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
217 | otherwise -> Nothing
221 #if powerpc_TARGET_ARCH
222 AddrRegImm r (ImmInt n)
223 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
224 | otherwise -> Nothing
227 AddrRegImm r (ImmInteger n)
228 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
229 | otherwise -> Nothing
230 where n2 = n + toInteger off
236 #if alpha_TARGET_ARCH
238 fits8Bits :: Integer -> Bool
239 fits8Bits i = i >= -256 && i < 256
243 #if sparc_TARGET_ARCH
245 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
246 fits13Bits :: Integral a => a -> Bool
247 fits13Bits x = x >= -4096 && x < 4096
251 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
252 ++show i++");\nprobably because of large constant data structures;" ++
253 "\nworkaround: use -fvia-C on this module.\n")
257 #if powerpc_TARGET_ARCH
258 fits16Bits :: Integral a => a -> Bool
259 fits16Bits x = x >= -32768 && x < 32768
261 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
263 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
265 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
266 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
267 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
268 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
269 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
270 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
272 narrowed = narrow rep signed
275 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
276 | otherwise = Nothing
278 | narrowed >= 0 && narrowed < 65536 = Just narrowed
279 | otherwise = Nothing
280 toI16 _ _ = Just narrowed
284 -- @spRel@ gives us a stack relative addressing mode for volatile
285 -- temporaries and for excess call arguments. @fpRel@, where
286 -- applicable, is the same but for the frame pointer.
288 spRel :: Int -- desired stack offset in words, positive or negative
292 #if defined(i386_TARGET_ARCH)
293 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
294 #elif defined(x86_64_TARGET_ARCH)
295 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
297 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
300 #if sparc_TARGET_ARCH
301 fpRel :: Int -> AddrMode
302 -- Duznae work for offsets greater than 13 bits; we just hope for
305 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
308 #if x86_64_TARGET_ARCH
309 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
312 -- -----------------------------------------------------------------------------
315 -- We map STG registers onto appropriate CmmExprs. Either they map
316 -- to real machine registers or stored as offsets from BaseReg. Given
317 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
318 -- register it is in, on this platform, or a StixExpr denoting the
319 -- address in the register table holding it. get_MagicId_addr always
320 -- produces the register table address for it.
322 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
323 get_GlobalReg_addr :: GlobalReg -> CmmExpr
324 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
326 get_GlobalReg_reg_or_addr mid
327 = case globalRegMaybe mid of
329 Nothing -> Right (get_GlobalReg_addr mid)
331 get_GlobalReg_addr BaseReg = regTableOffset 0
332 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
333 (globalRegRep mid) (baseRegOffset mid)
335 -- Calculate a literal representing an offset into the register table.
336 -- Used when we don't have an actual BaseReg to offset from.
338 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
340 get_Regtable_addr_from_offset rep offset
341 = case globalRegMaybe BaseReg of
342 Nothing -> regTableOffset offset
343 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
345 -- ---------------------------------------------------------------------------
348 -- RealRegs are machine regs which are available for allocation, in
349 -- the usual way. We know what class they are, because that's part of
350 -- the processor's architecture.
352 -- VirtualRegs are virtual registers. The register allocator will
353 -- eventually have to map them into RealRegs, or into spill slots.
354 -- VirtualRegs are allocated on the fly, usually to represent a single
355 -- value in the abstract assembly code (i.e. dynamic registers are
356 -- usually single assignment). With the new register allocator, the
357 -- single assignment restriction isn't necessary to get correct code,
358 -- although a better register allocation will result if single
359 -- assignment is used -- because the allocator maps a VirtualReg into
360 -- a single RealReg, even if the VirtualReg has multiple live ranges.
362 -- Virtual regs can be of either class, so that info is attached.
364 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
365 -- when supplied with the vreg for the lower-half of the quantity.
366 -- (NB. Not reversible).
367 getHiVRegFromLo (VirtualRegI u)
368 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
369 getHiVRegFromLo other
370 = pprPanic "getHiVRegFromLo" (ppr other)
381 = RealReg {-# UNPACK #-} !RegNo
382 | VirtualRegI {-# UNPACK #-} !Unique
383 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
384 | VirtualRegF {-# UNPACK #-} !Unique
385 | VirtualRegD {-# UNPACK #-} !Unique
388 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
389 -- in the register allocator.
390 instance Uniquable Reg where
391 getUnique (RealReg i) = mkUnique 'C' i
392 getUnique (VirtualRegI u) = u
393 getUnique (VirtualRegHi u) = u
394 getUnique (VirtualRegF u) = u
395 getUnique (VirtualRegD u) = u
397 mkVReg :: Unique -> MachRep -> Reg
400 #if sparc_TARGET_ARCH
406 other -> VirtualRegI u
408 isVirtualReg :: Reg -> Bool
409 isVirtualReg (RealReg _) = False
410 isVirtualReg (VirtualRegI _) = True
411 isVirtualReg (VirtualRegHi _) = True
412 isVirtualReg (VirtualRegF _) = True
413 isVirtualReg (VirtualRegD _) = True
415 isRealReg :: Reg -> Bool
416 isRealReg = not . isVirtualReg
418 instance Show Reg where
419 show (RealReg i) = showReg i
420 show (VirtualRegI u) = "%vI_" ++ show u
421 show (VirtualRegHi u) = "%vHi_" ++ show u
422 show (VirtualRegF u) = "%vF_" ++ show u
423 show (VirtualRegD u) = "%vD_" ++ show u
425 instance Outputable Reg where
426 ppr r = Outputable.text (show r)
429 -- -----------------------------------------------------------------------------
430 -- Machine-specific register stuff
432 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
433 -- point registers. The mapping of STG registers to alpha machine registers
434 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
436 #if alpha_TARGET_ARCH
440 v0, f0, ra, pv, gp, sp, zeroh :: Reg
442 f0 = realReg (fReg 0)
443 ra = FixedReg ILIT(26)
445 gp = FixedReg ILIT(29)
446 sp = FixedReg ILIT(30)
447 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
449 t9, t10, t11, t12 :: Reg
457 Intel x86 architecture:
458 - All registers except 7 (esp) are available for use.
459 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
460 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
461 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
462 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
463 fp registers, and 3-operand insns for them, and we translate this into
464 real stack-based x86 fp code after register allocation.
466 The fp registers are all Double registers; we don't have any RcFloat class
467 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
473 fake0, fake1, fake2, fake3, fake4, fake5,
474 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
490 -- On x86, we might want to have an 8-bit RegClass, which would
491 -- contain just regs 1-4 (the others don't have 8-bit versions).
492 -- However, we can get away without this at the moment because the
493 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
494 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
495 regClass (VirtualRegI u) = RcInteger
496 regClass (VirtualRegHi u) = RcInteger
497 regClass (VirtualRegD u) = RcDouble
498 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
499 (ppr (VirtualRegF u))
502 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
503 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
505 showReg :: RegNo -> String
507 = if n >= 0 && n < 14
509 else "%unknown_x86_real_reg_" ++ show n
514 AMD x86_64 architecture:
515 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
516 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
517 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
521 #if x86_64_TARGET_ARCH
523 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
524 r8, r9, r10, r11, r12, r13, r14, r15,
525 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
526 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
561 -- so we can re-use some x86 code:
571 xmm n = RealReg (16+n)
573 -- On x86, we might want to have an 8-bit RegClass, which would
574 -- contain just regs 1-4 (the others don't have 8-bit versions).
575 -- However, we can get away without this at the moment because the
576 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
577 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
578 regClass (VirtualRegI u) = RcInteger
579 regClass (VirtualRegHi u) = RcInteger
580 regClass (VirtualRegD u) = RcDouble
581 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
582 (ppr (VirtualRegF u))
585 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
587 showReg :: RegNo -> String
589 | n >= 16 = "%xmm" ++ show (n-16)
590 | n >= 8 = "%r" ++ show n
591 | otherwise = regNames !! n
596 The SPARC has 64 registers of interest; 32 integer registers and 32
597 floating point registers. The mapping of STG registers to SPARC
598 machine registers is defined in StgRegs.h. We are, of course,
599 prepared for any eventuality.
601 The whole fp-register pairing thing on sparcs is a huge nuisance. See
602 fptools/ghc/includes/MachRegs.h for a description of what's going on
606 #if sparc_TARGET_ARCH
608 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
615 nCG_FirstFloatReg :: RegNo
616 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
618 regClass (VirtualRegI u) = RcInteger
619 regClass (VirtualRegF u) = RcFloat
620 regClass (VirtualRegD u) = RcDouble
621 regClass (RealReg i) | i < 32 = RcInteger
622 | i < nCG_FirstFloatReg = RcDouble
623 | otherwise = RcFloat
625 showReg :: RegNo -> String
627 | n >= 0 && n < 8 = "%g" ++ show n
628 | n >= 8 && n < 16 = "%o" ++ show (n-8)
629 | n >= 16 && n < 24 = "%l" ++ show (n-16)
630 | n >= 24 && n < 32 = "%i" ++ show (n-24)
631 | n >= 32 && n < 64 = "%f" ++ show (n-32)
632 | otherwise = "%unknown_sparc_real_reg_" ++ show n
634 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
636 f6 = RealReg (fReg 6)
637 f8 = RealReg (fReg 8)
638 f22 = RealReg (fReg 22)
639 f26 = RealReg (fReg 26)
640 f27 = RealReg (fReg 27)
643 -- g0 is useful for codegen; is always zero, and writes to it vanish.
644 g0 = RealReg (gReg 0)
645 g1 = RealReg (gReg 1)
646 g2 = RealReg (gReg 2)
648 -- FP, SP, int and float return (from C) regs.
649 fp = RealReg (iReg 6)
650 sp = RealReg (oReg 6)
651 o0 = RealReg (oReg 0)
652 o1 = RealReg (oReg 1)
653 f0 = RealReg (fReg 0)
654 f1 = RealReg (fReg 1)
659 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
663 #if powerpc_TARGET_ARCH
667 regClass (VirtualRegI u) = RcInteger
668 regClass (VirtualRegHi u) = RcInteger
669 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
670 (ppr (VirtualRegF u))
671 regClass (VirtualRegD u) = RcDouble
672 regClass (RealReg i) | i < 32 = RcInteger
673 | otherwise = RcDouble
675 showReg :: RegNo -> String
677 | n >= 0 && n <= 31 = "%r" ++ show n
678 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
679 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
686 f1 = RealReg $ fReg 1
687 f20 = RealReg $ fReg 20
688 f21 = RealReg $ fReg 21
692 Redefine the literals used for machine-registers with non-numeric
693 names in the header files. Gag me with a spoon, eh?
696 #if alpha_TARGET_ARCH
747 #if x86_64_TARGET_ARCH
782 #if sparc_TARGET_ARCH
850 #if powerpc_TARGET_ARCH
884 #ifdef darwin_TARGET_OS
954 -- allMachRegs is the complete set of machine regs.
955 allMachRegNos :: [RegNo]
957 = IF_ARCH_alpha( [0..63],
958 IF_ARCH_i386( [0..13],
959 IF_ARCH_x86_64( [0..31],
960 IF_ARCH_sparc( ([0..31]
961 ++ [f0,f2 .. nCG_FirstFloatReg-1]
962 ++ [nCG_FirstFloatReg .. f31]),
963 IF_ARCH_powerpc([0..63],
966 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
967 -- i.e., these are the regs for which we are prepared to allow the
968 -- register allocator to attempt to map VRegs to.
969 allocatableRegs :: [RegNo]
971 = let isFree i = isFastTrue (freeReg i)
972 in filter isFree allMachRegNos
974 -- these are the regs which we cannot assume stay alive over a
976 callClobberedRegs :: [Reg]
979 #if alpha_TARGET_ARCH
980 [0, 1, 2, 3, 4, 5, 6, 7, 8,
981 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
982 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
983 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
984 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
985 #endif /* alpha_TARGET_ARCH */
987 -- caller-saves registers
988 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
989 #endif /* i386_TARGET_ARCH */
990 #if x86_64_TARGET_ARCH
991 -- caller-saves registers
992 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
993 -- all xmm regs are caller-saves
994 #endif /* x86_64_TARGET_ARCH */
995 #if sparc_TARGET_ARCH
998 [oReg i | i <- [0..5]] ++
999 [gReg i | i <- [1..7]] ++
1000 [fReg i | i <- [0..31]] )
1001 #endif /* sparc_TARGET_ARCH */
1002 #if powerpc_TARGET_ARCH
1003 #if darwin_TARGET_OS
1004 map RealReg (0:[2..12] ++ map fReg [0..13])
1005 #elif linux_TARGET_OS
1006 map RealReg (0:[2..13] ++ map fReg [0..13])
1008 #endif /* powerpc_TARGET_ARCH */
1011 -- argRegs is the set of regs which are read for an n-argument call to C.
1012 -- For archs which pass all args on the stack (x86), is empty.
1013 -- Sparc passes up to the first 6 args in regs.
1014 -- Dunno about Alpha.
1015 argRegs :: RegNo -> [Reg]
1017 #if i386_TARGET_ARCH
1018 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1021 #if x86_64_TARGET_ARCH
1022 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1025 #if alpha_TARGET_ARCH
1027 argRegs 1 = freeMappedRegs [16, fReg 16]
1028 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1029 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1030 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1031 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1032 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1033 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1034 #endif /* alpha_TARGET_ARCH */
1036 #if sparc_TARGET_ARCH
1038 argRegs 1 = map (RealReg . oReg) [0]
1039 argRegs 2 = map (RealReg . oReg) [0,1]
1040 argRegs 3 = map (RealReg . oReg) [0,1,2]
1041 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1042 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1043 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1044 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1045 #endif /* sparc_TARGET_ARCH */
1047 #if powerpc_TARGET_ARCH
1049 argRegs 1 = map RealReg [3]
1050 argRegs 2 = map RealReg [3,4]
1051 argRegs 3 = map RealReg [3..5]
1052 argRegs 4 = map RealReg [3..6]
1053 argRegs 5 = map RealReg [3..7]
1054 argRegs 6 = map RealReg [3..8]
1055 argRegs 7 = map RealReg [3..9]
1056 argRegs 8 = map RealReg [3..10]
1057 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1058 #endif /* powerpc_TARGET_ARCH */
1061 -- all of the arg regs ??
1062 #if alpha_TARGET_ARCH
1063 allArgRegs :: [(Reg, Reg)]
1064 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1065 #endif /* alpha_TARGET_ARCH */
1067 #if sparc_TARGET_ARCH
1069 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1070 #endif /* sparc_TARGET_ARCH */
1072 #if i386_TARGET_ARCH
1074 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1077 #if x86_64_TARGET_ARCH
1079 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1080 allFPArgRegs :: [Reg]
1081 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1084 #if powerpc_TARGET_ARCH
1086 allArgRegs = map RealReg [3..10]
1087 allFPArgRegs :: [Reg]
1088 #if darwin_TARGET_OS
1089 allFPArgRegs = map (RealReg . fReg) [1..13]
1090 #elif linux_TARGET_OS
1091 allFPArgRegs = map (RealReg . fReg) [1..8]
1093 #endif /* powerpc_TARGET_ARCH */
1097 freeReg :: RegNo -> FastBool
1099 #if alpha_TARGET_ARCH
1100 freeReg 26 = fastBool False -- return address (ra)
1101 freeReg 28 = fastBool False -- reserved for the assembler (at)
1102 freeReg 29 = fastBool False -- global pointer (gp)
1103 freeReg 30 = fastBool False -- stack pointer (sp)
1104 freeReg 31 = fastBool False -- always zero (zeroh)
1105 freeReg 63 = fastBool False -- always zero (f31)
1108 #if i386_TARGET_ARCH
1109 freeReg esp = fastBool False -- %esp is the C stack pointer
1112 #if x86_64_TARGET_ARCH
1113 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1116 #if sparc_TARGET_ARCH
1117 freeReg g0 = fastBool False -- %g0 is always 0.
1118 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1119 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1120 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1121 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1122 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1123 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1124 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1125 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1126 freeReg f1 = fastBool False
1129 #if powerpc_TARGET_ARCH
1130 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1131 freeReg 1 = fastBool False -- The Stack Pointer
1132 #if !darwin_TARGET_OS
1133 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1134 freeReg 2 = fastBool False
1139 freeReg REG_Base = fastBool False
1142 freeReg REG_R1 = fastBool False
1145 freeReg REG_R2 = fastBool False
1148 freeReg REG_R3 = fastBool False
1151 freeReg REG_R4 = fastBool False
1154 freeReg REG_R5 = fastBool False
1157 freeReg REG_R6 = fastBool False
1160 freeReg REG_R7 = fastBool False
1163 freeReg REG_R8 = fastBool False
1166 freeReg REG_F1 = fastBool False
1169 freeReg REG_F2 = fastBool False
1172 freeReg REG_F3 = fastBool False
1175 freeReg REG_F4 = fastBool False
1178 freeReg REG_D1 = fastBool False
1181 freeReg REG_D2 = fastBool False
1184 freeReg REG_Sp = fastBool False
1187 freeReg REG_Su = fastBool False
1190 freeReg REG_SpLim = fastBool False
1193 freeReg REG_Hp = fastBool False
1196 freeReg REG_HpLim = fastBool False
1198 freeReg n = fastBool True
1201 -- -----------------------------------------------------------------------------
1202 -- Information about global registers
1204 baseRegOffset :: GlobalReg -> Int
1206 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1207 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1208 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1209 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1210 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1211 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1212 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1213 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1214 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1215 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1216 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1217 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1218 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1219 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1220 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1221 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1222 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1223 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1224 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1225 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1226 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1227 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1228 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1229 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1230 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1231 baseRegOffset GCFun = oFFSET_stgGCFun
1233 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1234 baseRegOffset _ = panic "baseRegOffset:other"
1238 -- | Returns 'True' if this global register is stored in a caller-saves
1239 -- machine register.
1241 callerSaves :: GlobalReg -> Bool
1243 #ifdef CALLER_SAVES_Base
1244 callerSaves BaseReg = True
1246 #ifdef CALLER_SAVES_R1
1247 callerSaves (VanillaReg 1) = True
1249 #ifdef CALLER_SAVES_R2
1250 callerSaves (VanillaReg 2) = True
1252 #ifdef CALLER_SAVES_R3
1253 callerSaves (VanillaReg 3) = True
1255 #ifdef CALLER_SAVES_R4
1256 callerSaves (VanillaReg 4) = True
1258 #ifdef CALLER_SAVES_R5
1259 callerSaves (VanillaReg 5) = True
1261 #ifdef CALLER_SAVES_R6
1262 callerSaves (VanillaReg 6) = True
1264 #ifdef CALLER_SAVES_R7
1265 callerSaves (VanillaReg 7) = True
1267 #ifdef CALLER_SAVES_R8
1268 callerSaves (VanillaReg 8) = True
1270 #ifdef CALLER_SAVES_F1
1271 callerSaves (FloatReg 1) = True
1273 #ifdef CALLER_SAVES_F2
1274 callerSaves (FloatReg 2) = True
1276 #ifdef CALLER_SAVES_F3
1277 callerSaves (FloatReg 3) = True
1279 #ifdef CALLER_SAVES_F4
1280 callerSaves (FloatReg 4) = True
1282 #ifdef CALLER_SAVES_D1
1283 callerSaves (DoubleReg 1) = True
1285 #ifdef CALLER_SAVES_D2
1286 callerSaves (DoubleReg 2) = True
1288 #ifdef CALLER_SAVES_L1
1289 callerSaves (LongReg 1) = True
1291 #ifdef CALLER_SAVES_Sp
1292 callerSaves Sp = True
1294 #ifdef CALLER_SAVES_SpLim
1295 callerSaves SpLim = True
1297 #ifdef CALLER_SAVES_Hp
1298 callerSaves Hp = True
1300 #ifdef CALLER_SAVES_HpLim
1301 callerSaves HpLim = True
1303 #ifdef CALLER_SAVES_CurrentTSO
1304 callerSaves CurrentTSO = True
1306 #ifdef CALLER_SAVES_CurrentNursery
1307 callerSaves CurrentNursery = True
1309 callerSaves _ = False
1312 -- | Returns 'Nothing' if this global register is not stored
1313 -- in a real machine register, otherwise returns @'Just' reg@, where
1314 -- reg is the machine register it is stored in.
1316 globalRegMaybe :: GlobalReg -> Maybe Reg
1319 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1322 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1325 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1328 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1331 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1334 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1337 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1340 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1343 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1346 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1349 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1352 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1355 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1358 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1361 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1364 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1367 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1370 globalRegMaybe Sp = Just (RealReg REG_Sp)
1373 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1376 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1379 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1382 globalRegMaybe Hp = Just (RealReg REG_Hp)
1385 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1387 #ifdef REG_CurrentTSO
1388 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1390 #ifdef REG_CurrentNursery
1391 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1393 globalRegMaybe _ = Nothing