2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
17 RegClass(..), regClass,
18 Reg(..), isRealReg, isVirtualReg,
19 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
41 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
44 , eax, ebx, ecx, edx, esi, esp
45 , fake0, fake1, fake2, fake3, fake4, fake5
49 , fpRel, gReg, iReg, lReg, oReg, largeOffsetError
50 , fp, sp, g0, g1, g2, o0, f0, f6, f8, f26, f27
55 #include "HsVersions.h"
57 import AbsCSyn ( MagicId(..) )
58 import AbsCUtils ( magicIdPrimRep )
59 import CLabel ( CLabel, mkMainRegTableLabel )
60 import PrimOp ( PrimOp(..) )
61 import PrimRep ( PrimRep(..), isFloatingRep )
62 import Stix ( StixTree(..), StixReg(..),
63 getUniqueNat, returnNat, thenNat, NatM )
64 import Unique ( mkPseudoUnique2, Uniquable(..), Unique )
69 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
74 | ImmInteger Integer -- Sigh.
75 | ImmCLbl CLabel -- AbstractC Label (with baggage)
76 | ImmLab Bool SDoc -- Simple string label (underscore-able)
77 -- Bool==True ==> in a different DLL
78 | ImmLit SDoc -- Simple string
83 | LO Imm -- Possible restrictions...
86 strImmLit s = ImmLit (text s)
89 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
100 = AddrBaseIndex Base Index Displacement
103 type Base = Maybe Reg
104 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
105 type Displacement = Imm
108 #if sparc_TARGET_ARCH
113 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
117 #if alpha_TARGET_ARCH
118 _ -> panic "MachMisc.addrOffset not defined for Alpha"
121 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
122 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
123 AddrBaseIndex r i (ImmInteger n)
124 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
127 #if sparc_TARGET_ARCH
128 AddrRegImm r (ImmInt n)
129 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
130 | otherwise -> Nothing
133 AddrRegImm r (ImmInteger n)
134 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
135 | otherwise -> Nothing
136 where n2 = n + toInteger off
138 AddrRegReg r (RealReg 0)
139 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
140 | otherwise -> Nothing
147 #if alpha_TARGET_ARCH
149 fits8Bits :: Integer -> Bool
150 fits8Bits i = i >= -256 && i < 256
154 #if sparc_TARGET_ARCH
156 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
157 fits13Bits :: Integral a => a -> Bool
158 fits13Bits x = x >= -4096 && x < 4096
162 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
163 ++show i++");\nprobably because of large constant data structures;" ++
164 "\nworkaround: use -fvia-C on this module.\n")
169 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
171 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
172 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
173 The rest are either in real machine registers or stored as offsets
177 data RegLoc = Save StixTree | Always StixTree
180 Trees for register save locations:
182 saveLoc :: MagicId -> StixTree
184 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
188 stgReg :: MagicId -> RegLoc
191 = case (magicIdRegMaybe x) of
192 Just _ -> Save nonReg
193 Nothing -> Always nonReg
195 offset = baseRegOffset x
197 baseLoc = case (magicIdRegMaybe BaseReg) of
198 Just _ -> StReg (StixMagicId BaseReg)
199 Nothing -> StCLbl mkMainRegTableLabel
202 BaseReg -> StCLbl mkMainRegTableLabel
204 _ -> StInd (magicIdPrimRep x)
205 (StPrim IntAddOp [baseLoc,
206 StInt (toInteger (offset*BYTES_PER_WORD))])
209 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
211 @spRel@ gives us a stack relative addressing mode for volatile
212 temporaries and for excess call arguments. @fpRel@, where
213 applicable, is the same but for the frame pointer.
216 spRel :: Int -- desired stack offset in words, positive or negative
221 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
223 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
226 #if sparc_TARGET_ARCH
227 fpRel :: Int -> MachRegsAddr
228 -- Duznae work for offsets greater than 13 bits; we just hope for
231 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
235 %************************************************************************
237 \subsection[Reg]{Real registers}
239 %************************************************************************
241 RealRegs are machine regs which are available for allocation, in the
242 usual way. We know what class they are, because that's part of the
243 processor's architecture.
245 VirtualRegs are virtual registers. The register allocator will
246 eventually have to map them into RealRegs, or into spill slots.
247 VirtualRegs are allocated on the fly, usually to represent a single
248 value in the abstract assembly code (i.e. dynamic registers are
249 usually single assignment). With the new register allocator, the
250 single assignment restriction isn't necessary to get correct code,
251 although a better register allocation will result if single assignment
252 is used -- because the allocator maps a VirtualReg into a single
253 RealReg, even if the VirtualReg has multiple live ranges.
255 Virtual regs can be of either class, so that info is attached.
271 unRealReg (RealReg i) = i
272 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
274 mkVReg :: Unique -> PrimRep -> Reg
276 #if sparc_TARGET_ARCH
278 FloatRep -> VirtualRegF u
279 DoubleRep -> VirtualRegD u
280 other -> VirtualRegI u
282 = if isFloatingRep pk then VirtualRegD u else VirtualRegI u
285 isVirtualReg (RealReg _) = False
286 isVirtualReg (VirtualRegI _) = True
287 isVirtualReg (VirtualRegF _) = True
288 isVirtualReg (VirtualRegD _) = True
289 isRealReg = not . isVirtualReg
291 getNewRegNCG :: PrimRep -> NatM Reg
293 = getUniqueNat `thenNat` \ u -> returnNat (mkVReg u pk)
295 instance Eq Reg where
296 (==) (RealReg i1) (RealReg i2) = i1 == i2
297 (==) (VirtualRegI u1) (VirtualRegI u2) = u1 == u2
298 (==) (VirtualRegF u1) (VirtualRegF u2) = u1 == u2
299 (==) (VirtualRegD u1) (VirtualRegD u2) = u1 == u2
300 (==) reg1 reg2 = False
302 instance Ord Reg where
303 compare (RealReg i1) (RealReg i2) = compare i1 i2
304 compare (RealReg _) (VirtualRegI _) = LT
305 compare (RealReg _) (VirtualRegF _) = LT
306 compare (RealReg _) (VirtualRegD _) = LT
308 compare (VirtualRegI _) (RealReg _) = GT
309 compare (VirtualRegI u1) (VirtualRegI u2) = compare u1 u2
310 compare (VirtualRegI _) (VirtualRegF _) = LT
311 compare (VirtualRegI _) (VirtualRegD _) = LT
313 compare (VirtualRegF _) (RealReg _) = GT
314 compare (VirtualRegF _) (VirtualRegI _) = GT
315 compare (VirtualRegF u1) (VirtualRegF u2) = compare u1 u2
316 compare (VirtualRegF _) (VirtualRegD _) = LT
318 compare (VirtualRegD _) (RealReg _) = GT
319 compare (VirtualRegD _) (VirtualRegI _) = GT
320 compare (VirtualRegD _) (VirtualRegF _) = GT
321 compare (VirtualRegD u1) (VirtualRegD u2) = compare u1 u2
324 instance Show Reg where
325 showsPrec _ (RealReg i) = showString (showReg i)
326 showsPrec _ (VirtualRegI u) = showString "%vI_" . shows u
327 showsPrec _ (VirtualRegF u) = showString "%vF_" . shows u
328 showsPrec _ (VirtualRegD u) = showString "%vD_" . shows u
330 instance Outputable Reg where
331 ppr r = text (show r)
333 instance Uniquable Reg where
334 getUnique (RealReg i) = mkPseudoUnique2 i
335 getUnique (VirtualRegI u) = u
336 getUnique (VirtualRegF u) = u
337 getUnique (VirtualRegD u) = u
340 ** Machine-specific Reg stuff: **
342 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
343 point registers. The mapping of STG registers to alpha machine registers
344 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
346 #if alpha_TARGET_ARCH
350 v0, f0, ra, pv, gp, sp, zeroh :: Reg
352 f0 = realReg (fReg 0)
353 ra = FixedReg ILIT(26)
355 gp = FixedReg ILIT(29)
356 sp = FixedReg ILIT(30)
357 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
359 t9, t10, t11, t12 :: Reg
367 Intel x86 architecture:
368 - All registers except 7 (esp) are available for use.
369 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
370 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
371 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
372 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
373 fp registers, and 3-operand insns for them, and we translate this into
374 real stack-based x86 fp code after register allocation.
376 The fp registers are all Double registers; we don't have any RcFloat class
377 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
383 fake0, fake1, fake2, fake3, fake4, fake5,
384 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
400 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
401 regClass (VirtualRegI u) = RcInteger
402 regClass (VirtualRegD u) = RcDouble
403 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
404 (ppr (VirtualRegF u))
407 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
408 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
410 showReg :: Int -> String
412 = if n >= 0 && n < 14
414 else "%unknown_x86_real_reg_" ++ show n
419 The SPARC has 64 registers of interest; 32 integer registers and 32
420 floating point registers. The mapping of STG registers to SPARC
421 machine registers is defined in StgRegs.h. We are, of course,
422 prepared for any eventuality.
424 The whole fp-register pairing thing on sparcs is a huge nuisance. See
425 fptools/ghc/includes/MachRegs.h for a description of what's going on
429 #if sparc_TARGET_ARCH
431 gReg,lReg,iReg,oReg,fReg :: Int -> Int
438 nCG_FirstFloatReg :: Int
439 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
441 regClass (VirtualRegI u) = RcInteger
442 regClass (VirtualRegF u) = RcFloat
443 regClass (VirtualRegD u) = RcDouble
444 regClass (RealReg i) | i < 32 = RcInteger
445 | i < nCG_FirstFloatReg = RcDouble
446 | otherwise = RcFloat
448 showReg :: Int -> String
450 | n >= 0 && n < 8 = "%g" ++ show n
451 | n >= 8 && n < 16 = "%o" ++ show (n-8)
452 | n >= 16 && n < 24 = "%l" ++ show (n-16)
453 | n >= 24 && n < 32 = "%i" ++ show (n-24)
454 | n >= 32 && n < 64 = "%f" ++ show (n-32)
455 | otherwise = "%unknown_sparc_real_reg_" ++ show n
457 g0, g1, g2, fp, sp, o0, f0, f1, f6, f8, f22, f26, f27 :: Reg
459 f6 = RealReg (fReg 6)
460 f8 = RealReg (fReg 8)
461 f22 = RealReg (fReg 22)
462 f26 = RealReg (fReg 26)
463 f27 = RealReg (fReg 27)
466 -- g0 is useful for codegen; is always zero, and writes to it vanish.
467 g0 = RealReg (gReg 0)
468 g1 = RealReg (gReg 1)
469 g2 = RealReg (gReg 2)
471 -- FP, SP, int and float return (from C) regs.
472 fp = RealReg (iReg 6)
473 sp = RealReg (oReg 6)
474 o0 = RealReg (oReg 0)
475 f0 = RealReg (fReg 0)
476 f1 = RealReg (fReg 1)
481 Redefine the literals used for machine-registers with non-numeric
482 names in the header files. Gag me with a spoon, eh?
484 #if alpha_TARGET_ARCH
534 #if sparc_TARGET_ARCH
605 baseRegOffset :: MagicId -> Int
607 baseRegOffset (VanillaReg _ 1#) = OFFSET_R1
608 baseRegOffset (VanillaReg _ 2#) = OFFSET_R2
609 baseRegOffset (VanillaReg _ 3#) = OFFSET_R3
610 baseRegOffset (VanillaReg _ 4#) = OFFSET_R4
611 baseRegOffset (VanillaReg _ 5#) = OFFSET_R5
612 baseRegOffset (VanillaReg _ 6#) = OFFSET_R6
613 baseRegOffset (VanillaReg _ 7#) = OFFSET_R7
614 baseRegOffset (VanillaReg _ 8#) = OFFSET_R8
615 baseRegOffset (VanillaReg _ 9#) = OFFSET_R9
616 baseRegOffset (VanillaReg _ 10#) = OFFSET_R10
617 baseRegOffset (FloatReg 1#) = OFFSET_F1
618 baseRegOffset (FloatReg 2#) = OFFSET_F2
619 baseRegOffset (FloatReg 3#) = OFFSET_F3
620 baseRegOffset (FloatReg 4#) = OFFSET_F4
621 baseRegOffset (DoubleReg 1#) = OFFSET_D1
622 baseRegOffset (DoubleReg 2#) = OFFSET_D2
623 baseRegOffset Sp = OFFSET_Sp
624 baseRegOffset Su = OFFSET_Su
625 baseRegOffset SpLim = OFFSET_SpLim
627 baseRegOffset (LongReg _ 1#) = OFFSET_L1
629 baseRegOffset Hp = OFFSET_Hp
630 baseRegOffset HpLim = OFFSET_HpLim
631 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
632 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
634 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
635 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
636 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
641 callerSaves :: MagicId -> Bool
643 #ifdef CALLER_SAVES_Base
644 callerSaves BaseReg = True
646 #ifdef CALLER_SAVES_R1
647 callerSaves (VanillaReg _ ILIT(1)) = True
649 #ifdef CALLER_SAVES_R2
650 callerSaves (VanillaReg _ ILIT(2)) = True
652 #ifdef CALLER_SAVES_R3
653 callerSaves (VanillaReg _ ILIT(3)) = True
655 #ifdef CALLER_SAVES_R4
656 callerSaves (VanillaReg _ ILIT(4)) = True
658 #ifdef CALLER_SAVES_R5
659 callerSaves (VanillaReg _ ILIT(5)) = True
661 #ifdef CALLER_SAVES_R6
662 callerSaves (VanillaReg _ ILIT(6)) = True
664 #ifdef CALLER_SAVES_R7
665 callerSaves (VanillaReg _ ILIT(7)) = True
667 #ifdef CALLER_SAVES_R8
668 callerSaves (VanillaReg _ ILIT(8)) = True
670 #ifdef CALLER_SAVES_F1
671 callerSaves (FloatReg ILIT(1)) = True
673 #ifdef CALLER_SAVES_F2
674 callerSaves (FloatReg ILIT(2)) = True
676 #ifdef CALLER_SAVES_F3
677 callerSaves (FloatReg ILIT(3)) = True
679 #ifdef CALLER_SAVES_F4
680 callerSaves (FloatReg ILIT(4)) = True
682 #ifdef CALLER_SAVES_D1
683 callerSaves (DoubleReg ILIT(1)) = True
685 #ifdef CALLER_SAVES_D2
686 callerSaves (DoubleReg ILIT(2)) = True
688 #ifdef CALLER_SAVES_L1
689 callerSaves (LongReg _ ILIT(1)) = True
691 #ifdef CALLER_SAVES_Sp
692 callerSaves Sp = True
694 #ifdef CALLER_SAVES_Su
695 callerSaves Su = True
697 #ifdef CALLER_SAVES_SpLim
698 callerSaves SpLim = True
700 #ifdef CALLER_SAVES_Hp
701 callerSaves Hp = True
703 #ifdef CALLER_SAVES_HpLim
704 callerSaves HpLim = True
706 #ifdef CALLER_SAVES_CurrentTSO
707 callerSaves CurrentTSO = True
709 #ifdef CALLER_SAVES_CurrentNursery
710 callerSaves CurrentNursery = True
712 callerSaves _ = False
716 magicIdRegMaybe :: MagicId -> Maybe Reg
719 magicIdRegMaybe BaseReg = Just (RealReg REG_Base)
722 magicIdRegMaybe (VanillaReg _ 1#) = Just (RealReg REG_R1)
725 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (RealReg REG_R2)
728 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (RealReg REG_R3)
731 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (RealReg REG_R4)
734 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (RealReg REG_R5)
737 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (RealReg REG_R6)
740 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (RealReg REG_R7)
743 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (RealReg REG_R8)
746 magicIdRegMaybe (VanillaReg _ ILIT(9)) = Just (RealReg REG_R9)
749 magicIdRegMaybe (VanillaReg _ ILIT(10)) = Just (RealReg REG_R10)
752 magicIdRegMaybe (FloatReg ILIT(1)) = Just (RealReg REG_F1)
755 magicIdRegMaybe (FloatReg ILIT(2)) = Just (RealReg REG_F2)
758 magicIdRegMaybe (FloatReg ILIT(3)) = Just (RealReg REG_F3)
761 magicIdRegMaybe (FloatReg ILIT(4)) = Just (RealReg REG_F4)
764 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (RealReg REG_D1)
767 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (RealReg REG_D2)
770 magicIdRegMaybe Sp = Just (RealReg REG_Sp)
773 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (RealReg REG_Lng1)
776 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (RealReg REG_Lng2)
779 magicIdRegMaybe Su = Just (RealReg REG_Su)
782 magicIdRegMaybe SpLim = Just (RealReg REG_SpLim)
785 magicIdRegMaybe Hp = Just (RealReg REG_Hp)
788 magicIdRegMaybe HpLim = Just (RealReg REG_HpLim)
790 #ifdef REG_CurrentTSO
791 magicIdRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
793 #ifdef REG_CurrentNursery
794 magicIdRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
796 magicIdRegMaybe _ = Nothing
800 -------------------------------
801 -- allMachRegs is the complete set of machine regs.
802 allMachRegNos :: [Int]
804 = IF_ARCH_alpha( [0..63],
805 IF_ARCH_i386( [0..13],
806 IF_ARCH_sparc( ([0..31]
807 ++ [f0,f2 .. nCG_FirstFloatReg-1]
808 ++ [nCG_FirstFloatReg .. f31]),
810 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
811 -- i.e., these are the regs for which we are prepared to allow the
812 -- register allocator to attempt to map VRegs to.
813 allocatableRegs :: [Reg]
815 = let isFree i = _IS_TRUE_(freeReg i)
816 in map RealReg (filter isFree allMachRegNos)
818 -------------------------------
819 -- these are the regs which we cannot assume stay alive over a
821 callClobberedRegs :: [Reg]
824 #if alpha_TARGET_ARCH
825 [0, 1, 2, 3, 4, 5, 6, 7, 8,
826 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
827 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
828 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
829 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
830 #endif {- alpha_TARGET_ARCH -}
832 -- caller-saves registers
833 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
834 #endif {- i386_TARGET_ARCH -}
835 #if sparc_TARGET_ARCH
838 [oReg i | i <- [0..5]] ++
839 [gReg i | i <- [1..7]] ++
840 [fReg i | i <- [0..31]] )
841 #endif {- sparc_TARGET_ARCH -}
843 -------------------------------
844 -- argRegs is the set of regs which are read for an n-argument call to C.
845 -- For archs which pass all args on the stack (x86), is empty.
846 -- Sparc passes up to the first 6 args in regs.
847 -- Dunno about Alpha.
848 argRegs :: Int -> [Reg]
851 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
854 #if alpha_TARGET_ARCH
856 argRegs 1 = freeMappedRegs [16, fReg 16]
857 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
858 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
859 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
860 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
861 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
862 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
863 #endif {- alpha_TARGET_ARCH -}
865 #if sparc_TARGET_ARCH
867 argRegs 1 = map (RealReg . oReg) [0]
868 argRegs 2 = map (RealReg . oReg) [0,1]
869 argRegs 3 = map (RealReg . oReg) [0,1,2]
870 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
871 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
872 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
873 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
874 #endif {- sparc_TARGET_ARCH -}
876 -------------------------------
877 -- all of the arg regs ??
878 #if alpha_TARGET_ARCH
879 allArgRegs :: [(Reg, Reg)]
880 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
881 #endif {- alpha_TARGET_ARCH -}
883 #if sparc_TARGET_ARCH
885 allArgRegs = map RealReg [oReg i | i <- [0..5]]
886 #endif {- sparc_TARGET_ARCH -}
890 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
895 freeReg :: Int -> FastBool
897 #if alpha_TARGET_ARCH
898 freeReg 26 = fastBool False -- return address (ra)
899 freeReg 28 = fastBool False -- reserved for the assembler (at)
900 freeReg 29 = fastBool False -- global pointer (gp)
901 freeReg 30 = fastBool False -- stack pointer (sp)
902 freeReg 31 = fastBool False -- always zero (zeroh)
903 freeReg 63 = fastBool False -- always zero (f31)
907 freeReg esp = fastBool False -- %esp is the C stack pointer
910 #if sparc_TARGET_ARCH
911 freeReg g0 = fastBool False -- %g0 is always 0.
912 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
913 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
914 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
915 freeReg i6 = fastBool False -- %i6 is our frame pointer.
916 freeReg o6 = fastBool False -- %o6 is our stack pointer.
917 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
918 freeReg f1 = fastBool False
922 freeReg REG_Base = fastBool False
925 freeReg REG_R1 = fastBool False
928 freeReg REG_R2 = fastBool False
931 freeReg REG_R3 = fastBool False
934 freeReg REG_R4 = fastBool False
937 freeReg REG_R5 = fastBool False
940 freeReg REG_R6 = fastBool False
943 freeReg REG_R7 = fastBool False
946 freeReg REG_R8 = fastBool False
949 freeReg REG_F1 = fastBool False
952 freeReg REG_F2 = fastBool False
955 freeReg REG_F3 = fastBool False
958 freeReg REG_F4 = fastBool False
961 freeReg REG_D1 = fastBool False
964 freeReg REG_D2 = fastBool False
967 freeReg REG_Sp = fastBool False
970 freeReg REG_Su = fastBool False
973 freeReg REG_SpLim = fastBool False
976 freeReg REG_Hp = fastBool False
979 freeReg REG_HpLim = fastBool False
981 freeReg n = fastBool True