2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
45 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
48 , eax, ebx, ecx, edx, esi, esp
49 , fake0, fake1, fake2, fake3, fake4, fake5
54 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
60 #include "HsVersions.h"
62 import AbsCSyn ( MagicId(..) )
63 import AbsCUtils ( magicIdPrimRep )
64 import CLabel ( CLabel )
65 import PrimOp ( PrimOp(..) )
66 import PrimRep ( PrimRep(..) )
67 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
68 getUniqueNat, returnNat, thenNat, NatM )
69 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
72 --import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM )
76 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
81 | ImmInteger Integer -- Sigh.
82 | ImmCLbl CLabel -- AbstractC Label (with baggage)
83 | ImmLab SDoc -- Simple string label (underscore-able)
84 | ImmLit SDoc -- Simple string
88 | LO Imm -- Possible restrictions...
91 strImmLit s = ImmLit (text s)
94 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
105 = AddrBaseIndex Base Index Displacement
108 type Base = Maybe Reg
109 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
110 type Displacement = Imm
113 #if sparc_TARGET_ARCH
118 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
122 #if alpha_TARGET_ARCH
123 _ -> panic "MachMisc.addrOffset not defined for Alpha"
126 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
127 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
128 AddrBaseIndex r i (ImmInteger n)
129 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
132 #if sparc_TARGET_ARCH
133 AddrRegImm r (ImmInt n)
134 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
135 | otherwise -> Nothing
138 AddrRegImm r (ImmInteger n)
139 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
140 | otherwise -> Nothing
141 where n2 = n + toInteger off
143 AddrRegReg r (FixedReg ILIT(0))
144 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
145 | otherwise -> Nothing
152 #if alpha_TARGET_ARCH
154 fits8Bits :: Integer -> Bool
155 fits8Bits i = i >= -256 && i < 256
159 #if sparc_TARGET_ARCH
161 fits13Bits :: Int -> Bool
164 fits13Bits :: Integer -> Bool
167 fits13Bits :: Integral a => a -> Bool
168 fits13Bits x = x >= -4096 && x < 4096
172 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
177 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
179 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
180 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
181 The rest are either in real machine registers or stored as offsets
185 data RegLoc = Save StixTree | Always StixTree
188 Trees for register save locations:
190 saveLoc :: MagicId -> StixTree
192 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
196 stgReg :: MagicId -> RegLoc
199 = case (magicIdRegMaybe x) of
200 Just _ -> Save nonReg
201 Nothing -> Always nonReg
203 offset = baseRegOffset x
205 baseLoc = case (magicIdRegMaybe BaseReg) of
206 Just _ -> StReg (StixMagicId BaseReg)
207 Nothing -> sStLitLbl SLIT("MainRegTable")
210 BaseReg -> sStLitLbl SLIT("MainRegTable")
212 _ -> StInd (magicIdPrimRep x)
213 (StPrim IntAddOp [baseLoc,
214 StInt (toInteger (offset*BYTES_PER_WORD))])
217 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
219 @spRel@ gives us a stack relative addressing mode for volatile
220 temporaries and for excess call arguments. @fpRel@, where
221 applicable, is the same but for the frame pointer.
224 spRel :: Int -- desired stack offset in words, positive or negative
229 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
231 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
234 #if sparc_TARGET_ARCH
235 fpRel :: Int -> MachRegsAddr
236 -- Duznae work for offsets greater than 13 bits; we just hope for
239 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
243 %************************************************************************
245 \subsection[Reg]{Real registers}
247 %************************************************************************
249 Static Registers correspond to actual machine registers. These should
250 be avoided until the last possible moment.
252 Dynamic registers are allocated on the fly, usually to represent a single
253 value in the abstract assembly code (i.e. dynamic registers are usually
254 single assignment). Ultimately, they are mapped to available machine
255 registers before spitting out the code.
259 = FixedReg FAST_INT -- A pre-allocated machine register
261 | MappedReg FAST_INT -- A dynamically allocated machine register
263 | MemoryReg Int PrimRep -- A machine "register" actually held in
264 -- a memory allocated table of
265 -- registers which didn't fit in real
268 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
269 -- always mapped to one of the earlier
270 -- two (?) before we're done.
271 mkReg :: Unique -> PrimRep -> Reg
274 getNewRegNCG :: PrimRep -> NatM Reg
276 = getUniqueNat `thenNat` \ u ->
277 returnNat (UnmappedReg u pk)
279 instance Show Reg where
280 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
281 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
282 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
283 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
286 instance Outputable Reg where
287 ppr r = text (show r)
290 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
291 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
292 cmpReg (MemoryReg i _) (MemoryReg i' _) = i `compare` i'
293 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = compare u u'
295 = let tag1 = tagReg r1
298 if tag1 _LT_ tag2 then LT else GT
300 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
301 tagReg (MappedReg _) = ILIT(2)
302 tagReg (MemoryReg _ _) = ILIT(3)
303 tagReg (UnmappedReg _ _) = ILIT(4)
305 cmp_ihash :: FAST_INT -> FAST_INT -> Ordering
306 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ else if a1 _LT_ a2 then LT else GT
308 instance Eq Reg where
309 a == b = case (a `compare` b) of { EQ -> True; _ -> False }
310 a /= b = case (a `compare` b) of { EQ -> False; _ -> True }
312 instance Ord Reg where
313 a <= b = case (a `compare` b) of { LT -> True; EQ -> True; GT -> False }
314 a < b = case (a `compare` b) of { LT -> True; EQ -> False; GT -> False }
315 a >= b = case (a `compare` b) of { LT -> False; EQ -> True; GT -> True }
316 a > b = case (a `compare` b) of { LT -> False; EQ -> False; GT -> True }
317 compare a b = cmpReg a b
319 instance Uniquable Reg where
320 getUnique (UnmappedReg u _) = u
321 getUnique (FixedReg i) = mkPseudoUnique1 IBOX(i)
322 getUnique (MappedReg i) = mkPseudoUnique2 IBOX(i)
323 getUnique (MemoryReg i _) = mkPseudoUnique3 i
329 realReg :: RegNo -> Reg
331 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
333 extractMappedRegNos :: [Reg] -> [RegNo]
335 extractMappedRegNos regs
338 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
339 ex _ acc = acc -- leave it out
341 mappedRegNo :: Reg -> RegNo
342 mappedRegNo (MappedReg i) = IBOX(i)
343 mappedRegNo _ = pprPanic "mappedRegNo" empty
346 ** Machine-specific Reg stuff: **
348 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
349 point registers. The mapping of STG registers to alpha machine registers
350 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
352 #if alpha_TARGET_ARCH
356 v0, f0, ra, pv, gp, sp, zeroh :: Reg
358 f0 = realReg (fReg 0)
359 ra = FixedReg ILIT(26)
361 gp = FixedReg ILIT(29)
362 sp = FixedReg ILIT(30)
363 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
365 t9, t10, t11, t12 :: Reg
373 Intel x86 architecture:
374 - All registers except 7 (esp) are available for use.
375 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
376 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
377 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
378 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
379 fp registers, and 3-operand insns for them, and we translate this into
380 real stack-based x86 fp code after register allocation.
385 gReg,fReg :: Int -> Int
389 fake0, fake1, fake2, fake3, fake4, fake5, eax, ebx, ecx, edx, esp :: Reg
390 eax = realReg (gReg 0)
391 ebx = realReg (gReg 1)
392 ecx = realReg (gReg 2)
393 edx = realReg (gReg 3)
394 esi = realReg (gReg 4)
395 edi = realReg (gReg 5)
396 ebp = realReg (gReg 6)
397 esp = realReg (gReg 7)
398 fake0 = realReg (fReg 0)
399 fake1 = realReg (fReg 1)
400 fake2 = realReg (fReg 2)
401 fake3 = realReg (fReg 3)
402 fake4 = realReg (fReg 4)
403 fake5 = realReg (fReg 5)
407 The SPARC has 64 registers of interest; 32 integer registers and 32
408 floating point registers. The mapping of STG registers to SPARC
409 machine registers is defined in StgRegs.h. We are, of course,
410 prepared for any eventuality.
413 #if sparc_TARGET_ARCH
415 gReg,lReg,iReg,oReg,fReg :: Int -> Int
423 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
424 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
426 g0, fp, sp, o0, f0 :: Reg
427 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
428 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
429 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
430 o0 = realReg (oReg 0)
431 f0 = realReg (fReg 0)
436 Redefine the literals used for machine-registers with non-numeric
437 names in the header files. Gag me with a spoon, eh?
439 #if alpha_TARGET_ARCH
489 #if sparc_TARGET_ARCH
558 baseRegOffset :: MagicId -> Int
560 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
561 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
562 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
563 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
564 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
565 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
566 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
567 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
568 baseRegOffset (VanillaReg _ ILIT(9)) = OFFSET_R9
569 baseRegOffset (VanillaReg _ ILIT(10)) = OFFSET_R10
570 baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1
571 baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2
572 baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3
573 baseRegOffset (FloatReg ILIT(4)) = OFFSET_F4
574 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_D1
575 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_D2
576 baseRegOffset Sp = OFFSET_Sp
577 baseRegOffset Su = OFFSET_Su
578 baseRegOffset SpLim = OFFSET_SpLim
580 baseRegOffset (LongReg _ ILIT(1)) = OFFSET_Lng1
583 baseRegOffset (LongReg _ ILIT(2)) = OFFSET_Lng2
585 baseRegOffset Hp = OFFSET_Hp
586 baseRegOffset HpLim = OFFSET_HpLim
587 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
588 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
590 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
591 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
592 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
597 callerSaves :: MagicId -> Bool
599 #ifdef CALLER_SAVES_Base
600 callerSaves BaseReg = True
602 #ifdef CALLER_SAVES_R1
603 callerSaves (VanillaReg _ ILIT(1)) = True
605 #ifdef CALLER_SAVES_R2
606 callerSaves (VanillaReg _ ILIT(2)) = True
608 #ifdef CALLER_SAVES_R3
609 callerSaves (VanillaReg _ ILIT(3)) = True
611 #ifdef CALLER_SAVES_R4
612 callerSaves (VanillaReg _ ILIT(4)) = True
614 #ifdef CALLER_SAVES_R5
615 callerSaves (VanillaReg _ ILIT(5)) = True
617 #ifdef CALLER_SAVES_R6
618 callerSaves (VanillaReg _ ILIT(6)) = True
620 #ifdef CALLER_SAVES_R7
621 callerSaves (VanillaReg _ ILIT(7)) = True
623 #ifdef CALLER_SAVES_R8
624 callerSaves (VanillaReg _ ILIT(8)) = True
626 #ifdef CALLER_SAVES_F1
627 callerSaves (FloatReg ILIT(1)) = True
629 #ifdef CALLER_SAVES_F2
630 callerSaves (FloatReg ILIT(2)) = True
632 #ifdef CALLER_SAVES_F3
633 callerSaves (FloatReg ILIT(3)) = True
635 #ifdef CALLER_SAVES_F4
636 callerSaves (FloatReg ILIT(4)) = True
638 #ifdef CALLER_SAVES_D1
639 callerSaves (DoubleReg ILIT(1)) = True
641 #ifdef CALLER_SAVES_D2
642 callerSaves (DoubleReg ILIT(2)) = True
644 #ifdef CALLER_SAVES_L1
645 callerSaves (LongReg _ ILIT(1)) = True
647 #ifdef CALLER_SAVES_Sp
648 callerSaves Sp = True
650 #ifdef CALLER_SAVES_Su
651 callerSaves Su = True
653 #ifdef CALLER_SAVES_SpLim
654 callerSaves SpLim = True
656 #ifdef CALLER_SAVES_Hp
657 callerSaves Hp = True
659 #ifdef CALLER_SAVES_HpLim
660 callerSaves HpLim = True
662 #ifdef CALLER_SAVES_CurrentTSO
663 callerSaves CurrentTSO = True
665 #ifdef CALLER_SAVES_CurrentNursery
666 callerSaves CurrentNursery = True
668 callerSaves _ = False
672 magicIdRegMaybe :: MagicId -> Maybe Reg
675 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
678 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
681 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
684 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
687 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
690 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
693 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
696 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
699 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
702 magicIdRegMaybe (VanillaReg _ ILIT(9)) = Just (FixedReg ILIT(REG_R9))
705 magicIdRegMaybe (VanillaReg _ ILIT(10)) = Just (FixedReg ILIT(REG_R10))
708 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_F1))
711 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_F2))
714 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_F3))
717 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_F4))
720 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_D1))
723 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_D2))
726 magicIdRegMaybe Sp = Just (FixedReg ILIT(REG_Sp))
729 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (FixedReg ILIT(REG_Lng1))
732 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (FixedReg ILIT(REG_Lng2))
735 magicIdRegMaybe Su = Just (FixedReg ILIT(REG_Su))
738 magicIdRegMaybe SpLim = Just (FixedReg ILIT(REG_SpLim))
741 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
744 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
746 #ifdef REG_CurrentTSO
747 magicIdRegMaybe CurrentTSO = Just (FixedReg ILIT(REG_CurrentTSO))
749 #ifdef REG_CurrentNursery
750 magicIdRegMaybe CurrentNursery = Just (FixedReg ILIT(REG_CurrentNursery))
752 magicIdRegMaybe _ = Nothing
756 -------------------------------
759 = freeMappedRegs IF_ARCH_alpha( [0..63],
760 IF_ARCH_i386( [0..13],
761 IF_ARCH_sparc( [0..63],)))
763 -------------------------------
764 callClobberedRegs :: [Reg]
767 #if alpha_TARGET_ARCH
768 [0, 1, 2, 3, 4, 5, 6, 7, 8,
769 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
770 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
771 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
772 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
773 #endif {- alpha_TARGET_ARCH -}
776 #endif {- i386_TARGET_ARCH -}
777 #if sparc_TARGET_ARCH
779 [oReg i | i <- [0..5]] ++
780 [gReg i | i <- [1..7]] ++
781 [fReg i | i <- [0..31]] )
782 #endif {- sparc_TARGET_ARCH -}
784 -------------------------------
785 argRegs :: Int -> [Reg]
789 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
791 #if alpha_TARGET_ARCH
792 argRegs 1 = freeMappedRegs [16, fReg 16]
793 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
794 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
795 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
796 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
797 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
798 #endif {- alpha_TARGET_ARCH -}
799 #if sparc_TARGET_ARCH
800 argRegs 1 = freeMappedRegs (map oReg [0])
801 argRegs 2 = freeMappedRegs (map oReg [0,1])
802 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
803 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
804 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
805 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
806 #endif {- sparc_TARGET_ARCH -}
807 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
808 #endif {- i386_TARGET_ARCH -}
810 -------------------------------
812 #if alpha_TARGET_ARCH
813 allArgRegs :: [(Reg, Reg)]
815 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
816 #endif {- alpha_TARGET_ARCH -}
818 #if sparc_TARGET_ARCH
821 allArgRegs = map realReg [oReg i | i <- [0..5]]
822 #endif {- sparc_TARGET_ARCH -}
824 -------------------------------
825 freeMappedRegs :: [Int] -> [Reg]
831 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
835 freeReg :: FAST_INT -> FAST_BOOL
837 #if alpha_TARGET_ARCH
838 freeReg ILIT(26) = _FALSE_ -- return address (ra)
839 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
840 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
841 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
842 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
843 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
847 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
850 #if sparc_TARGET_ARCH
851 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
852 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
853 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
854 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
855 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
856 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
860 freeReg ILIT(REG_Base) = _FALSE_
863 freeReg ILIT(REG_R1) = _FALSE_
866 freeReg ILIT(REG_R2) = _FALSE_
869 freeReg ILIT(REG_R3) = _FALSE_
872 freeReg ILIT(REG_R4) = _FALSE_
875 freeReg ILIT(REG_R5) = _FALSE_
878 freeReg ILIT(REG_R6) = _FALSE_
881 freeReg ILIT(REG_R7) = _FALSE_
884 freeReg ILIT(REG_R8) = _FALSE_
887 freeReg ILIT(REG_F1) = _FALSE_
890 freeReg ILIT(REG_F2) = _FALSE_
893 freeReg ILIT(REG_F3) = _FALSE_
896 freeReg ILIT(REG_F4) = _FALSE_
899 freeReg ILIT(REG_D1) = _FALSE_
902 freeReg ILIT(REG_D2) = _FALSE_
905 freeReg ILIT(REG_Sp) = _FALSE_
908 freeReg ILIT(REG_Su) = _FALSE_
911 freeReg ILIT(REG_SpLim) = _FALSE_
914 freeReg ILIT(REG_Hp) = _FALSE_
917 freeReg ILIT(REG_HpLim) = _FALSE_
920 -- we hang onto two double regs for dedicated
921 -- use; this is not necessary on Alphas and
922 -- may not be on other non-SPARCs.
924 | n _EQ_ (ILIT(REG_D1) _ADD_ ILIT(1)) = _FALSE_
927 | n _EQ_ (ILIT(REG_D2) _ADD_ ILIT(1)) = _FALSE_