2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
17 RegClass(..), regClass,
18 VRegUnique(..), pprVRegUnique, getHiVRegFromLo,
19 Reg(..), isRealReg, isVirtualReg, getVRegUnique,
20 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
31 get_MagicId_reg_or_addr,
33 get_Regtable_addr_from_offset,
41 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
44 , eax, ebx, ecx, edx, esi, esp
45 , fake0, fake1, fake2, fake3, fake4, fake5
49 , fpRel, gReg, iReg, lReg, oReg, largeOffsetError
50 , fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27
53 #if powerpc_TARGET_ARCH
62 #include "HsVersions.h"
64 import AbsCSyn ( MagicId(..) )
65 import CLabel ( CLabel, mkMainCapabilityLabel )
66 import PrimRep ( PrimRep(..), isFloatingRep )
67 import Stix ( StixExpr(..), StixReg(..),
68 getUniqueNat, returnNat, thenNat, NatM )
69 import Unique ( Unique )
71 import Outputable ( Outputable(..), pprPanic, panic )
72 import qualified Outputable
76 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
81 | ImmInteger Integer -- Sigh.
82 | ImmCLbl CLabel -- AbstractC Label (with baggage)
83 | ImmLab Bool Doc -- Simple string label (underscore-able)
84 -- Bool==True ==> in a different DLL
85 | ImmLit Doc -- Simple string
90 | LO Imm {- Possible restrictions... -}
95 | HA Imm {- high halfword adjusted -}
97 strImmLit s = ImmLit (text s)
100 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
104 #if alpha_TARGET_ARCH
111 = AddrBaseIndex Base Index Displacement
114 type Base = Maybe Reg
115 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
116 type Displacement = Imm
119 #if sparc_TARGET_ARCH
124 #if powerpc_TARGET_ARCH
129 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
133 #if alpha_TARGET_ARCH
134 _ -> panic "MachMisc.addrOffset not defined for Alpha"
137 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
138 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
139 AddrBaseIndex r i (ImmInteger n)
140 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
143 #if sparc_TARGET_ARCH
144 AddrRegImm r (ImmInt n)
145 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
146 | otherwise -> Nothing
149 AddrRegImm r (ImmInteger n)
150 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
151 | otherwise -> Nothing
152 where n2 = n + toInteger off
154 AddrRegReg r (RealReg 0)
155 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
156 | otherwise -> Nothing
161 #if powerpc_TARGET_ARCH
162 AddrRegImm r (ImmInt n)
163 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
164 | otherwise -> Nothing
167 AddrRegImm r (ImmInteger n)
168 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
169 | otherwise -> Nothing
170 where n2 = n + toInteger off
172 AddrRegReg r (RealReg 0)
173 | fits16Bits off -> Just (AddrRegImm r (ImmInt off))
174 | otherwise -> Nothing
180 #if alpha_TARGET_ARCH
182 fits8Bits :: Integer -> Bool
183 fits8Bits i = i >= -256 && i < 256
187 #if sparc_TARGET_ARCH
189 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
190 fits13Bits :: Integral a => a -> Bool
191 fits13Bits x = x >= -4096 && x < 4096
195 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
196 ++show i++");\nprobably because of large constant data structures;" ++
197 "\nworkaround: use -fvia-C on this module.\n")
201 #if powerpc_TARGET_ARCH
202 fits16Bits :: Integral a => a -> Bool
203 fits16Bits x = x >= -32768 && x < 32768
207 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
209 @stgReg@: we map STG registers onto appropriate Stix Trees. Either
210 they map to real machine registers or stored as offsets from BaseReg.
211 Given a MagicId, get_MagicId_reg_or_addr produces either the real
212 register it is in, on this platform, or a StixExpr denoting the
213 address in the register table holding it. get_MagicId_addr always
214 produces the register table address for it.
217 get_MagicId_reg_or_addr :: MagicId -> Either Reg StixExpr
218 get_MagicId_addr :: MagicId -> StixExpr
219 get_Regtable_addr_from_offset :: Int -> StixExpr
221 get_MagicId_reg_or_addr mid
222 = case magicIdRegMaybe mid of
224 Nothing -> Right (get_MagicId_addr mid)
226 get_MagicId_addr BaseReg
227 = -- This arch doesn't have BaseReg in a register, so we have to
228 -- use &MainRegTable.r instead.
229 StIndex PtrRep (StCLbl mkMainCapabilityLabel)
230 (StInt (toInteger OFFW_Capability_r))
232 = get_Regtable_addr_from_offset (baseRegOffset mid)
234 get_Regtable_addr_from_offset offset_in_words
235 = let ptr_to_RegTable
236 = case magicIdRegMaybe BaseReg of
238 -> -- This arch doesn't have BaseReg in a register, so we have to
239 -- use &MainRegTable.r instead.
240 StIndex PtrRep (StCLbl mkMainCapabilityLabel)
241 (StInt (toInteger OFFW_Capability_r))
243 -> -- It's in a reg, so leave it as it is
244 StReg (StixMagicId BaseReg)
246 StIndex PtrRep ptr_to_RegTable (StInt (toInteger offset_in_words))
249 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
251 @spRel@ gives us a stack relative addressing mode for volatile
252 temporaries and for excess call arguments. @fpRel@, where
253 applicable, is the same but for the frame pointer.
256 spRel :: Int -- desired stack offset in words, positive or negative
261 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
263 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
266 #if sparc_TARGET_ARCH
267 fpRel :: Int -> MachRegsAddr
268 -- Duznae work for offsets greater than 13 bits; we just hope for
271 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
275 %************************************************************************
277 \subsection[Reg]{Real registers}
279 %************************************************************************
281 RealRegs are machine regs which are available for allocation, in the
282 usual way. We know what class they are, because that's part of the
283 processor's architecture.
285 VirtualRegs are virtual registers. The register allocator will
286 eventually have to map them into RealRegs, or into spill slots.
287 VirtualRegs are allocated on the fly, usually to represent a single
288 value in the abstract assembly code (i.e. dynamic registers are
289 usually single assignment). With the new register allocator, the
290 single assignment restriction isn't necessary to get correct code,
291 although a better register allocation will result if single assignment
292 is used -- because the allocator maps a VirtualReg into a single
293 RealReg, even if the VirtualReg has multiple live ranges.
295 Virtual regs can be of either class, so that info is attached.
300 = VRegUniqueLo Unique -- lower part of a split quantity
301 | VRegUniqueHi Unique -- upper part thereof
304 instance Show VRegUnique where
305 show (VRegUniqueLo u) = show u
306 show (VRegUniqueHi u) = "_hi_" ++ show u
308 pprVRegUnique :: VRegUnique -> Outputable.SDoc
310 = Outputable.text . show
312 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
313 -- when supplied with the vreg for the lower-half of the quantity.
314 getHiVRegFromLo (VirtualRegI (VRegUniqueLo u))
315 = VirtualRegI (VRegUniqueHi u)
316 getHiVRegFromLo other
317 = pprPanic "getHiVRegFromLo" (ppr other)
327 | VirtualRegI VRegUnique
328 | VirtualRegF VRegUnique
329 | VirtualRegD VRegUnique
331 unRealReg (RealReg i) = i
332 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
334 getVRegUnique :: Reg -> VRegUnique
335 getVRegUnique (VirtualRegI vu) = vu
336 getVRegUnique (VirtualRegF vu) = vu
337 getVRegUnique (VirtualRegD vu) = vu
338 getVRegUnique rreg = pprPanic "getVRegUnique on RealReg" (ppr rreg)
340 mkVReg :: Unique -> PrimRep -> Reg
342 #if sparc_TARGET_ARCH
344 FloatRep -> VirtualRegF (VRegUniqueLo u)
345 DoubleRep -> VirtualRegD (VRegUniqueLo u)
346 other -> VirtualRegI (VRegUniqueLo u)
348 = if isFloatingRep pk then VirtualRegD (VRegUniqueLo u)
349 else VirtualRegI (VRegUniqueLo u)
352 isVirtualReg (RealReg _) = False
353 isVirtualReg (VirtualRegI _) = True
354 isVirtualReg (VirtualRegF _) = True
355 isVirtualReg (VirtualRegD _) = True
356 isRealReg = not . isVirtualReg
358 getNewRegNCG :: PrimRep -> NatM Reg
360 = getUniqueNat `thenNat` \ u -> returnNat (mkVReg u pk)
362 instance Eq Reg where
363 (==) (RealReg i1) (RealReg i2) = i1 == i2
364 (==) (VirtualRegI u1) (VirtualRegI u2) = u1 == u2
365 (==) (VirtualRegF u1) (VirtualRegF u2) = u1 == u2
366 (==) (VirtualRegD u1) (VirtualRegD u2) = u1 == u2
367 (==) reg1 reg2 = False
369 instance Ord Reg where
370 compare (RealReg i1) (RealReg i2) = compare i1 i2
371 compare (RealReg _) (VirtualRegI _) = LT
372 compare (RealReg _) (VirtualRegF _) = LT
373 compare (RealReg _) (VirtualRegD _) = LT
375 compare (VirtualRegI _) (RealReg _) = GT
376 compare (VirtualRegI u1) (VirtualRegI u2) = compare u1 u2
377 compare (VirtualRegI _) (VirtualRegF _) = LT
378 compare (VirtualRegI _) (VirtualRegD _) = LT
380 compare (VirtualRegF _) (RealReg _) = GT
381 compare (VirtualRegF _) (VirtualRegI _) = GT
382 compare (VirtualRegF u1) (VirtualRegF u2) = compare u1 u2
383 compare (VirtualRegF _) (VirtualRegD _) = LT
385 compare (VirtualRegD _) (RealReg _) = GT
386 compare (VirtualRegD _) (VirtualRegI _) = GT
387 compare (VirtualRegD _) (VirtualRegF _) = GT
388 compare (VirtualRegD u1) (VirtualRegD u2) = compare u1 u2
391 instance Show Reg where
392 show (RealReg i) = showReg i
393 show (VirtualRegI u) = "%vI_" ++ show u
394 show (VirtualRegF u) = "%vF_" ++ show u
395 show (VirtualRegD u) = "%vD_" ++ show u
397 instance Outputable Reg where
398 ppr r = Outputable.text (show r)
401 ** Machine-specific Reg stuff: **
403 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
404 point registers. The mapping of STG registers to alpha machine registers
405 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
407 #if alpha_TARGET_ARCH
411 v0, f0, ra, pv, gp, sp, zeroh :: Reg
413 f0 = realReg (fReg 0)
414 ra = FixedReg ILIT(26)
416 gp = FixedReg ILIT(29)
417 sp = FixedReg ILIT(30)
418 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
420 t9, t10, t11, t12 :: Reg
428 Intel x86 architecture:
429 - All registers except 7 (esp) are available for use.
430 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
431 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
432 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
433 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
434 fp registers, and 3-operand insns for them, and we translate this into
435 real stack-based x86 fp code after register allocation.
437 The fp registers are all Double registers; we don't have any RcFloat class
438 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
444 fake0, fake1, fake2, fake3, fake4, fake5,
445 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
461 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
462 regClass (VirtualRegI u) = RcInteger
463 regClass (VirtualRegD u) = RcDouble
464 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
465 (ppr (VirtualRegF u))
468 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
469 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
471 showReg :: Int -> String
473 = if n >= 0 && n < 14
475 else "%unknown_x86_real_reg_" ++ show n
480 The SPARC has 64 registers of interest; 32 integer registers and 32
481 floating point registers. The mapping of STG registers to SPARC
482 machine registers is defined in StgRegs.h. We are, of course,
483 prepared for any eventuality.
485 The whole fp-register pairing thing on sparcs is a huge nuisance. See
486 fptools/ghc/includes/MachRegs.h for a description of what's going on
490 #if sparc_TARGET_ARCH
492 gReg,lReg,iReg,oReg,fReg :: Int -> Int
499 nCG_FirstFloatReg :: Int
500 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
502 regClass (VirtualRegI u) = RcInteger
503 regClass (VirtualRegF u) = RcFloat
504 regClass (VirtualRegD u) = RcDouble
505 regClass (RealReg i) | i < 32 = RcInteger
506 | i < nCG_FirstFloatReg = RcDouble
507 | otherwise = RcFloat
509 showReg :: Int -> String
511 | n >= 0 && n < 8 = "%g" ++ show n
512 | n >= 8 && n < 16 = "%o" ++ show (n-8)
513 | n >= 16 && n < 24 = "%l" ++ show (n-16)
514 | n >= 24 && n < 32 = "%i" ++ show (n-24)
515 | n >= 32 && n < 64 = "%f" ++ show (n-32)
516 | otherwise = "%unknown_sparc_real_reg_" ++ show n
518 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
520 f6 = RealReg (fReg 6)
521 f8 = RealReg (fReg 8)
522 f22 = RealReg (fReg 22)
523 f26 = RealReg (fReg 26)
524 f27 = RealReg (fReg 27)
527 -- g0 is useful for codegen; is always zero, and writes to it vanish.
528 g0 = RealReg (gReg 0)
529 g1 = RealReg (gReg 1)
530 g2 = RealReg (gReg 2)
532 -- FP, SP, int and float return (from C) regs.
533 fp = RealReg (iReg 6)
534 sp = RealReg (oReg 6)
535 o0 = RealReg (oReg 0)
536 o1 = RealReg (oReg 1)
537 f0 = RealReg (fReg 0)
538 f1 = RealReg (fReg 1)
543 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
546 #if powerpc_TARGET_ARCH
550 regClass (VirtualRegI u) = RcInteger
551 regClass (VirtualRegF u) = RcFloat
552 regClass (VirtualRegD u) = RcDouble
553 regClass (RealReg i) | i < 32 = RcInteger
554 | otherwise = RcDouble
555 -- | i < nCG_FirstFloatReg = RcDouble
556 -- | otherwise = RcFloat
558 showReg :: Int -> String
560 | n >= 0 && n <= 31 = "%r" ++ show n
561 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
562 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
569 f1 = RealReg $ fReg 1
570 f20 = RealReg $ fReg 20
571 f21 = RealReg $ fReg 21
575 Redefine the literals used for machine-registers with non-numeric
576 names in the header files. Gag me with a spoon, eh?
578 #if alpha_TARGET_ARCH
628 #if sparc_TARGET_ARCH
696 #if powerpc_TARGET_ARCH
730 #ifdef darwin_TARGET_OS
801 baseRegOffset :: MagicId -> Int
803 baseRegOffset (VanillaReg _ 1#) = OFFSET_R1
804 baseRegOffset (VanillaReg _ 2#) = OFFSET_R2
805 baseRegOffset (VanillaReg _ 3#) = OFFSET_R3
806 baseRegOffset (VanillaReg _ 4#) = OFFSET_R4
807 baseRegOffset (VanillaReg _ 5#) = OFFSET_R5
808 baseRegOffset (VanillaReg _ 6#) = OFFSET_R6
809 baseRegOffset (VanillaReg _ 7#) = OFFSET_R7
810 baseRegOffset (VanillaReg _ 8#) = OFFSET_R8
811 baseRegOffset (VanillaReg _ 9#) = OFFSET_R9
812 baseRegOffset (VanillaReg _ 10#) = OFFSET_R10
813 baseRegOffset (FloatReg 1#) = OFFSET_F1
814 baseRegOffset (FloatReg 2#) = OFFSET_F2
815 baseRegOffset (FloatReg 3#) = OFFSET_F3
816 baseRegOffset (FloatReg 4#) = OFFSET_F4
817 baseRegOffset (DoubleReg 1#) = OFFSET_D1
818 baseRegOffset (DoubleReg 2#) = OFFSET_D2
819 baseRegOffset Sp = OFFSET_Sp
820 baseRegOffset SpLim = OFFSET_SpLim
822 baseRegOffset (LongReg _ 1#) = OFFSET_L1
824 baseRegOffset Hp = OFFSET_Hp
825 baseRegOffset HpLim = OFFSET_HpLim
826 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
827 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
828 baseRegOffset HpAlloc = OFFSET_HpAlloc
830 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
831 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
832 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
837 callerSaves :: MagicId -> Bool
839 #ifdef CALLER_SAVES_Base
840 callerSaves BaseReg = True
842 #ifdef CALLER_SAVES_R1
843 callerSaves (VanillaReg _ ILIT(1)) = True
845 #ifdef CALLER_SAVES_R2
846 callerSaves (VanillaReg _ ILIT(2)) = True
848 #ifdef CALLER_SAVES_R3
849 callerSaves (VanillaReg _ ILIT(3)) = True
851 #ifdef CALLER_SAVES_R4
852 callerSaves (VanillaReg _ ILIT(4)) = True
854 #ifdef CALLER_SAVES_R5
855 callerSaves (VanillaReg _ ILIT(5)) = True
857 #ifdef CALLER_SAVES_R6
858 callerSaves (VanillaReg _ ILIT(6)) = True
860 #ifdef CALLER_SAVES_R7
861 callerSaves (VanillaReg _ ILIT(7)) = True
863 #ifdef CALLER_SAVES_R8
864 callerSaves (VanillaReg _ ILIT(8)) = True
866 #ifdef CALLER_SAVES_F1
867 callerSaves (FloatReg 1#) = True
869 #ifdef CALLER_SAVES_F2
870 callerSaves (FloatReg 2#) = True
872 #ifdef CALLER_SAVES_F3
873 callerSaves (FloatReg 3#) = True
875 #ifdef CALLER_SAVES_F4
876 callerSaves (FloatReg 4#) = True
878 #ifdef CALLER_SAVES_D1
879 callerSaves (DoubleReg 1#) = True
881 #ifdef CALLER_SAVES_D2
882 callerSaves (DoubleReg 2#) = True
884 #ifdef CALLER_SAVES_L1
885 callerSaves (LongReg _ ILIT(1)) = True
887 #ifdef CALLER_SAVES_Sp
888 callerSaves Sp = True
890 #ifdef CALLER_SAVES_SpLim
891 callerSaves SpLim = True
893 #ifdef CALLER_SAVES_Hp
894 callerSaves Hp = True
896 #ifdef CALLER_SAVES_HpLim
897 callerSaves HpLim = True
899 #ifdef CALLER_SAVES_CurrentTSO
900 callerSaves CurrentTSO = True
902 #ifdef CALLER_SAVES_CurrentNursery
903 callerSaves CurrentNursery = True
905 callerSaves _ = False
909 magicIdRegMaybe :: MagicId -> Maybe Reg
912 magicIdRegMaybe BaseReg = Just (RealReg REG_Base)
915 magicIdRegMaybe (VanillaReg _ 1#) = Just (RealReg REG_R1)
918 magicIdRegMaybe (VanillaReg _ 2#) = Just (RealReg REG_R2)
921 magicIdRegMaybe (VanillaReg _ 3#) = Just (RealReg REG_R3)
924 magicIdRegMaybe (VanillaReg _ 4#) = Just (RealReg REG_R4)
927 magicIdRegMaybe (VanillaReg _ 5#) = Just (RealReg REG_R5)
930 magicIdRegMaybe (VanillaReg _ 6#) = Just (RealReg REG_R6)
933 magicIdRegMaybe (VanillaReg _ 7#) = Just (RealReg REG_R7)
936 magicIdRegMaybe (VanillaReg _ 8#) = Just (RealReg REG_R8)
939 magicIdRegMaybe (VanillaReg _ 9#) = Just (RealReg REG_R9)
942 magicIdRegMaybe (VanillaReg _ 10#) = Just (RealReg REG_R10)
945 magicIdRegMaybe (FloatReg 1#) = Just (RealReg REG_F1)
948 magicIdRegMaybe (FloatReg 2#) = Just (RealReg REG_F2)
951 magicIdRegMaybe (FloatReg 3#) = Just (RealReg REG_F3)
954 magicIdRegMaybe (FloatReg 4#) = Just (RealReg REG_F4)
957 magicIdRegMaybe (DoubleReg 1#) = Just (RealReg REG_D1)
960 magicIdRegMaybe (DoubleReg 2#) = Just (RealReg REG_D2)
963 magicIdRegMaybe Sp = Just (RealReg REG_Sp)
966 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (RealReg REG_Lng1)
969 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (RealReg REG_Lng2)
972 magicIdRegMaybe SpLim = Just (RealReg REG_SpLim)
975 magicIdRegMaybe Hp = Just (RealReg REG_Hp)
978 magicIdRegMaybe HpLim = Just (RealReg REG_HpLim)
980 #ifdef REG_CurrentTSO
981 magicIdRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
983 #ifdef REG_CurrentNursery
984 magicIdRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
986 magicIdRegMaybe _ = Nothing
990 -------------------------------
991 -- allMachRegs is the complete set of machine regs.
992 allMachRegNos :: [Int]
994 = IF_ARCH_alpha( [0..63],
995 IF_ARCH_i386( [0..13],
996 IF_ARCH_sparc( ([0..31]
997 ++ [f0,f2 .. nCG_FirstFloatReg-1]
998 ++ [nCG_FirstFloatReg .. f31]),
999 IF_ARCH_powerpc([0..63],
1001 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1002 -- i.e., these are the regs for which we are prepared to allow the
1003 -- register allocator to attempt to map VRegs to.
1004 allocatableRegs :: [Reg]
1006 = let isFree i = isFastTrue (freeReg i)
1007 in map RealReg (filter isFree allMachRegNos)
1009 -------------------------------
1010 -- these are the regs which we cannot assume stay alive over a
1012 callClobberedRegs :: [Reg]
1015 #if alpha_TARGET_ARCH
1016 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1017 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1018 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1019 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1020 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1021 #endif /* alpha_TARGET_ARCH */
1022 #if i386_TARGET_ARCH
1023 -- caller-saves registers
1024 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1025 #endif /* i386_TARGET_ARCH */
1026 #if sparc_TARGET_ARCH
1029 [oReg i | i <- [0..5]] ++
1030 [gReg i | i <- [1..7]] ++
1031 [fReg i | i <- [0..31]] )
1032 #endif /* sparc_TARGET_ARCH */
1033 #if powerpc_TARGET_ARCH
1034 map RealReg ([0..12] ++ map fReg [0..13])
1035 #endif /* powerpc_TARGET_ARCH */
1037 -------------------------------
1038 -- argRegs is the set of regs which are read for an n-argument call to C.
1039 -- For archs which pass all args on the stack (x86), is empty.
1040 -- Sparc passes up to the first 6 args in regs.
1041 -- Dunno about Alpha.
1042 argRegs :: Int -> [Reg]
1044 #if i386_TARGET_ARCH
1045 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1048 #if alpha_TARGET_ARCH
1050 argRegs 1 = freeMappedRegs [16, fReg 16]
1051 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1052 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1053 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1054 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1055 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1056 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1057 #endif /* alpha_TARGET_ARCH */
1059 #if sparc_TARGET_ARCH
1061 argRegs 1 = map (RealReg . oReg) [0]
1062 argRegs 2 = map (RealReg . oReg) [0,1]
1063 argRegs 3 = map (RealReg . oReg) [0,1,2]
1064 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1065 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1066 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1067 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1068 #endif /* sparc_TARGET_ARCH */
1070 #if powerpc_TARGET_ARCH
1072 argRegs 1 = map RealReg [3]
1073 argRegs 2 = map RealReg [3,4]
1074 argRegs 3 = map RealReg [3..5]
1075 argRegs 4 = map RealReg [3..6]
1076 argRegs 5 = map RealReg [3..7]
1077 argRegs 6 = map RealReg [3..8]
1078 argRegs 7 = map RealReg [3..9]
1079 argRegs 8 = map RealReg [3..10]
1080 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1081 #endif /* powerpc_TARGET_ARCH */
1083 -------------------------------
1084 -- all of the arg regs ??
1085 #if alpha_TARGET_ARCH
1086 allArgRegs :: [(Reg, Reg)]
1087 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1088 #endif /* alpha_TARGET_ARCH */
1090 #if sparc_TARGET_ARCH
1092 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1093 #endif /* sparc_TARGET_ARCH */
1095 #if i386_TARGET_ARCH
1097 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1100 #if powerpc_TARGET_ARCH
1102 allArgRegs = map RealReg [3..10]
1103 allFPArgRegs :: [Reg]
1104 allFPArgRegs = map (RealReg . fReg) [1..13]
1105 #endif /* powerpc_TARGET_ARCH */
1109 freeReg :: Int -> FastBool
1111 #if alpha_TARGET_ARCH
1112 freeReg 26 = fastBool False -- return address (ra)
1113 freeReg 28 = fastBool False -- reserved for the assembler (at)
1114 freeReg 29 = fastBool False -- global pointer (gp)
1115 freeReg 30 = fastBool False -- stack pointer (sp)
1116 freeReg 31 = fastBool False -- always zero (zeroh)
1117 freeReg 63 = fastBool False -- always zero (f31)
1120 #if i386_TARGET_ARCH
1121 freeReg esp = fastBool False -- %esp is the C stack pointer
1124 #if sparc_TARGET_ARCH
1125 freeReg g0 = fastBool False -- %g0 is always 0.
1126 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1127 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1128 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1129 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1130 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1131 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1132 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1133 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1134 freeReg f1 = fastBool False
1137 #if powerpc_TARGET_ARCH
1138 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1139 freeReg 1 = fastBool False -- The Stack Pointer
1140 #if !darwin_TARGET_OS
1141 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1142 freeReg 2 = fastBool False
1147 freeReg REG_Base = fastBool False
1150 freeReg REG_R1 = fastBool False
1153 freeReg REG_R2 = fastBool False
1156 freeReg REG_R3 = fastBool False
1159 freeReg REG_R4 = fastBool False
1162 freeReg REG_R5 = fastBool False
1165 freeReg REG_R6 = fastBool False
1168 freeReg REG_R7 = fastBool False
1171 freeReg REG_R8 = fastBool False
1174 freeReg REG_F1 = fastBool False
1177 freeReg REG_F2 = fastBool False
1180 freeReg REG_F3 = fastBool False
1183 freeReg REG_F4 = fastBool False
1186 freeReg REG_D1 = fastBool False
1189 freeReg REG_D2 = fastBool False
1192 freeReg REG_Sp = fastBool False
1195 freeReg REG_Su = fastBool False
1198 freeReg REG_SpLim = fastBool False
1201 freeReg REG_Hp = fastBool False
1204 freeReg REG_HpLim = fastBool False
1206 freeReg n = fastBool True