2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
46 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
49 , eax, ebx, ecx, edx, esi, esp
50 , st0, st1, st2, st3, st4, st5, st6, st7
55 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
61 #include "HsVersions.h"
63 import AbsCSyn ( MagicId(..) )
64 import AbsCUtils ( magicIdPrimRep )
65 import CLabel ( CLabel )
66 import PrimOp ( PrimOp(..) )
67 import PrimRep ( PrimRep(..) )
68 import Stix ( sStLitLbl, StixTree(..), StixReg(..) )
69 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
72 import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM )
76 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
81 | ImmInteger Integer -- Sigh.
82 | ImmCLbl CLabel -- AbstractC Label (with baggage)
83 | ImmLab SDoc -- Simple string label (underscore-able)
84 | ImmLit SDoc -- Simple string
87 | LO Imm -- Possible restrictions...
90 strImmLit s = ImmLit (text s)
93 IF_ARCH_alpha({-prepend nothing-}
94 ,IF_ARCH_i386( '0' : 'd' :
95 ,IF_ARCH_sparc('0' : 'r' :,)))
96 showSDoc (rational r))
99 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
103 #if alpha_TARGET_ARCH
110 = AddrBaseIndex Base Index Displacement
113 type Base = Maybe Reg
114 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
115 type Displacement = Imm
118 #if sparc_TARGET_ARCH
123 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
127 #if alpha_TARGET_ARCH
128 _ -> panic "MachMisc.addrOffset not defined for Alpha"
131 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
132 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
133 AddrBaseIndex r i (ImmInteger n)
134 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
137 #if sparc_TARGET_ARCH
138 AddrRegImm r (ImmInt n)
139 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
140 | otherwise -> Nothing
143 AddrRegImm r (ImmInteger n)
144 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
145 | otherwise -> Nothing
146 where n2 = n + toInteger off
148 AddrRegReg r (FixedReg ILIT(0))
149 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
150 | otherwise -> Nothing
157 #if alpha_TARGET_ARCH
159 fits8Bits :: Integer -> Bool
160 fits8Bits i = i >= -256 && i < 256
164 #if sparc_TARGET_ARCH
166 fits13Bits :: Int -> Bool
169 fits13Bits :: Integer -> Bool
172 fits13Bits :: Integral a => a -> Bool
173 fits13Bits x = x >= -4096 && x < 4096
177 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
182 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
184 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
185 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
186 The rest are either in real machine registers or stored as offsets
190 data RegLoc = Save StixTree | Always StixTree
193 Trees for register save locations:
195 saveLoc :: MagicId -> StixTree
197 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
201 stgReg :: MagicId -> RegLoc
204 = case (magicIdRegMaybe x) of
205 Just _ -> Save nonReg
206 Nothing -> Always nonReg
208 offset = baseRegOffset x
210 baseLoc = case (magicIdRegMaybe BaseReg) of
211 Just _ -> StReg (StixMagicId BaseReg)
212 Nothing -> sStLitLbl SLIT("MainRegTable")
215 BaseReg -> sStLitLbl SLIT("MainRegTable")
217 _ -> StInd (magicIdPrimRep x)
218 (StPrim IntAddOp [baseLoc,
219 StInt (toInteger (offset*BYTES_PER_WORD))])
222 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
224 @spRel@ gives us a stack relative addressing mode for volatile
225 temporaries and for excess call arguments. @fpRel@, where
226 applicable, is the same but for the frame pointer.
229 spRel :: Int -- desired stack offset in words, positive or negative
234 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
236 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
239 #if sparc_TARGET_ARCH
240 fpRel :: Int -> MachRegsAddr
241 -- Duznae work for offsets greater than 13 bits; we just hope for
244 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
248 %************************************************************************
250 \subsection[Reg]{Real registers}
252 %************************************************************************
254 Static Registers correspond to actual machine registers. These should
255 be avoided until the last possible moment.
257 Dynamic registers are allocated on the fly, usually to represent a single
258 value in the abstract assembly code (i.e. dynamic registers are usually
259 single assignment). Ultimately, they are mapped to available machine
260 registers before spitting out the code.
264 = FixedReg FAST_INT -- A pre-allocated machine register
266 | MappedReg FAST_INT -- A dynamically allocated machine register
268 | MemoryReg Int PrimRep -- A machine "register" actually held in
269 -- a memory allocated table of
270 -- registers which didn't fit in real
273 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
274 -- always mapped to one of the earlier
275 -- two (?) before we're done.
276 mkReg :: Unique -> PrimRep -> Reg
279 getNewRegNCG :: PrimRep -> UniqSM Reg
281 = getUniqueUs `thenUs` \ u ->
282 returnUs (UnmappedReg u pk)
284 instance Text Reg where
285 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
286 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
287 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
288 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
291 instance Outputable Reg where
292 ppr r = text (show r)
295 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
296 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
297 cmpReg (MemoryReg i _) (MemoryReg i' _) = i `compare` i'
298 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = compare u u'
300 = let tag1 = tagReg r1
303 if tag1 _LT_ tag2 then LT else GT
305 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
306 tagReg (MappedReg _) = ILIT(2)
307 tagReg (MemoryReg _ _) = ILIT(3)
308 tagReg (UnmappedReg _ _) = ILIT(4)
310 cmp_ihash :: FAST_INT -> FAST_INT -> Ordering
311 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ else if a1 _LT_ a2 then LT else GT
313 instance Eq Reg where
314 a == b = case (a `compare` b) of { EQ -> True; _ -> False }
315 a /= b = case (a `compare` b) of { EQ -> False; _ -> True }
317 instance Ord Reg where
318 a <= b = case (a `compare` b) of { LT -> True; EQ -> True; GT -> False }
319 a < b = case (a `compare` b) of { LT -> True; EQ -> False; GT -> False }
320 a >= b = case (a `compare` b) of { LT -> False; EQ -> True; GT -> True }
321 a > b = case (a `compare` b) of { LT -> False; EQ -> False; GT -> True }
322 compare a b = cmpReg a b
324 instance Uniquable Reg where
325 getUnique (UnmappedReg u _) = u
326 getUnique (FixedReg i) = mkPseudoUnique1 IBOX(i)
327 getUnique (MappedReg i) = mkPseudoUnique2 IBOX(i)
328 getUnique (MemoryReg i _) = mkPseudoUnique3 i
334 realReg :: RegNo -> Reg
336 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
338 extractMappedRegNos :: [Reg] -> [RegNo]
340 extractMappedRegNos regs
343 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
344 ex _ acc = acc -- leave it out
347 ** Machine-specific Reg stuff: **
349 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
350 point registers. The mapping of STG registers to alpha machine registers
351 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
353 #if alpha_TARGET_ARCH
357 v0, f0, ra, pv, gp, sp, zeroh :: Reg
359 f0 = realReg (fReg 0)
360 ra = FixedReg ILIT(26)
362 gp = FixedReg ILIT(29)
363 sp = FixedReg ILIT(30)
364 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
366 t9, t10, t11, t12 :: Reg
374 Intel x86 architecture:
375 - All registers except 7 (esp) are available for use.
376 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
377 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
378 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
379 - Registers 8-15 hold extended floating point values.
383 gReg,fReg :: Int -> Int
387 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
388 eax = realReg (gReg 0)
389 ebx = realReg (gReg 1)
390 ecx = realReg (gReg 2)
391 edx = realReg (gReg 3)
392 esi = realReg (gReg 4)
393 edi = realReg (gReg 5)
394 ebp = realReg (gReg 6)
395 esp = realReg (gReg 7)
396 st0 = realReg (fReg 0)
397 st1 = realReg (fReg 1)
398 st2 = realReg (fReg 2)
399 st3 = realReg (fReg 3)
400 st4 = realReg (fReg 4)
401 st5 = realReg (fReg 5)
402 st6 = realReg (fReg 6)
403 st7 = realReg (fReg 7)
408 The SPARC has 64 registers of interest; 32 integer registers and 32
409 floating point registers. The mapping of STG registers to SPARC
410 machine registers is defined in StgRegs.h. We are, of course,
411 prepared for any eventuality.
414 #if sparc_TARGET_ARCH
416 gReg,lReg,iReg,oReg,fReg :: Int -> Int
424 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
425 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
427 g0, fp, sp, o0, f0 :: Reg
428 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
429 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
430 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
431 o0 = realReg (oReg 0)
432 f0 = realReg (fReg 0)
437 Redefine the literals used for machine-registers with non-numeric
438 names in the header files. Gag me with a spoon, eh?
440 #if alpha_TARGET_ARCH
492 #if sparc_TARGET_ARCH
561 baseRegOffset :: MagicId -> Int
563 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
564 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
565 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
566 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
567 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
568 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
569 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
570 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
571 baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1
572 baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2
573 baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3
574 baseRegOffset (FloatReg ILIT(4)) = OFFSET_F4
575 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_D1
576 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_D2
577 baseRegOffset Sp = OFFSET_Sp
578 baseRegOffset Su = OFFSET_Su
579 baseRegOffset SpLim = OFFSET_SpLim
581 baseRegOffset (LongReg _ ILIT(1)) = OFFSET_Lng1
584 baseRegOffset (LongReg _ ILIT(2)) = OFFSET_Lng2
586 baseRegOffset Hp = OFFSET_Hp
587 baseRegOffset HpLim = OFFSET_HpLim
589 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
590 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
591 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
596 callerSaves :: MagicId -> Bool
598 #ifdef CALLER_SAVES_Base
599 callerSaves BaseReg = True
601 #ifdef CALLER_SAVES_R1
602 callerSaves (VanillaReg _ ILIT(1)) = True
604 #ifdef CALLER_SAVES_R2
605 callerSaves (VanillaReg _ ILIT(2)) = True
607 #ifdef CALLER_SAVES_R3
608 callerSaves (VanillaReg _ ILIT(3)) = True
610 #ifdef CALLER_SAVES_R4
611 callerSaves (VanillaReg _ ILIT(4)) = True
613 #ifdef CALLER_SAVES_R5
614 callerSaves (VanillaReg _ ILIT(5)) = True
616 #ifdef CALLER_SAVES_R6
617 callerSaves (VanillaReg _ ILIT(6)) = True
619 #ifdef CALLER_SAVES_R7
620 callerSaves (VanillaReg _ ILIT(7)) = True
622 #ifdef CALLER_SAVES_R8
623 callerSaves (VanillaReg _ ILIT(8)) = True
625 #ifdef CALLER_SAVES_F1
626 callerSaves (FloatReg ILIT(1)) = True
628 #ifdef CALLER_SAVES_F2
629 callerSaves (FloatReg ILIT(2)) = True
631 #ifdef CALLER_SAVES_F3
632 callerSaves (FloatReg ILIT(3)) = True
634 #ifdef CALLER_SAVES_F4
635 callerSaves (FloatReg ILIT(4)) = True
637 #ifdef CALLER_SAVES_D1
638 callerSaves (DoubleReg ILIT(1)) = True
640 #ifdef CALLER_SAVES_D2
641 callerSaves (DoubleReg ILIT(2)) = True
643 #ifdef CALLER_SAVES_L1
644 callerSaves (LongReg _ ILIT(1)) = True
646 #ifdef CALLER_SAVES_Sp
647 callerSaves Sp = True
649 #ifdef CALLER_SAVES_Su
650 callerSaves Su = True
652 #ifdef CALLER_SAVES_SpLim
653 callerSaves SpLim = True
655 #ifdef CALLER_SAVES_Hp
656 callerSaves Hp = True
658 #ifdef CALLER_SAVES_HpLim
659 callerSaves HpLim = True
661 callerSaves _ = False
665 magicIdRegMaybe :: MagicId -> Maybe Reg
668 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
671 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
674 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
677 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
680 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
683 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
686 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
689 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
692 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
695 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_F1))
698 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_F2))
701 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_F3))
704 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_F4))
707 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_D1))
710 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_D2))
713 magicIdRegMaybe Sp = Just (FixedReg ILIT(REG_Sp))
716 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (FixedReg ILIT(REG_Lng1))
719 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (FixedReg ILIT(REG_Lng2))
722 magicIdRegMaybe Su = Just (FixedReg ILIT(REG_Su))
725 magicIdRegMaybe SpLim = Just (FixedReg ILIT(REG_SpLim))
728 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
731 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
733 magicIdRegMaybe _ = Nothing
736 %************************************************************************
738 \subsection{Free, reserved, call-clobbered, and argument registers}
740 %************************************************************************
742 @freeRegs@ is the list of registers we can use in register allocation.
743 @freeReg@ (below) says if a particular register is free.
745 With a per-instruction clobber list, we might be able to get some of
746 these back, but it's probably not worth the hassle.
748 @callClobberedRegs@ ... the obvious.
750 @argRegs@: assuming a call with N arguments, what registers will be
751 used to hold arguments? (NB: it doesn't know whether the arguments
752 are integer or floating-point...)
755 reservedRegs :: [RegNo]
757 #if alpha_TARGET_ARCH
758 = [NCG_Reserved_I1, NCG_Reserved_I2,
759 NCG_Reserved_F1, NCG_Reserved_F2]
762 = [{-certainly cannot afford any!-}]
764 #if sparc_TARGET_ARCH
765 = [NCG_Reserved_I1, NCG_Reserved_I2,
766 NCG_Reserved_F1, NCG_Reserved_F2,
767 NCG_Reserved_D1, NCG_Reserved_D2]
770 -------------------------------
773 = freeMappedRegs IF_ARCH_alpha( [0..63],
774 IF_ARCH_i386( [0..15],
775 IF_ARCH_sparc( [0..63],)))
777 -------------------------------
778 callClobberedRegs :: [Reg]
781 #if alpha_TARGET_ARCH
782 [0, 1, 2, 3, 4, 5, 6, 7, 8,
783 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
784 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
785 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
786 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
787 #endif {- alpha_TARGET_ARCH -}
790 #endif {- i386_TARGET_ARCH -}
791 #if sparc_TARGET_ARCH
793 [oReg i | i <- [0..5]] ++
794 [gReg i | i <- [1..7]] ++
795 [fReg i | i <- [0..31]] )
796 #endif {- sparc_TARGET_ARCH -}
798 -------------------------------
799 argRegs :: Int -> [Reg]
803 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
805 #if alpha_TARGET_ARCH
806 argRegs 1 = freeMappedRegs [16, fReg 16]
807 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
808 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
809 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
810 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
811 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
812 #endif {- alpha_TARGET_ARCH -}
813 #if sparc_TARGET_ARCH
814 argRegs 1 = freeMappedRegs (map oReg [0])
815 argRegs 2 = freeMappedRegs (map oReg [0,1])
816 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
817 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
818 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
819 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
820 #endif {- sparc_TARGET_ARCH -}
821 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
822 #endif {- i386_TARGET_ARCH -}
824 -------------------------------
826 #if alpha_TARGET_ARCH
827 allArgRegs :: [(Reg, Reg)]
829 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
830 #endif {- alpha_TARGET_ARCH -}
832 #if sparc_TARGET_ARCH
835 allArgRegs = map realReg [oReg i | i <- [0..5]]
836 #endif {- sparc_TARGET_ARCH -}
838 -------------------------------
839 freeMappedRegs :: [Int] -> [Reg]
845 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
849 freeReg :: FAST_INT -> FAST_BOOL
851 #if alpha_TARGET_ARCH
852 freeReg ILIT(26) = _FALSE_ -- return address (ra)
853 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
854 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
855 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
856 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
857 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
861 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
864 #if sparc_TARGET_ARCH
865 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
866 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
867 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
868 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
869 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
870 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
874 freeReg ILIT(REG_Base) = _FALSE_
877 freeReg ILIT(REG_R1) = _FALSE_
880 freeReg ILIT(REG_R2) = _FALSE_
883 freeReg ILIT(REG_R3) = _FALSE_
886 freeReg ILIT(REG_R4) = _FALSE_
889 freeReg ILIT(REG_R5) = _FALSE_
892 freeReg ILIT(REG_R6) = _FALSE_
895 freeReg ILIT(REG_R7) = _FALSE_
898 freeReg ILIT(REG_R8) = _FALSE_
901 freeReg ILIT(REG_F1) = _FALSE_
904 freeReg ILIT(REG_F2) = _FALSE_
907 freeReg ILIT(REG_F3) = _FALSE_
910 freeReg ILIT(REG_F4) = _FALSE_
913 freeReg ILIT(REG_D1) = _FALSE_
916 freeReg ILIT(REG_D2) = _FALSE_
919 freeReg ILIT(REG_Sp) = _FALSE_
922 freeReg ILIT(REG_Su) = _FALSE_
925 freeReg ILIT(REG_SpLim) = _FALSE_
928 freeReg ILIT(REG_Hp) = _FALSE_
931 freeReg ILIT(REG_HpLim) = _FALSE_
934 -- we hang onto two double regs for dedicated
935 -- use; this is not necessary on Alphas and
936 -- may not be on other non-SPARCs.
938 | n _EQ_ (ILIT(REG_D1) _ADD_ ILIT(1)) = _FALSE_
941 | n _EQ_ (ILIT(REG_D2) _ADD_ ILIT(1)) = _FALSE_