2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "HsVersions.h"
14 #include "nativeGen/NCG.h"
47 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
50 , eax, ebx, ecx, edx, esi, esp
51 , st0, st1, st2, st3, st4, st5, st6, st7
56 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
62 #if __GLASGOW_HASKELL__ >= 202
63 import GlaExts hiding (Addr)
69 import AbsCSyn ( MagicId(..) )
70 import AbsCUtils ( magicIdPrimRep )
71 import CLabel ( CLabel )
72 import Outputable ( Outputable(..) )
73 import Pretty ( Doc, text, rational )
74 import PrimOp ( PrimOp(..) )
75 import PrimRep ( PrimRep(..) )
76 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
79 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
80 Unique{-instance Ord3-}, Uniquable(..)
82 import UniqSupply ( getUnique, returnUs, thenUs, SYN_IE(UniqSM) )
83 import Util ( panic, Ord3(..) )
86 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
91 | ImmInteger Integer -- Sigh.
92 | ImmCLbl CLabel -- AbstractC Label (with baggage)
93 | ImmLab Doc -- Simple string label (underscore-able)
94 | ImmLit Doc -- Simple string
96 | LO Imm -- Possible restrictions...
99 strImmLit s = ImmLit (text s)
102 IF_ARCH_alpha({-prepend nothing-}
103 ,IF_ARCH_i386( '0' : 'd' :
104 ,IF_ARCH_sparc('0' : 'r' :,)))
108 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
112 #if alpha_TARGET_ARCH
119 = Addr Base Index Displacement
122 type Base = Maybe Reg
123 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
124 type Displacement = Imm
127 #if sparc_TARGET_ARCH
132 addrOffset :: Addr -> Int -> Maybe Addr
136 #if alpha_TARGET_ARCH
137 _ -> panic "MachMisc.addrOffset not defined for Alpha"
140 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
141 Addr r i (ImmInt n) -> Just (Addr r i (ImmInt (n + off)))
142 Addr r i (ImmInteger n)
143 -> Just (Addr r i (ImmInt (fromInteger (n + toInteger off))))
146 #if sparc_TARGET_ARCH
147 AddrRegImm r (ImmInt n)
148 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
149 | otherwise -> Nothing
152 AddrRegImm r (ImmInteger n)
153 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
154 | otherwise -> Nothing
155 where n2 = n + toInteger off
157 AddrRegReg r (FixedReg ILIT(0))
158 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
159 | otherwise -> Nothing
166 #if alpha_TARGET_ARCH
168 fits8Bits :: Integer -> Bool
169 fits8Bits i = i >= -256 && i < 256
173 #if sparc_TARGET_ARCH
175 fits13Bits :: Int -> Bool
178 fits13Bits :: Integer -> Bool
181 fits13Bits :: Integral a => a -> Bool
182 fits13Bits x = x >= -4096 && x < 4096
186 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
191 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
193 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
194 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
195 The rest are either in real machine registers or stored as offsets
199 data RegLoc = Save StixTree | Always StixTree
202 Trees for register save locations:
204 saveLoc :: MagicId -> StixTree
206 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
210 stgReg :: MagicId -> RegLoc
213 = case (magicIdRegMaybe x) of
214 Just _ -> Save nonReg
215 Nothing -> Always nonReg
217 offset = baseRegOffset x
219 baseLoc = case (magicIdRegMaybe BaseReg) of
220 Just _ -> StReg (StixMagicId BaseReg)
221 Nothing -> sStLitLbl SLIT("MainRegTable")
224 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
225 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
226 BaseReg -> sStLitLbl SLIT("MainRegTable")
227 -- these Hp&HpLim cases perhaps should
228 -- not be here for i386 (???) WDP 96/03
229 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
230 HpLim -> StInd PtrRep (sStLitLbl
231 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
232 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
233 StInt (1*BYTES_PER_WORD)])
235 r2 = VanillaReg PtrRep ILIT(2)
236 infoptr = case (stgReg r2) of
238 Save _ -> StReg (StixMagicId r2)
239 _ -> StInd (magicIdPrimRep x)
240 (StPrim IntAddOp [baseLoc,
241 StInt (toInteger (offset*BYTES_PER_WORD))])
244 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
246 @spRel@ gives us a stack relative addressing mode for volatile
247 temporaries and for excess call arguments. @fpRel@, where
248 applicable, is the same but for the frame pointer.
251 spRel :: Int -- desired stack offset in words, positive or negative
256 = Addr (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
258 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
261 #if sparc_TARGET_ARCH
263 -- Duznae work for offsets greater than 13 bits; we just hope for
266 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
270 %************************************************************************
272 \subsection[Reg]{Real registers}
274 %************************************************************************
276 Static Registers correspond to actual machine registers. These should
277 be avoided until the last possible moment.
279 Dynamic registers are allocated on the fly, usually to represent a single
280 value in the abstract assembly code (i.e. dynamic registers are usually
281 single assignment). Ultimately, they are mapped to available machine
282 registers before spitting out the code.
286 = FixedReg FAST_INT -- A pre-allocated machine register
288 | MappedReg FAST_INT -- A dynamically allocated machine register
290 | MemoryReg Int PrimRep -- A machine "register" actually held in
291 -- a memory allocated table of
292 -- registers which didn't fit in real
295 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
296 -- always mapped to one of the earlier
297 -- two (?) before we're done.
298 mkReg :: Unique -> PrimRep -> Reg
301 getNewRegNCG :: PrimRep -> UniqSM Reg
303 = getUnique `thenUs` \ u ->
304 returnUs (UnmappedReg u pk)
306 instance Text Reg where
307 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
308 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
309 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
310 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
313 instance Outputable Reg where
314 ppr sty r = text (show r)
317 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
318 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
319 cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i'
320 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u'
322 = let tag1 = tagReg r1
325 if tag1 _LT_ tag2 then LT_ else GT_
327 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
328 tagReg (MappedReg _) = ILIT(2)
329 tagReg (MemoryReg _ _) = ILIT(3)
330 tagReg (UnmappedReg _ _) = ILIT(4)
332 cmp_i :: Int -> Int -> TAG_
333 cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_
335 cmp_ihash :: FAST_INT -> FAST_INT -> TAG_
336 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_
338 instance Ord3 Reg where
341 instance Eq Reg where
342 a == b = case (a `cmp` b) of { EQ_ -> True; _ -> False }
343 a /= b = case (a `cmp` b) of { EQ_ -> False; _ -> True }
345 instance Ord Reg where
346 a <= b = case (a `cmp` b) of { LT_ -> True; EQ_ -> True; GT__ -> False }
347 a < b = case (a `cmp` b) of { LT_ -> True; EQ_ -> False; GT__ -> False }
348 a >= b = case (a `cmp` b) of { LT_ -> False; EQ_ -> True; GT__ -> True }
349 a > b = case (a `cmp` b) of { LT_ -> False; EQ_ -> False; GT__ -> True }
350 _tagCmp a b = case (a `cmp` b) of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT }
352 instance Uniquable Reg where
353 uniqueOf (UnmappedReg u _) = u
354 uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i)
355 uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i)
356 uniqueOf (MemoryReg i _) = mkPseudoUnique3 i
362 realReg :: RegNo -> Reg
364 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
366 extractMappedRegNos :: [Reg] -> [RegNo]
368 extractMappedRegNos regs
371 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
372 ex _ acc = acc -- leave it out
375 ** Machine-specific Reg stuff: **
377 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
378 point registers. The mapping of STG registers to alpha machine registers
379 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
381 #if alpha_TARGET_ARCH
385 v0, f0, ra, pv, gp, sp, zeroh :: Reg
387 f0 = realReg (fReg 0)
388 ra = FixedReg ILIT(26)
390 gp = FixedReg ILIT(29)
391 sp = FixedReg ILIT(30)
392 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
394 t9, t10, t11, t12 :: Reg
402 Intel x86 architecture:
403 - All registers except 7 (esp) are available for use.
404 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
405 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
406 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
407 - Registers 8-15 hold extended floating point values.
411 gReg,fReg :: Int -> Int
415 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
416 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
417 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
418 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
419 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
420 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
421 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
422 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
423 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
424 st0 = realReg (fReg 0)
425 st1 = realReg (fReg 1)
426 st2 = realReg (fReg 2)
427 st3 = realReg (fReg 3)
428 st4 = realReg (fReg 4)
429 st5 = realReg (fReg 5)
430 st6 = realReg (fReg 6)
431 st7 = realReg (fReg 7)
436 The SPARC has 64 registers of interest; 32 integer registers and 32
437 floating point registers. The mapping of STG registers to SPARC
438 machine registers is defined in StgRegs.h. We are, of course,
439 prepared for any eventuality.
442 #if sparc_TARGET_ARCH
444 gReg,lReg,iReg,oReg,fReg :: Int -> Int
452 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
453 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
455 g0, fp, sp, o0, f0 :: Reg
456 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
457 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
458 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
459 o0 = realReg (oReg 0)
460 f0 = realReg (fReg 0)
465 Redefine the literals used for machine-registers with non-numeric
466 names in the header files. Gag me with a spoon, eh?
468 #if alpha_TARGET_ARCH
520 #if sparc_TARGET_ARCH
589 baseRegOffset :: MagicId -> Int
591 baseRegOffset StkOReg = OFFSET_StkO
592 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
593 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
594 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
595 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
596 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
597 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
598 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
599 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
600 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
601 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
602 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
603 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
604 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
605 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
606 baseRegOffset TagReg = OFFSET_Tag
607 baseRegOffset RetReg = OFFSET_Ret
608 baseRegOffset SpA = OFFSET_SpA
609 baseRegOffset SuA = OFFSET_SuA
610 baseRegOffset SpB = OFFSET_SpB
611 baseRegOffset SuB = OFFSET_SuB
612 baseRegOffset Hp = OFFSET_Hp
613 baseRegOffset HpLim = OFFSET_HpLim
614 baseRegOffset LivenessReg = OFFSET_Liveness
616 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
617 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
618 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
619 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
620 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
625 callerSaves :: MagicId -> Bool
627 #ifdef CALLER_SAVES_Base
628 callerSaves BaseReg = True
630 #ifdef CALLER_SAVES_StkO
631 callerSaves StkOReg = True
633 #ifdef CALLER_SAVES_R1
634 callerSaves (VanillaReg _ ILIT(1)) = True
636 #ifdef CALLER_SAVES_R2
637 callerSaves (VanillaReg _ ILIT(2)) = True
639 #ifdef CALLER_SAVES_R3
640 callerSaves (VanillaReg _ ILIT(3)) = True
642 #ifdef CALLER_SAVES_R4
643 callerSaves (VanillaReg _ ILIT(4)) = True
645 #ifdef CALLER_SAVES_R5
646 callerSaves (VanillaReg _ ILIT(5)) = True
648 #ifdef CALLER_SAVES_R6
649 callerSaves (VanillaReg _ ILIT(6)) = True
651 #ifdef CALLER_SAVES_R7
652 callerSaves (VanillaReg _ ILIT(7)) = True
654 #ifdef CALLER_SAVES_R8
655 callerSaves (VanillaReg _ ILIT(8)) = True
657 #ifdef CALLER_SAVES_FltReg1
658 callerSaves (FloatReg ILIT(1)) = True
660 #ifdef CALLER_SAVES_FltReg2
661 callerSaves (FloatReg ILIT(2)) = True
663 #ifdef CALLER_SAVES_FltReg3
664 callerSaves (FloatReg ILIT(3)) = True
666 #ifdef CALLER_SAVES_FltReg4
667 callerSaves (FloatReg ILIT(4)) = True
669 #ifdef CALLER_SAVES_DblReg1
670 callerSaves (DoubleReg ILIT(1)) = True
672 #ifdef CALLER_SAVES_DblReg2
673 callerSaves (DoubleReg ILIT(2)) = True
675 #ifdef CALLER_SAVES_Tag
676 callerSaves TagReg = True
678 #ifdef CALLER_SAVES_Ret
679 callerSaves RetReg = True
681 #ifdef CALLER_SAVES_SpA
682 callerSaves SpA = True
684 #ifdef CALLER_SAVES_SuA
685 callerSaves SuA = True
687 #ifdef CALLER_SAVES_SpB
688 callerSaves SpB = True
690 #ifdef CALLER_SAVES_SuB
691 callerSaves SuB = True
693 #ifdef CALLER_SAVES_Hp
694 callerSaves Hp = True
696 #ifdef CALLER_SAVES_HpLim
697 callerSaves HpLim = True
699 #ifdef CALLER_SAVES_Liveness
700 callerSaves LivenessReg = True
702 #ifdef CALLER_SAVES_StdUpdRetVec
703 callerSaves StdUpdRetVecReg = True
705 #ifdef CALLER_SAVES_StkStub
706 callerSaves StkStubReg = True
708 callerSaves _ = False
712 magicIdRegMaybe :: MagicId -> Maybe Reg
715 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
718 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
721 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
724 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
727 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
730 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
733 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
736 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
739 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
742 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
745 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
748 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
751 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
754 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
757 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
760 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
763 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
766 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
769 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
772 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
775 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
778 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
781 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
784 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
787 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
789 #ifdef REG_StdUpdRetVec
790 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
793 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
795 magicIdRegMaybe _ = Nothing
798 %************************************************************************
800 \subsection{Free, reserved, call-clobbered, and argument registers}
802 %************************************************************************
804 @freeRegs@ is the list of registers we can use in register allocation.
805 @freeReg@ (below) says if a particular register is free.
807 With a per-instruction clobber list, we might be able to get some of
808 these back, but it's probably not worth the hassle.
810 @callClobberedRegs@ ... the obvious.
812 @argRegs@: assuming a call with N arguments, what registers will be
813 used to hold arguments? (NB: it doesn't know whether the arguments
814 are integer or floating-point...)
817 reservedRegs :: [RegNo]
819 #if alpha_TARGET_ARCH
820 = [NCG_Reserved_I1, NCG_Reserved_I2,
821 NCG_Reserved_F1, NCG_Reserved_F2]
824 = [{-certainly cannot afford any!-}]
826 #if sparc_TARGET_ARCH
827 = [NCG_Reserved_I1, NCG_Reserved_I2,
828 NCG_Reserved_F1, NCG_Reserved_F2,
829 NCG_Reserved_D1, NCG_Reserved_D2]
832 -------------------------------
835 = freeMappedRegs IF_ARCH_alpha( [0..63],
836 IF_ARCH_i386( [0..15],
837 IF_ARCH_sparc( [0..63],)))
839 -------------------------------
840 callClobberedRegs :: [Reg]
843 #if alpha_TARGET_ARCH
844 [0, 1, 2, 3, 4, 5, 6, 7, 8,
845 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
846 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
847 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
848 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
849 #endif {- alpha_TARGET_ARCH -}
852 #endif {- i386_TARGET_ARCH -}
853 #if sparc_TARGET_ARCH
855 [oReg i | i <- [0..5]] ++
856 [gReg i | i <- [1..7]] ++
857 [fReg i | i <- [0..31]] )
858 #endif {- sparc_TARGET_ARCH -}
860 -------------------------------
861 argRegs :: Int -> [Reg]
864 #if alpha_TARGET_ARCH
865 argRegs 1 = freeMappedRegs [16, fReg 16]
866 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
867 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
868 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
869 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
870 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
871 #endif {- alpha_TARGET_ARCH -}
873 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
874 #endif {- i386_TARGET_ARCH -}
875 #if sparc_TARGET_ARCH
876 argRegs 1 = freeMappedRegs (map oReg [0])
877 argRegs 2 = freeMappedRegs (map oReg [0,1])
878 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
879 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
880 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
881 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
882 #endif {- sparc_TARGET_ARCH -}
883 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
885 -------------------------------
887 #if alpha_TARGET_ARCH
888 allArgRegs :: [(Reg, Reg)]
890 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
891 #endif {- alpha_TARGET_ARCH -}
893 #if sparc_TARGET_ARCH
896 allArgRegs = map realReg [oReg i | i <- [0..5]]
897 #endif {- sparc_TARGET_ARCH -}
899 -------------------------------
900 freeMappedRegs :: [Int] -> [Reg]
906 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
910 freeReg :: FAST_INT -> FAST_BOOL
912 #if alpha_TARGET_ARCH
913 freeReg ILIT(26) = _FALSE_ -- return address (ra)
914 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
915 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
916 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
917 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
918 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
922 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
925 #if sparc_TARGET_ARCH
926 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
927 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
928 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
929 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
930 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
931 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
935 freeReg ILIT(REG_Base) = _FALSE_
938 freeReg ILIT(REG_StkO) = _FALSE_
941 freeReg ILIT(REG_R1) = _FALSE_
944 freeReg ILIT(REG_R2) = _FALSE_
947 freeReg ILIT(REG_R3) = _FALSE_
950 freeReg ILIT(REG_R4) = _FALSE_
953 freeReg ILIT(REG_R5) = _FALSE_
956 freeReg ILIT(REG_R6) = _FALSE_
959 freeReg ILIT(REG_R7) = _FALSE_
962 freeReg ILIT(REG_R8) = _FALSE_
965 freeReg ILIT(REG_Flt1) = _FALSE_
968 freeReg ILIT(REG_Flt2) = _FALSE_
971 freeReg ILIT(REG_Flt3) = _FALSE_
974 freeReg ILIT(REG_Flt4) = _FALSE_
977 freeReg ILIT(REG_Dbl1) = _FALSE_
980 freeReg ILIT(REG_Dbl2) = _FALSE_
983 freeReg ILIT(REG_Tag) = _FALSE_
986 freeReg ILIT(REG_Ret) = _FALSE_
989 freeReg ILIT(REG_SpA) = _FALSE_
992 freeReg ILIT(REG_SuA) = _FALSE_
995 freeReg ILIT(REG_SpB) = _FALSE_
998 freeReg ILIT(REG_SuB) = _FALSE_
1001 freeReg ILIT(REG_Hp) = _FALSE_
1004 freeReg ILIT(REG_HpLim) = _FALSE_
1007 freeReg ILIT(REG_Liveness) = _FALSE_
1009 #ifdef REG_StdUpdRetVec
1010 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1013 freeReg ILIT(REG_StkStub) = _FALSE_
1017 -- we hang onto two double regs for dedicated
1018 -- use; this is not necessary on Alphas and
1019 -- may not be on other non-SPARCs.
1021 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1024 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1026 | otherwise = _TRUE_