1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
47 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
56 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
57 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
59 #if powerpc_TARGET_ARCH
68 #include "HsVersions.h"
71 # define STOLEN_X86_REGS 4
72 -- HACK: go for the max
75 #include "../includes/MachRegs.h"
78 import MachOp ( MachRep(..) )
80 import CLabel ( CLabel, mkMainCapabilityLabel )
81 import Unique ( Unique )
83 import Outputable ( Outputable(..), pprPanic, panic )
84 import qualified Outputable
89 #if powerpc_TARGET_ARCH
90 #if __GLASGOW_HASKELL__ >= 504
91 import Data.Word ( Word8, Word16, Word32 )
92 import Data.Int ( Int8, Int16, Int32 )
94 import Word ( Word8, Word16, Word32 )
95 import Int ( Int8, Int16, Int32 )
99 -- -----------------------------------------------------------------------------
104 | ImmInteger Integer -- Sigh.
105 | ImmCLbl CLabel -- AbstractC Label (with baggage)
106 | ImmLit Doc -- Simple string
107 | ImmIndex CLabel Int
110 #if sparc_TARGET_ARCH
111 | LO Imm {- Possible restrictions... -}
114 #if powerpc_TARGET_ARCH
117 | HA Imm {- high halfword adjusted -}
119 -- special dyld (dynamic linker) things
120 | ImmDyldNonLazyPtr CLabel -- Llabel$non_lazy_ptr
123 strImmLit s = ImmLit (text s)
125 litToImm :: CmmLit -> Imm
126 litToImm (CmmInt i _) = ImmInteger i
127 litToImm (CmmFloat f F32) = ImmFloat f
128 litToImm (CmmFloat f F64) = ImmDouble f
129 litToImm (CmmLabel l) = ImmCLbl l
130 litToImm (CmmLabelOff l off) = ImmIndex l off
132 -- -----------------------------------------------------------------------------
136 #if alpha_TARGET_ARCH
143 = AddrBaseIndex Base Index Displacement
146 type Base = Maybe Reg
147 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
148 type Displacement = Imm
151 #if sparc_TARGET_ARCH
156 #if powerpc_TARGET_ARCH
162 addrModeRegs :: AddrMode -> [Reg]
163 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
165 b_regs = case b of { Just r -> [r]; _ -> [] }
166 i_regs = case i of { Just (r,_) -> [r]; _ -> [] }
171 addrOffset :: AddrMode -> Int -> Maybe AddrMode
175 #if alpha_TARGET_ARCH
176 _ -> panic "MachMisc.addrOffset not defined for Alpha"
179 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
181 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
182 AddrBaseIndex r i (ImmInteger n)
183 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
185 AddrBaseIndex r i (ImmCLbl lbl)
186 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
188 AddrBaseIndex r i (ImmIndex lbl ix)
189 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
191 _ -> Nothing -- in theory, shouldn't happen
193 #if sparc_TARGET_ARCH
194 AddrRegImm r (ImmInt n)
195 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
196 | otherwise -> Nothing
199 AddrRegImm r (ImmInteger n)
200 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
201 | otherwise -> Nothing
202 where n2 = n + toInteger off
204 AddrRegReg r (RealReg 0)
205 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
206 | otherwise -> Nothing
210 #if powerpc_TARGET_ARCH
211 AddrRegImm r (ImmInt n)
212 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
213 | otherwise -> Nothing
216 AddrRegImm r (ImmInteger n)
217 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
218 | otherwise -> Nothing
219 where n2 = n + toInteger off
225 #if alpha_TARGET_ARCH
227 fits8Bits :: Integer -> Bool
228 fits8Bits i = i >= -256 && i < 256
232 #if sparc_TARGET_ARCH
234 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
235 fits13Bits :: Integral a => a -> Bool
236 fits13Bits x = x >= -4096 && x < 4096
240 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
241 ++show i++");\nprobably because of large constant data structures;" ++
242 "\nworkaround: use -fvia-C on this module.\n")
246 #if powerpc_TARGET_ARCH
247 fits16Bits :: Integral a => a -> Bool
248 fits16Bits x = x >= -32768 && x < 32768
250 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
252 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
254 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
255 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
256 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
257 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
258 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
259 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
261 narrowed = narrow rep signed
264 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
265 | otherwise = Nothing
267 | narrowed >= 0 && narrowed < 65536 = Just narrowed
268 | otherwise = Nothing
269 toI16 _ _ = Just narrowed
273 -- @spRel@ gives us a stack relative addressing mode for volatile
274 -- temporaries and for excess call arguments. @fpRel@, where
275 -- applicable, is the same but for the frame pointer.
277 spRel :: Int -- desired stack offset in words, positive or negative
282 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * wORD_SIZE))
284 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
287 #if sparc_TARGET_ARCH
288 fpRel :: Int -> AddrMode
289 -- Duznae work for offsets greater than 13 bits; we just hope for
292 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
296 -- -----------------------------------------------------------------------------
299 -- We map STG registers onto appropriate CmmExprs. Either they map
300 -- to real machine registers or stored as offsets from BaseReg. Given
301 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
302 -- register it is in, on this platform, or a StixExpr denoting the
303 -- address in the register table holding it. get_MagicId_addr always
304 -- produces the register table address for it.
306 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
307 get_GlobalReg_addr :: GlobalReg -> CmmExpr
308 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
310 get_GlobalReg_reg_or_addr mid
311 = case globalRegMaybe mid of
313 Nothing -> Right (get_GlobalReg_addr mid)
315 get_GlobalReg_addr BaseReg = regTableOffset 0
316 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
317 (globalRegRep mid) (baseRegOffset mid)
319 -- Calculate a literal representing an offset into the register table.
320 -- Used when we don't have an actual BaseReg to offset from.
322 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
324 get_Regtable_addr_from_offset rep offset
325 = case globalRegMaybe BaseReg of
326 Nothing -> regTableOffset offset
327 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
329 -- ---------------------------------------------------------------------------
332 -- RealRegs are machine regs which are available for allocation, in
333 -- the usual way. We know what class they are, because that's part of
334 -- the processor's architecture.
336 -- VirtualRegs are virtual registers. The register allocator will
337 -- eventually have to map them into RealRegs, or into spill slots.
338 -- VirtualRegs are allocated on the fly, usually to represent a single
339 -- value in the abstract assembly code (i.e. dynamic registers are
340 -- usually single assignment). With the new register allocator, the
341 -- single assignment restriction isn't necessary to get correct code,
342 -- although a better register allocation will result if single
343 -- assignment is used -- because the allocator maps a VirtualReg into
344 -- a single RealReg, even if the VirtualReg has multiple live ranges.
346 -- Virtual regs can be of either class, so that info is attached.
348 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
349 -- when supplied with the vreg for the lower-half of the quantity.
350 -- (NB. Not reversible).
351 getHiVRegFromLo (VirtualRegI u)
352 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
353 getHiVRegFromLo other
354 = pprPanic "getHiVRegFromLo" (ppr other)
365 = RealReg {-# UNPACK #-} !RegNo
366 | VirtualRegI {-# UNPACK #-} !Unique
367 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
368 | VirtualRegF {-# UNPACK #-} !Unique
369 | VirtualRegD {-# UNPACK #-} !Unique
372 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
373 -- in the register allocator.
374 instance Uniquable Reg where
375 getUnique (RealReg i) = mkUnique 'C' i
376 getUnique (VirtualRegI u) = u
377 getUnique (VirtualRegHi u) = u
378 getUnique (VirtualRegF u) = u
379 getUnique (VirtualRegD u) = u
381 mkVReg :: Unique -> MachRep -> Reg
384 #if sparc_TARGET_ARCH
390 other -> VirtualRegI u
392 isVirtualReg :: Reg -> Bool
393 isVirtualReg (RealReg _) = False
394 isVirtualReg (VirtualRegI _) = True
395 isVirtualReg (VirtualRegHi _) = True
396 isVirtualReg (VirtualRegF _) = True
397 isVirtualReg (VirtualRegD _) = True
399 isRealReg :: Reg -> Bool
400 isRealReg = not . isVirtualReg
402 instance Show Reg where
403 show (RealReg i) = showReg i
404 show (VirtualRegI u) = "%vI_" ++ show u
405 show (VirtualRegHi u) = "%vHi_" ++ show u
406 show (VirtualRegF u) = "%vF_" ++ show u
407 show (VirtualRegD u) = "%vD_" ++ show u
409 instance Outputable Reg where
410 ppr r = Outputable.text (show r)
413 -- -----------------------------------------------------------------------------
414 -- Machine-specific register stuff
416 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
417 -- point registers. The mapping of STG registers to alpha machine registers
418 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
420 #if alpha_TARGET_ARCH
424 v0, f0, ra, pv, gp, sp, zeroh :: Reg
426 f0 = realReg (fReg 0)
427 ra = FixedReg ILIT(26)
429 gp = FixedReg ILIT(29)
430 sp = FixedReg ILIT(30)
431 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
433 t9, t10, t11, t12 :: Reg
441 Intel x86 architecture:
442 - All registers except 7 (esp) are available for use.
443 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
444 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
445 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
446 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
447 fp registers, and 3-operand insns for them, and we translate this into
448 real stack-based x86 fp code after register allocation.
450 The fp registers are all Double registers; we don't have any RcFloat class
451 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
457 fake0, fake1, fake2, fake3, fake4, fake5,
458 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
474 -- On x86, we might want to have an 8-bit RegClass, which would
475 -- contain just regs 1-4 (the others don't have 8-bit versions).
476 -- However, we can get away without this at the moment because the
477 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
478 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
479 regClass (VirtualRegI u) = RcInteger
480 regClass (VirtualRegHi u) = RcInteger
481 regClass (VirtualRegD u) = RcDouble
482 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
483 (ppr (VirtualRegF u))
486 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
487 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
489 showReg :: RegNo -> String
491 = if n >= 0 && n < 14
493 else "%unknown_x86_real_reg_" ++ show n
498 The SPARC has 64 registers of interest; 32 integer registers and 32
499 floating point registers. The mapping of STG registers to SPARC
500 machine registers is defined in StgRegs.h. We are, of course,
501 prepared for any eventuality.
503 The whole fp-register pairing thing on sparcs is a huge nuisance. See
504 fptools/ghc/includes/MachRegs.h for a description of what's going on
508 #if sparc_TARGET_ARCH
510 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
517 nCG_FirstFloatReg :: RegNo
518 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
520 regClass (VirtualRegI u) = RcInteger
521 regClass (VirtualRegF u) = RcFloat
522 regClass (VirtualRegD u) = RcDouble
523 regClass (RealReg i) | i < 32 = RcInteger
524 | i < nCG_FirstFloatReg = RcDouble
525 | otherwise = RcFloat
527 showReg :: RegNo -> String
529 | n >= 0 && n < 8 = "%g" ++ show n
530 | n >= 8 && n < 16 = "%o" ++ show (n-8)
531 | n >= 16 && n < 24 = "%l" ++ show (n-16)
532 | n >= 24 && n < 32 = "%i" ++ show (n-24)
533 | n >= 32 && n < 64 = "%f" ++ show (n-32)
534 | otherwise = "%unknown_sparc_real_reg_" ++ show n
536 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
538 f6 = RealReg (fReg 6)
539 f8 = RealReg (fReg 8)
540 f22 = RealReg (fReg 22)
541 f26 = RealReg (fReg 26)
542 f27 = RealReg (fReg 27)
545 -- g0 is useful for codegen; is always zero, and writes to it vanish.
546 g0 = RealReg (gReg 0)
547 g1 = RealReg (gReg 1)
548 g2 = RealReg (gReg 2)
550 -- FP, SP, int and float return (from C) regs.
551 fp = RealReg (iReg 6)
552 sp = RealReg (oReg 6)
553 o0 = RealReg (oReg 0)
554 o1 = RealReg (oReg 1)
555 f0 = RealReg (fReg 0)
556 f1 = RealReg (fReg 1)
561 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
565 #if powerpc_TARGET_ARCH
569 regClass (VirtualRegI u) = RcInteger
570 regClass (VirtualRegHi u) = RcInteger
571 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
572 (ppr (VirtualRegF u))
573 regClass (VirtualRegD u) = RcDouble
574 regClass (RealReg i) | i < 32 = RcInteger
575 | otherwise = RcDouble
577 showReg :: RegNo -> String
579 | n >= 0 && n <= 31 = "%r" ++ show n
580 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
581 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
588 f1 = RealReg $ fReg 1
589 f20 = RealReg $ fReg 20
590 f21 = RealReg $ fReg 21
594 Redefine the literals used for machine-registers with non-numeric
595 names in the header files. Gag me with a spoon, eh?
598 #if alpha_TARGET_ARCH
648 #if sparc_TARGET_ARCH
716 #if powerpc_TARGET_ARCH
750 #ifdef darwin_TARGET_OS
820 -- allMachRegs is the complete set of machine regs.
821 allMachRegNos :: [RegNo]
823 = IF_ARCH_alpha( [0..63],
824 IF_ARCH_i386( [0..13],
825 IF_ARCH_sparc( ([0..31]
826 ++ [f0,f2 .. nCG_FirstFloatReg-1]
827 ++ [nCG_FirstFloatReg .. f31]),
828 IF_ARCH_powerpc([0..63],
831 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
832 -- i.e., these are the regs for which we are prepared to allow the
833 -- register allocator to attempt to map VRegs to.
834 allocatableRegs :: [RegNo]
836 = let isFree i = isFastTrue (freeReg i)
837 in filter isFree allMachRegNos
839 -- these are the regs which we cannot assume stay alive over a
841 callClobberedRegs :: [Reg]
844 #if alpha_TARGET_ARCH
845 [0, 1, 2, 3, 4, 5, 6, 7, 8,
846 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
847 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
848 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
849 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
850 #endif /* alpha_TARGET_ARCH */
852 -- caller-saves registers
853 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
854 #endif /* i386_TARGET_ARCH */
855 #if sparc_TARGET_ARCH
858 [oReg i | i <- [0..5]] ++
859 [gReg i | i <- [1..7]] ++
860 [fReg i | i <- [0..31]] )
861 #endif /* sparc_TARGET_ARCH */
862 #if powerpc_TARGET_ARCH
864 map RealReg (0:[2..12] ++ map fReg [0..13])
865 #elif linux_TARGET_OS
866 map RealReg (0:[2..13] ++ map fReg [0..13])
868 #endif /* powerpc_TARGET_ARCH */
871 -- argRegs is the set of regs which are read for an n-argument call to C.
872 -- For archs which pass all args on the stack (x86), is empty.
873 -- Sparc passes up to the first 6 args in regs.
874 -- Dunno about Alpha.
875 argRegs :: RegNo -> [Reg]
878 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
881 #if alpha_TARGET_ARCH
883 argRegs 1 = freeMappedRegs [16, fReg 16]
884 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
885 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
886 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
887 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
888 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
889 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
890 #endif /* alpha_TARGET_ARCH */
892 #if sparc_TARGET_ARCH
894 argRegs 1 = map (RealReg . oReg) [0]
895 argRegs 2 = map (RealReg . oReg) [0,1]
896 argRegs 3 = map (RealReg . oReg) [0,1,2]
897 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
898 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
899 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
900 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
901 #endif /* sparc_TARGET_ARCH */
903 #if powerpc_TARGET_ARCH
905 argRegs 1 = map RealReg [3]
906 argRegs 2 = map RealReg [3,4]
907 argRegs 3 = map RealReg [3..5]
908 argRegs 4 = map RealReg [3..6]
909 argRegs 5 = map RealReg [3..7]
910 argRegs 6 = map RealReg [3..8]
911 argRegs 7 = map RealReg [3..9]
912 argRegs 8 = map RealReg [3..10]
913 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
914 #endif /* powerpc_TARGET_ARCH */
917 -- all of the arg regs ??
918 #if alpha_TARGET_ARCH
919 allArgRegs :: [(Reg, Reg)]
920 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
921 #endif /* alpha_TARGET_ARCH */
923 #if sparc_TARGET_ARCH
925 allArgRegs = map RealReg [oReg i | i <- [0..5]]
926 #endif /* sparc_TARGET_ARCH */
930 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
933 #if powerpc_TARGET_ARCH
935 allArgRegs = map RealReg [3..10]
936 allFPArgRegs :: [Reg]
938 allFPArgRegs = map (RealReg . fReg) [1..13]
939 #elif linux_TARGET_OS
940 allFPArgRegs = map (RealReg . fReg) [1..8]
942 #endif /* powerpc_TARGET_ARCH */
946 freeReg :: RegNo -> FastBool
948 #if alpha_TARGET_ARCH
949 freeReg 26 = fastBool False -- return address (ra)
950 freeReg 28 = fastBool False -- reserved for the assembler (at)
951 freeReg 29 = fastBool False -- global pointer (gp)
952 freeReg 30 = fastBool False -- stack pointer (sp)
953 freeReg 31 = fastBool False -- always zero (zeroh)
954 freeReg 63 = fastBool False -- always zero (f31)
958 freeReg esp = fastBool False -- %esp is the C stack pointer
961 #if sparc_TARGET_ARCH
962 freeReg g0 = fastBool False -- %g0 is always 0.
963 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
964 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
965 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
966 freeReg i6 = fastBool False -- %i6 is our frame pointer.
967 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
968 freeReg o6 = fastBool False -- %o6 is our stack pointer.
969 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
970 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
971 freeReg f1 = fastBool False
974 #if powerpc_TARGET_ARCH
975 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
976 freeReg 1 = fastBool False -- The Stack Pointer
977 #if !darwin_TARGET_OS
978 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
979 freeReg 2 = fastBool False
984 freeReg REG_Base = fastBool False
987 freeReg REG_R1 = fastBool False
990 freeReg REG_R2 = fastBool False
993 freeReg REG_R3 = fastBool False
996 freeReg REG_R4 = fastBool False
999 freeReg REG_R5 = fastBool False
1002 freeReg REG_R6 = fastBool False
1005 freeReg REG_R7 = fastBool False
1008 freeReg REG_R8 = fastBool False
1011 freeReg REG_F1 = fastBool False
1014 freeReg REG_F2 = fastBool False
1017 freeReg REG_F3 = fastBool False
1020 freeReg REG_F4 = fastBool False
1023 freeReg REG_D1 = fastBool False
1026 freeReg REG_D2 = fastBool False
1029 freeReg REG_Sp = fastBool False
1032 freeReg REG_Su = fastBool False
1035 freeReg REG_SpLim = fastBool False
1038 freeReg REG_Hp = fastBool False
1041 freeReg REG_HpLim = fastBool False
1043 freeReg n = fastBool True
1046 -- -----------------------------------------------------------------------------
1047 -- Information about global registers
1049 baseRegOffset :: GlobalReg -> Int
1051 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1052 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1053 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1054 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1055 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1056 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1057 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1058 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1059 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1060 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1061 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1062 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1063 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1064 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1065 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1066 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1067 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1068 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1069 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1070 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1071 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1072 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1073 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1074 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1075 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1076 baseRegOffset GCFun = oFFSET_stgGCFun
1078 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1079 baseRegOffset _ = panic "baseRegOffset:other"
1083 -- | Returns 'True' if this global register is stored in a caller-saves
1084 -- machine register.
1086 callerSaves :: GlobalReg -> Bool
1088 #ifdef CALLER_SAVES_Base
1089 callerSaves BaseReg = True
1091 #ifdef CALLER_SAVES_R1
1092 callerSaves (VanillaReg _ ILIT(1)) = True
1094 #ifdef CALLER_SAVES_R2
1095 callerSaves (VanillaReg _ ILIT(2)) = True
1097 #ifdef CALLER_SAVES_R3
1098 callerSaves (VanillaReg _ ILIT(3)) = True
1100 #ifdef CALLER_SAVES_R4
1101 callerSaves (VanillaReg _ ILIT(4)) = True
1103 #ifdef CALLER_SAVES_R5
1104 callerSaves (VanillaReg _ ILIT(5)) = True
1106 #ifdef CALLER_SAVES_R6
1107 callerSaves (VanillaReg _ ILIT(6)) = True
1109 #ifdef CALLER_SAVES_R7
1110 callerSaves (VanillaReg _ ILIT(7)) = True
1112 #ifdef CALLER_SAVES_R8
1113 callerSaves (VanillaReg _ ILIT(8)) = True
1115 #ifdef CALLER_SAVES_F1
1116 callerSaves (FloatReg 1#) = True
1118 #ifdef CALLER_SAVES_F2
1119 callerSaves (FloatReg 2#) = True
1121 #ifdef CALLER_SAVES_F3
1122 callerSaves (FloatReg 3#) = True
1124 #ifdef CALLER_SAVES_F4
1125 callerSaves (FloatReg 4#) = True
1127 #ifdef CALLER_SAVES_D1
1128 callerSaves (DoubleReg 1#) = True
1130 #ifdef CALLER_SAVES_D2
1131 callerSaves (DoubleReg 2#) = True
1133 #ifdef CALLER_SAVES_L1
1134 callerSaves (LongReg _ ILIT(1)) = True
1136 #ifdef CALLER_SAVES_Sp
1137 callerSaves Sp = True
1139 #ifdef CALLER_SAVES_SpLim
1140 callerSaves SpLim = True
1142 #ifdef CALLER_SAVES_Hp
1143 callerSaves Hp = True
1145 #ifdef CALLER_SAVES_HpLim
1146 callerSaves HpLim = True
1148 #ifdef CALLER_SAVES_CurrentTSO
1149 callerSaves CurrentTSO = True
1151 #ifdef CALLER_SAVES_CurrentNursery
1152 callerSaves CurrentNursery = True
1154 callerSaves _ = False
1157 -- | Returns 'Nothing' if this global register is not stored
1158 -- in a real machine register, otherwise returns @'Just' reg@, where
1159 -- reg is the machine register it is stored in.
1161 globalRegMaybe :: GlobalReg -> Maybe Reg
1164 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1167 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1170 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1173 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1176 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1179 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1182 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1185 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1188 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1191 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1194 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1197 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1200 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1203 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1206 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1209 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1212 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1215 globalRegMaybe Sp = Just (RealReg REG_Sp)
1218 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1221 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1224 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1227 globalRegMaybe Hp = Just (RealReg REG_Hp)
1230 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1232 #ifdef REG_CurrentTSO
1233 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1235 #ifdef REG_CurrentNursery
1236 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1238 globalRegMaybe _ = Nothing