1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
47 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
50 eax, ebx, ecx, edx, esi, edi, ebp, esp,
51 fake0, fake1, fake2, fake3, fake4, fake5,
56 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
57 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
59 #if powerpc_TARGET_ARCH
68 #include "HsVersions.h"
71 # define STOLEN_X86_REGS 4
72 -- HACK: go for the max
75 #include "../includes/MachRegs.h"
78 import MachOp ( MachRep(..) )
80 import CLabel ( CLabel, mkMainCapabilityLabel )
81 import Unique ( Unique )
83 import Outputable ( Outputable(..), pprPanic, panic )
84 import qualified Outputable
89 #if powerpc_TARGET_ARCH
90 #if __GLASGOW_HASKELL__ >= 504
91 import Data.Word ( Word8, Word16, Word32 )
92 import Data.Int ( Int8, Int16, Int32 )
94 import Word ( Word8, Word16, Word32 )
95 import Int ( Int8, Int16, Int32 )
99 -- -----------------------------------------------------------------------------
104 | ImmInteger Integer -- Sigh.
105 | ImmCLbl CLabel -- AbstractC Label (with baggage)
106 | ImmLit Doc -- Simple string
107 | ImmIndex CLabel Int
110 | ImmConstantSum Imm Imm
111 | ImmConstantDiff Imm Imm
112 #if sparc_TARGET_ARCH
113 | LO Imm {- Possible restrictions... -}
116 #if powerpc_TARGET_ARCH
119 | HA Imm {- high halfword adjusted -}
121 strImmLit s = ImmLit (text s)
123 litToImm :: CmmLit -> Imm
124 litToImm (CmmInt i _) = ImmInteger i
125 litToImm (CmmFloat f F32) = ImmFloat f
126 litToImm (CmmFloat f F64) = ImmDouble f
127 litToImm (CmmLabel l) = ImmCLbl l
128 litToImm (CmmLabelOff l off) = ImmIndex l off
129 litToImm (CmmLabelDiffOff l1 l2 off)
131 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
134 -- -----------------------------------------------------------------------------
138 #if alpha_TARGET_ARCH
145 = AddrBaseIndex Base Index Displacement
148 type Base = Maybe Reg
149 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
150 type Displacement = Imm
153 #if sparc_TARGET_ARCH
158 #if powerpc_TARGET_ARCH
164 addrModeRegs :: AddrMode -> [Reg]
165 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
167 b_regs = case b of { Just r -> [r]; _ -> [] }
168 i_regs = case i of { Just (r,_) -> [r]; _ -> [] }
173 addrOffset :: AddrMode -> Int -> Maybe AddrMode
177 #if alpha_TARGET_ARCH
178 _ -> panic "MachMisc.addrOffset not defined for Alpha"
181 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
183 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
184 AddrBaseIndex r i (ImmInteger n)
185 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
187 AddrBaseIndex r i (ImmCLbl lbl)
188 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
190 AddrBaseIndex r i (ImmIndex lbl ix)
191 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
193 _ -> Nothing -- in theory, shouldn't happen
195 #if sparc_TARGET_ARCH
196 AddrRegImm r (ImmInt n)
197 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
198 | otherwise -> Nothing
201 AddrRegImm r (ImmInteger n)
202 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
203 | otherwise -> Nothing
204 where n2 = n + toInteger off
206 AddrRegReg r (RealReg 0)
207 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
208 | otherwise -> Nothing
212 #if powerpc_TARGET_ARCH
213 AddrRegImm r (ImmInt n)
214 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
215 | otherwise -> Nothing
218 AddrRegImm r (ImmInteger n)
219 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
220 | otherwise -> Nothing
221 where n2 = n + toInteger off
227 #if alpha_TARGET_ARCH
229 fits8Bits :: Integer -> Bool
230 fits8Bits i = i >= -256 && i < 256
234 #if sparc_TARGET_ARCH
236 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
237 fits13Bits :: Integral a => a -> Bool
238 fits13Bits x = x >= -4096 && x < 4096
242 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
243 ++show i++");\nprobably because of large constant data structures;" ++
244 "\nworkaround: use -fvia-C on this module.\n")
248 #if powerpc_TARGET_ARCH
249 fits16Bits :: Integral a => a -> Bool
250 fits16Bits x = x >= -32768 && x < 32768
252 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
254 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
256 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
257 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
258 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
259 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
260 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
261 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
263 narrowed = narrow rep signed
266 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
267 | otherwise = Nothing
269 | narrowed >= 0 && narrowed < 65536 = Just narrowed
270 | otherwise = Nothing
271 toI16 _ _ = Just narrowed
275 -- @spRel@ gives us a stack relative addressing mode for volatile
276 -- temporaries and for excess call arguments. @fpRel@, where
277 -- applicable, is the same but for the frame pointer.
279 spRel :: Int -- desired stack offset in words, positive or negative
284 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * wORD_SIZE))
286 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
289 #if sparc_TARGET_ARCH
290 fpRel :: Int -> AddrMode
291 -- Duznae work for offsets greater than 13 bits; we just hope for
294 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
298 -- -----------------------------------------------------------------------------
301 -- We map STG registers onto appropriate CmmExprs. Either they map
302 -- to real machine registers or stored as offsets from BaseReg. Given
303 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
304 -- register it is in, on this platform, or a StixExpr denoting the
305 -- address in the register table holding it. get_MagicId_addr always
306 -- produces the register table address for it.
308 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
309 get_GlobalReg_addr :: GlobalReg -> CmmExpr
310 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
312 get_GlobalReg_reg_or_addr mid
313 = case globalRegMaybe mid of
315 Nothing -> Right (get_GlobalReg_addr mid)
317 get_GlobalReg_addr BaseReg = regTableOffset 0
318 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
319 (globalRegRep mid) (baseRegOffset mid)
321 -- Calculate a literal representing an offset into the register table.
322 -- Used when we don't have an actual BaseReg to offset from.
324 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
326 get_Regtable_addr_from_offset rep offset
327 = case globalRegMaybe BaseReg of
328 Nothing -> regTableOffset offset
329 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
331 -- ---------------------------------------------------------------------------
334 -- RealRegs are machine regs which are available for allocation, in
335 -- the usual way. We know what class they are, because that's part of
336 -- the processor's architecture.
338 -- VirtualRegs are virtual registers. The register allocator will
339 -- eventually have to map them into RealRegs, or into spill slots.
340 -- VirtualRegs are allocated on the fly, usually to represent a single
341 -- value in the abstract assembly code (i.e. dynamic registers are
342 -- usually single assignment). With the new register allocator, the
343 -- single assignment restriction isn't necessary to get correct code,
344 -- although a better register allocation will result if single
345 -- assignment is used -- because the allocator maps a VirtualReg into
346 -- a single RealReg, even if the VirtualReg has multiple live ranges.
348 -- Virtual regs can be of either class, so that info is attached.
350 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
351 -- when supplied with the vreg for the lower-half of the quantity.
352 -- (NB. Not reversible).
353 getHiVRegFromLo (VirtualRegI u)
354 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
355 getHiVRegFromLo other
356 = pprPanic "getHiVRegFromLo" (ppr other)
367 = RealReg {-# UNPACK #-} !RegNo
368 | VirtualRegI {-# UNPACK #-} !Unique
369 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
370 | VirtualRegF {-# UNPACK #-} !Unique
371 | VirtualRegD {-# UNPACK #-} !Unique
374 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
375 -- in the register allocator.
376 instance Uniquable Reg where
377 getUnique (RealReg i) = mkUnique 'C' i
378 getUnique (VirtualRegI u) = u
379 getUnique (VirtualRegHi u) = u
380 getUnique (VirtualRegF u) = u
381 getUnique (VirtualRegD u) = u
383 mkVReg :: Unique -> MachRep -> Reg
386 #if sparc_TARGET_ARCH
392 other -> VirtualRegI u
394 isVirtualReg :: Reg -> Bool
395 isVirtualReg (RealReg _) = False
396 isVirtualReg (VirtualRegI _) = True
397 isVirtualReg (VirtualRegHi _) = True
398 isVirtualReg (VirtualRegF _) = True
399 isVirtualReg (VirtualRegD _) = True
401 isRealReg :: Reg -> Bool
402 isRealReg = not . isVirtualReg
404 instance Show Reg where
405 show (RealReg i) = showReg i
406 show (VirtualRegI u) = "%vI_" ++ show u
407 show (VirtualRegHi u) = "%vHi_" ++ show u
408 show (VirtualRegF u) = "%vF_" ++ show u
409 show (VirtualRegD u) = "%vD_" ++ show u
411 instance Outputable Reg where
412 ppr r = Outputable.text (show r)
415 -- -----------------------------------------------------------------------------
416 -- Machine-specific register stuff
418 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
419 -- point registers. The mapping of STG registers to alpha machine registers
420 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
422 #if alpha_TARGET_ARCH
426 v0, f0, ra, pv, gp, sp, zeroh :: Reg
428 f0 = realReg (fReg 0)
429 ra = FixedReg ILIT(26)
431 gp = FixedReg ILIT(29)
432 sp = FixedReg ILIT(30)
433 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
435 t9, t10, t11, t12 :: Reg
443 Intel x86 architecture:
444 - All registers except 7 (esp) are available for use.
445 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
446 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
447 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
448 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
449 fp registers, and 3-operand insns for them, and we translate this into
450 real stack-based x86 fp code after register allocation.
452 The fp registers are all Double registers; we don't have any RcFloat class
453 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
459 fake0, fake1, fake2, fake3, fake4, fake5,
460 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
476 -- On x86, we might want to have an 8-bit RegClass, which would
477 -- contain just regs 1-4 (the others don't have 8-bit versions).
478 -- However, we can get away without this at the moment because the
479 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
480 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
481 regClass (VirtualRegI u) = RcInteger
482 regClass (VirtualRegHi u) = RcInteger
483 regClass (VirtualRegD u) = RcDouble
484 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
485 (ppr (VirtualRegF u))
488 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
489 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
491 showReg :: RegNo -> String
493 = if n >= 0 && n < 14
495 else "%unknown_x86_real_reg_" ++ show n
500 The SPARC has 64 registers of interest; 32 integer registers and 32
501 floating point registers. The mapping of STG registers to SPARC
502 machine registers is defined in StgRegs.h. We are, of course,
503 prepared for any eventuality.
505 The whole fp-register pairing thing on sparcs is a huge nuisance. See
506 fptools/ghc/includes/MachRegs.h for a description of what's going on
510 #if sparc_TARGET_ARCH
512 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
519 nCG_FirstFloatReg :: RegNo
520 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
522 regClass (VirtualRegI u) = RcInteger
523 regClass (VirtualRegF u) = RcFloat
524 regClass (VirtualRegD u) = RcDouble
525 regClass (RealReg i) | i < 32 = RcInteger
526 | i < nCG_FirstFloatReg = RcDouble
527 | otherwise = RcFloat
529 showReg :: RegNo -> String
531 | n >= 0 && n < 8 = "%g" ++ show n
532 | n >= 8 && n < 16 = "%o" ++ show (n-8)
533 | n >= 16 && n < 24 = "%l" ++ show (n-16)
534 | n >= 24 && n < 32 = "%i" ++ show (n-24)
535 | n >= 32 && n < 64 = "%f" ++ show (n-32)
536 | otherwise = "%unknown_sparc_real_reg_" ++ show n
538 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
540 f6 = RealReg (fReg 6)
541 f8 = RealReg (fReg 8)
542 f22 = RealReg (fReg 22)
543 f26 = RealReg (fReg 26)
544 f27 = RealReg (fReg 27)
547 -- g0 is useful for codegen; is always zero, and writes to it vanish.
548 g0 = RealReg (gReg 0)
549 g1 = RealReg (gReg 1)
550 g2 = RealReg (gReg 2)
552 -- FP, SP, int and float return (from C) regs.
553 fp = RealReg (iReg 6)
554 sp = RealReg (oReg 6)
555 o0 = RealReg (oReg 0)
556 o1 = RealReg (oReg 1)
557 f0 = RealReg (fReg 0)
558 f1 = RealReg (fReg 1)
563 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
567 #if powerpc_TARGET_ARCH
571 regClass (VirtualRegI u) = RcInteger
572 regClass (VirtualRegHi u) = RcInteger
573 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
574 (ppr (VirtualRegF u))
575 regClass (VirtualRegD u) = RcDouble
576 regClass (RealReg i) | i < 32 = RcInteger
577 | otherwise = RcDouble
579 showReg :: RegNo -> String
581 | n >= 0 && n <= 31 = "%r" ++ show n
582 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
583 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
590 f1 = RealReg $ fReg 1
591 f20 = RealReg $ fReg 20
592 f21 = RealReg $ fReg 21
596 Redefine the literals used for machine-registers with non-numeric
597 names in the header files. Gag me with a spoon, eh?
600 #if alpha_TARGET_ARCH
650 #if sparc_TARGET_ARCH
718 #if powerpc_TARGET_ARCH
752 #ifdef darwin_TARGET_OS
822 -- allMachRegs is the complete set of machine regs.
823 allMachRegNos :: [RegNo]
825 = IF_ARCH_alpha( [0..63],
826 IF_ARCH_i386( [0..13],
827 IF_ARCH_sparc( ([0..31]
828 ++ [f0,f2 .. nCG_FirstFloatReg-1]
829 ++ [nCG_FirstFloatReg .. f31]),
830 IF_ARCH_powerpc([0..63],
833 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
834 -- i.e., these are the regs for which we are prepared to allow the
835 -- register allocator to attempt to map VRegs to.
836 allocatableRegs :: [RegNo]
838 = let isFree i = isFastTrue (freeReg i)
839 in filter isFree allMachRegNos
841 -- these are the regs which we cannot assume stay alive over a
843 callClobberedRegs :: [Reg]
846 #if alpha_TARGET_ARCH
847 [0, 1, 2, 3, 4, 5, 6, 7, 8,
848 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
849 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
850 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
851 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
852 #endif /* alpha_TARGET_ARCH */
854 -- caller-saves registers
855 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
856 #endif /* i386_TARGET_ARCH */
857 #if sparc_TARGET_ARCH
860 [oReg i | i <- [0..5]] ++
861 [gReg i | i <- [1..7]] ++
862 [fReg i | i <- [0..31]] )
863 #endif /* sparc_TARGET_ARCH */
864 #if powerpc_TARGET_ARCH
866 map RealReg (0:[2..12] ++ map fReg [0..13])
867 #elif linux_TARGET_OS
868 map RealReg (0:[2..13] ++ map fReg [0..13])
870 #endif /* powerpc_TARGET_ARCH */
873 -- argRegs is the set of regs which are read for an n-argument call to C.
874 -- For archs which pass all args on the stack (x86), is empty.
875 -- Sparc passes up to the first 6 args in regs.
876 -- Dunno about Alpha.
877 argRegs :: RegNo -> [Reg]
880 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
883 #if alpha_TARGET_ARCH
885 argRegs 1 = freeMappedRegs [16, fReg 16]
886 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
887 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
888 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
889 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
890 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
891 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
892 #endif /* alpha_TARGET_ARCH */
894 #if sparc_TARGET_ARCH
896 argRegs 1 = map (RealReg . oReg) [0]
897 argRegs 2 = map (RealReg . oReg) [0,1]
898 argRegs 3 = map (RealReg . oReg) [0,1,2]
899 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
900 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
901 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
902 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
903 #endif /* sparc_TARGET_ARCH */
905 #if powerpc_TARGET_ARCH
907 argRegs 1 = map RealReg [3]
908 argRegs 2 = map RealReg [3,4]
909 argRegs 3 = map RealReg [3..5]
910 argRegs 4 = map RealReg [3..6]
911 argRegs 5 = map RealReg [3..7]
912 argRegs 6 = map RealReg [3..8]
913 argRegs 7 = map RealReg [3..9]
914 argRegs 8 = map RealReg [3..10]
915 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
916 #endif /* powerpc_TARGET_ARCH */
919 -- all of the arg regs ??
920 #if alpha_TARGET_ARCH
921 allArgRegs :: [(Reg, Reg)]
922 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
923 #endif /* alpha_TARGET_ARCH */
925 #if sparc_TARGET_ARCH
927 allArgRegs = map RealReg [oReg i | i <- [0..5]]
928 #endif /* sparc_TARGET_ARCH */
932 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
935 #if powerpc_TARGET_ARCH
937 allArgRegs = map RealReg [3..10]
938 allFPArgRegs :: [Reg]
940 allFPArgRegs = map (RealReg . fReg) [1..13]
941 #elif linux_TARGET_OS
942 allFPArgRegs = map (RealReg . fReg) [1..8]
944 #endif /* powerpc_TARGET_ARCH */
948 freeReg :: RegNo -> FastBool
950 #if alpha_TARGET_ARCH
951 freeReg 26 = fastBool False -- return address (ra)
952 freeReg 28 = fastBool False -- reserved for the assembler (at)
953 freeReg 29 = fastBool False -- global pointer (gp)
954 freeReg 30 = fastBool False -- stack pointer (sp)
955 freeReg 31 = fastBool False -- always zero (zeroh)
956 freeReg 63 = fastBool False -- always zero (f31)
960 freeReg esp = fastBool False -- %esp is the C stack pointer
963 #if sparc_TARGET_ARCH
964 freeReg g0 = fastBool False -- %g0 is always 0.
965 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
966 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
967 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
968 freeReg i6 = fastBool False -- %i6 is our frame pointer.
969 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
970 freeReg o6 = fastBool False -- %o6 is our stack pointer.
971 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
972 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
973 freeReg f1 = fastBool False
976 #if powerpc_TARGET_ARCH
977 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
978 freeReg 1 = fastBool False -- The Stack Pointer
979 #if !darwin_TARGET_OS
980 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
981 freeReg 2 = fastBool False
986 freeReg REG_Base = fastBool False
989 freeReg REG_R1 = fastBool False
992 freeReg REG_R2 = fastBool False
995 freeReg REG_R3 = fastBool False
998 freeReg REG_R4 = fastBool False
1001 freeReg REG_R5 = fastBool False
1004 freeReg REG_R6 = fastBool False
1007 freeReg REG_R7 = fastBool False
1010 freeReg REG_R8 = fastBool False
1013 freeReg REG_F1 = fastBool False
1016 freeReg REG_F2 = fastBool False
1019 freeReg REG_F3 = fastBool False
1022 freeReg REG_F4 = fastBool False
1025 freeReg REG_D1 = fastBool False
1028 freeReg REG_D2 = fastBool False
1031 freeReg REG_Sp = fastBool False
1034 freeReg REG_Su = fastBool False
1037 freeReg REG_SpLim = fastBool False
1040 freeReg REG_Hp = fastBool False
1043 freeReg REG_HpLim = fastBool False
1045 freeReg n = fastBool True
1048 -- -----------------------------------------------------------------------------
1049 -- Information about global registers
1051 baseRegOffset :: GlobalReg -> Int
1053 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1054 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1055 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1056 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1057 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1058 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1059 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1060 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1061 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1062 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1063 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1064 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1065 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1066 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1067 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1068 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1069 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1070 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1071 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1072 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1073 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1074 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1075 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1076 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1077 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1078 baseRegOffset GCFun = oFFSET_stgGCFun
1080 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1081 baseRegOffset _ = panic "baseRegOffset:other"
1085 -- | Returns 'True' if this global register is stored in a caller-saves
1086 -- machine register.
1088 callerSaves :: GlobalReg -> Bool
1090 #ifdef CALLER_SAVES_Base
1091 callerSaves BaseReg = True
1093 #ifdef CALLER_SAVES_R1
1094 callerSaves (VanillaReg _ ILIT(1)) = True
1096 #ifdef CALLER_SAVES_R2
1097 callerSaves (VanillaReg _ ILIT(2)) = True
1099 #ifdef CALLER_SAVES_R3
1100 callerSaves (VanillaReg _ ILIT(3)) = True
1102 #ifdef CALLER_SAVES_R4
1103 callerSaves (VanillaReg _ ILIT(4)) = True
1105 #ifdef CALLER_SAVES_R5
1106 callerSaves (VanillaReg _ ILIT(5)) = True
1108 #ifdef CALLER_SAVES_R6
1109 callerSaves (VanillaReg _ ILIT(6)) = True
1111 #ifdef CALLER_SAVES_R7
1112 callerSaves (VanillaReg _ ILIT(7)) = True
1114 #ifdef CALLER_SAVES_R8
1115 callerSaves (VanillaReg _ ILIT(8)) = True
1117 #ifdef CALLER_SAVES_F1
1118 callerSaves (FloatReg 1#) = True
1120 #ifdef CALLER_SAVES_F2
1121 callerSaves (FloatReg 2#) = True
1123 #ifdef CALLER_SAVES_F3
1124 callerSaves (FloatReg 3#) = True
1126 #ifdef CALLER_SAVES_F4
1127 callerSaves (FloatReg 4#) = True
1129 #ifdef CALLER_SAVES_D1
1130 callerSaves (DoubleReg 1#) = True
1132 #ifdef CALLER_SAVES_D2
1133 callerSaves (DoubleReg 2#) = True
1135 #ifdef CALLER_SAVES_L1
1136 callerSaves (LongReg _ ILIT(1)) = True
1138 #ifdef CALLER_SAVES_Sp
1139 callerSaves Sp = True
1141 #ifdef CALLER_SAVES_SpLim
1142 callerSaves SpLim = True
1144 #ifdef CALLER_SAVES_Hp
1145 callerSaves Hp = True
1147 #ifdef CALLER_SAVES_HpLim
1148 callerSaves HpLim = True
1150 #ifdef CALLER_SAVES_CurrentTSO
1151 callerSaves CurrentTSO = True
1153 #ifdef CALLER_SAVES_CurrentNursery
1154 callerSaves CurrentNursery = True
1156 callerSaves _ = False
1159 -- | Returns 'Nothing' if this global register is not stored
1160 -- in a real machine register, otherwise returns @'Just' reg@, where
1161 -- reg is the machine register it is stored in.
1163 globalRegMaybe :: GlobalReg -> Maybe Reg
1166 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1169 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1172 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1175 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1178 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1181 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1184 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1187 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1190 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1193 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1196 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1199 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1202 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1205 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1208 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1211 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1214 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1217 globalRegMaybe Sp = Just (RealReg REG_Sp)
1220 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1223 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1226 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1229 globalRegMaybe Hp = Just (RealReg REG_Hp)
1232 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1234 #ifdef REG_CurrentTSO
1235 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1237 #ifdef REG_CurrentNursery
1238 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1240 globalRegMaybe _ = Nothing